CN116504181A - Display control circuit, display control method, display panel and display device - Google Patents

Display control circuit, display control method, display panel and display device Download PDF

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Publication number
CN116504181A
CN116504181A CN202310165141.8A CN202310165141A CN116504181A CN 116504181 A CN116504181 A CN 116504181A CN 202310165141 A CN202310165141 A CN 202310165141A CN 116504181 A CN116504181 A CN 116504181A
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China
Prior art keywords
circuit
control
voltage
control signal
signal
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CN202310165141.8A
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Chinese (zh)
Inventor
龚庆
陆旭
朱俊锋
张仲瑞
王梓鉴
石慧男
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BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
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Priority to CN202310165141.8A priority Critical patent/CN116504181A/en
Publication of CN116504181A publication Critical patent/CN116504181A/en
Pending legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

The invention provides a display control circuit, a display control method, a display panel and a display device. The display control circuit comprises a pixel circuit, a driving integrated circuit and a picture generator; the picture generator judges whether the current picture is a dynamic picture or a static picture according to the current data voltage; the display control circuit is used for controlling the potential of the compensation control signal to be an effective voltage when the potential of the data providing indication signal is an effective voltage after the refresh frame is finished and controlling the potential of the compensation control signal to be an effective voltage when the current picture is a static picture and before the next effective voltage period of the data providing indication signal and is also used for controlling the potential of the compensation control signal to be an effective voltage when the potential of the data providing indication signal is an effective voltage after the refresh frame is finished and at least part of stages in the next effective voltage period of the light emitting control signal when the previous picture is a dynamic picture. The invention can control and realize fine down-conversion operation.

Description

Display control circuit, display control method, display panel and display device
Technical Field
The present invention relates to the field of display technologies, and in particular, to a display control circuit, a display control method, a display panel, and a display device.
Background
The relevant Frame Skip down-conversion can only be down-converted based on integer multiples of the fundamental frequency (e.g. when the fundamental frequency is 120Hz, the refresh frequency can only be down to 120Hz/n, where n is a positive integer), and no fine down-conversion operation can be achieved.
Disclosure of Invention
The invention mainly aims to provide a display control circuit, a display control method, a display panel and a display device, which solve the problem that fine down-conversion operation cannot be controlled in the prior art.
In one aspect, an embodiment of the present invention provides a display control circuit, which is included in a display panel, the display panel further including a pixel circuit, a driving integrated circuit, and a picture generator; the drive integrated circuit is used for providing a data providing indication signal; the pixel circuit is connected with a compensation control signal and a light-emitting control signal and is used for carrying out threshold voltage compensation under the control of the compensation control signal and carrying out light-emitting control under the control of the light-emitting control signal;
the display control circuit is used for controlling the frequency of the data providing indication signal to be a first frequency after the refresh frame is finished, wherein the first frequency is 1/n times of the light-emitting control frequency, and n is a positive integer; the light-emitting control frequency is the frequency of the light-emitting control signal;
The picture generator is used for judging whether the current picture is a dynamic picture or a static picture according to the current data voltage and providing a judging result to the display control circuit;
the display control circuit is used for controlling the potential of the compensation control signal to be kept at the invalid voltage before the next valid voltage time period of the data providing indication signal when the judging result indicates that the current picture is a static picture when the potential of the data providing indication signal is the valid voltage after the refresh frame is finished, and controlling the potential of the compensation control signal to be the valid voltage when the judging result indicates that the current picture is the dynamic picture and at least part of the stages in the next invalid voltage time period of the light emitting control signal when the potential of the data providing indication signal is the valid voltage after the refresh frame is finished.
Optionally, the pixel circuit is further connected to a data writing control signal, and the display control circuit is further configured to, when the potential of the data providing indication signal is an effective voltage after the refresh frame is finished, when the judgment result indicates that the current picture is a still picture, control the potential of the data writing control signal to be maintained at an ineffective voltage before a next effective voltage period of the data providing indication signal, and is further configured to, when the potential of the data providing indication signal is an effective voltage after the refresh frame is finished, control the potential of the data writing control signal to be an effective voltage at a next at least partial stage in the ineffective voltage period of the light emitting control signal when the judgment result indicates that the current picture is a dynamic picture.
Optionally, the pixel circuit is also connected with a data writing control signal;
the display control circuit is used for controlling the frequency of the data writing control signal to be a second frequency, and the second frequency is a fixed frequency.
Optionally, the second frequency is 1/m times of the light emission control frequency, and m is a positive integer.
Optionally, the pixel circuit is further connected to a first initial control signal, and is used for controlling to initialize the potential of the control end of the driving circuit in the pixel circuit under the control of the first initial control signal;
the display control circuit is used for controlling the potential of the first initial control signal to be maintained to be an invalid voltage before the next valid voltage time period of the data providing indication signal when the judging result indicates that the current picture is a static picture when the potential of the data providing indication signal is the valid voltage after the refresh frame is finished, and controlling the potential of the first initial control signal to be the valid voltage when the judging result indicates that the current picture is a dynamic picture when the potential of the data providing indication signal is the valid voltage after the refresh frame is finished.
Optionally, the pixel circuit is further connected to a second initial control signal, and is used for controlling to initialize the potential of the first pole of the light-emitting element in the pixel circuit under the control of the second initial control signal;
the display control circuit is used for controlling the frequency of the second initial control signal to be a third frequency, and the third frequency is a fixed frequency.
Optionally, the third frequency is 1/a times of the light emission control frequency, and m is a positive integer.
In a second aspect, an embodiment of the present invention provides a display control method, which is applied to the above display control circuit, where the display control method includes: after the end of the refresh frame,
the display control circuit controls the frequency of the data providing indication signal to be a first frequency which is 1/n times of the light emitting control frequency, wherein n is a positive integer;
the picture generator judges the current picture as a dynamic picture or a static picture according to the current data voltage and provides a judging result to the display control circuit;
when the judgment result indicates that the current picture is a static picture when the potential of the data providing indication signal is an effective voltage, the display control circuit controls the potential of the compensation control signal to be maintained at an ineffective voltage before the next effective voltage period of the data providing indication signal; when the judgment result indicates that the current picture is a dynamic picture when the potential of the data providing indication signal is an effective voltage, the display control circuit controls the potential of the compensation control signal to be an effective voltage in at least part of the next invalid voltage period of the light emission control signal.
Optionally, the pixel circuit is further connected to a data writing control signal, and the display control method further includes: after the end of the refresh frame,
when the judgment result indicates that the current picture is a static picture when the potential of the data providing indication signal is an effective voltage, the display control circuit controls the potential of the data writing control signal to be maintained at an ineffective voltage before the next effective voltage period of the data providing indication signal;
when the judgment result indicates that the current picture is a dynamic picture when the potential of the data supply indication signal is an effective voltage, the display control circuit controls the potential of the data writing control signal to be an effective voltage in at least part of the next invalid voltage period of the light emission control signal.
In a third aspect, an embodiment of the present invention provides a display panel, including the display control circuit described above.
Optionally, the display panel according to at least one embodiment of the present invention further includes a pixel circuit, a driving integrated circuit, and a picture generator;
the drive integrated circuit is used for providing a data providing indication signal;
the picture generator is used for judging whether the current picture is a dynamic picture or a static picture according to the current data voltage and providing a judging result to the display control circuit;
The pixel circuit comprises a light emitting element, a driving circuit, a compensation control circuit, a first light emitting control circuit and a second light emitting control circuit;
the control end of the driving circuit is electrically connected with a first node, the first end of the driving circuit is electrically connected with a second power-saving node, the second end of the driving circuit is electrically connected with a third node, and the driving circuit is used for controlling the communication between the second node and the third node under the control of the potential of the first node;
the control end of the compensation control circuit is electrically connected with the compensation control end, and the compensation control circuit is respectively electrically connected with the first node and the third node and is used for controlling the communication between the first node and the third node under the control of a compensation control signal provided by the compensation control end;
the first light emitting control circuit is respectively and electrically connected with the light emitting control end, the power supply voltage end and the second node and is used for controlling the communication between the power supply voltage end and the second node under the control of a light emitting control signal provided by the light emitting control end;
the second light-emitting control circuit is respectively and electrically connected with the light-emitting control end, the third node and the first electrode of the light-emitting element and is used for controlling the communication between the third node and the first electrode of the light-emitting element under the control of the light-emitting control signal;
The second pole of the light emitting element is electrically connected with the low voltage terminal.
Optionally, the pixel circuit further includes a data writing circuit, a first initializing circuit, and a second initializing circuit;
the data writing circuit is respectively and electrically connected with the writing control end, the data line and the second node and is used for writing the data voltage provided by the data line into the second node under the control of the data writing control signal provided by the writing control end;
the first initialization circuit is electrically connected with the first initial control end, the first initial voltage end and the first node respectively and is used for writing the first initial voltage provided by the first initial voltage end into the first node under the control of a first initial control signal provided by the first initial control end;
the second initializing circuit is electrically connected with the second initial control end, the second initial voltage end and the first pole of the light-emitting element respectively, and is used for writing the second initial voltage provided by the second initial voltage end into the first pole of the light-emitting element under the control of the second initial control signal provided by the second initial control end.
In a fourth aspect, an embodiment of the present invention provides a display device including the display panel described above.
Optionally, the pixel circuit in the display panel includes a compensation control circuit, a data writing circuit, a first initializing circuit and a second initializing circuit; the display device comprises a first GOA module and a second GOA module;
the first GOA module is used for providing a compensation control signal for the compensation control circuit and providing a first initial control signal for the first initialization circuit;
the second GOA module is used for providing a data writing control signal for the data writing circuit and providing a second initial control signal for the second initializing circuit.
Optionally, the pixel circuit in the display panel includes a compensation control circuit, a data writing circuit, a first initializing circuit and a second initializing circuit; the display device comprises a first GOA module, a second GOA module and a third GOA module;
the first GOA module is used for providing a compensation control signal for the compensation control circuit and providing a first initial control signal for the first initialization circuit;
the second GOA module is used for providing a data writing control signal for the data writing circuit;
the third GOA module provides a second initial control signal for the second initialization circuit.
Compared with the prior art, the display control circuit, the display control method, the display panel and the display device can control and realize fine down-conversion operation.
Drawings
FIG. 1 is a block diagram of a display panel according to at least one embodiment of the present invention;
FIG. 2 is a block diagram of a display panel according to at least one embodiment of the present invention;
FIG. 3 is a circuit diagram of at least one embodiment of a pixel circuit in at least one embodiment of the invention;
FIG. 4 is a timing diagram illustrating operation of at least one embodiment of the pixel circuit shown in FIG. 3;
FIG. 5 is a circuit diagram of at least one embodiment of a pixel circuit in at least one embodiment of the invention;
FIG. 6 is a timing diagram illustrating operation of at least one embodiment of the pixel circuit shown in FIG. 5;
FIG. 7 is a circuit diagram of at least one embodiment of a pixel circuit in at least one embodiment of the invention;
FIG. 8 is a timing diagram illustrating operation of at least one embodiment of the pixel circuit shown in FIG. 7;
FIG. 9 is a circuit diagram of at least one embodiment of a pixel circuit in at least one embodiment of the invention;
FIG. 10 is a timing diagram illustrating operation of at least one embodiment of the pixel circuit shown in FIG. 9;
FIG. 11 is a timing diagram illustrating operation of at least one embodiment of the AND gate of FIG. 12;
Fig. 12 is a block diagram of at least one embodiment of an and gate.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The transistors used in all embodiments of the present invention may be thin film transistors or field effect transistors or other devices having the same characteristics. In the embodiment of the invention, in order to distinguish two poles of the transistor except the gate, one pole is called a first electrode, and the other pole is called a second electrode.
In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; alternatively, the first electrode may be a source electrode and the second electrode may be a drain electrode.
The display control circuit according to the embodiment of the invention is included in a display panel, as shown in fig. 1, the display panel further includes a pixel circuit P1, a driving integrated circuit D0, and a picture generator S1; the driving integrated circuit D0 is configured to provide a data providing indication signal TE; the pixel circuit P1 is connected with a compensation control signal SC and a light emission control signal EM, and is used for carrying out threshold voltage compensation under the control of the compensation control signal SC and carrying out light emission control under the control of the light emission control signal EM;
The display control circuit 10 is configured to control the frequency of the data providing indication signal TE to be a first frequency after the refresh frame is finished, where n is a positive integer, and the first frequency is 1/n times the light emission control frequency; the light emission control frequency is the frequency of the light emission control signal EM;
the picture generator S1 is configured to determine that the current picture is a dynamic picture or a static picture according to the current data voltage, and provide the determination result to the display control circuit 10;
the display control circuit 10 is configured to control the potential of the compensation control signal SC to be maintained at an inactive voltage before a next active voltage period of the data supply indication signal TE when the determination result indicates that the current picture is a still picture when the potential of the data supply indication signal TE is an active voltage after the end of the refresh frame, and to control the potential of the compensation control signal SC to be an active voltage at least at a part of a next inactive voltage period of the light emission control signal EM when the determination result indicates that the current picture is a dynamic picture when the potential of the data supply indication signal TE is an active voltage after the end of the refresh frame.
In at least one embodiment of the present invention, the data providing indication signal TE may have a potential of an effective voltage finger: the potential of TE is high voltage;
the period of the effective voltage of the data providing indication signal TE may be: a period in which the potential of TE is maintained at a high voltage;
the maintaining of the potential of the compensation control signal SC to the inactive voltage may be: when the transistor controlled by the compensation control signal SC is an n-type transistor, the potential of SC is low voltage; when the transistor controlled by the compensation control signal SC is a p-type transistor, the potential of the SC is high voltage;
the potential of the compensation control signal SC maintained at the effective voltage may be: when the transistor controlled by the compensation control signal SC is an n-type transistor, the potential of SC is a high voltage; when the transistor controlled by the compensation control signal SC is a p-type transistor, the potential of SC is low;
when the transistor controlled by the emission control signal EM is a p-type transistor, the inactive voltage period of the emission control signal EM may refer to: the light emission control signal EM continues for a period of time of a high voltage signal;
when the transistor controlled by the emission control signal EM is an n-type transistor, the inactive voltage period of the emission control signal EM may refer to: the light emission control signal EM continues for a period of low voltage signal.
The embodiment of the invention relates to a timing sequence design scheme capable of realizing fine frequency reduction, and compared with the related Frame Skip frequency reduction which can only be based on integer multiple of a fundamental frequency (for example, when the fundamental frequency is 120Hz, the refresh frequency can only be reduced to 120Hz/n, wherein n is a positive integer), the display control circuit of the embodiment of the invention can control the implementation of finer frequency reduction operation, for example, when the fundamental frequency is 120Hz, the display control circuit of the embodiment of the invention can reduce the refresh frequency to 240Hz/b, and b can be an integer greater than 2, namely, can reduce the refresh frequency to 80Hz, 60Hz, 48Hz or 40Hz, or can reduce the refresh frequency to 360Hz/c, and c can be an integer greater than 3, for example, can reduce the refresh frequency to 90Hz, 72Hz, 60Hz or 51.4Hz.
When the display control circuit of the embodiment of the invention works, after the refresh frame is finished, the display control circuit enters a hold frame stage, in the hold frame stage, data voltage refresh can be performed in a time period when the potential of any one of the light-emitting control signals is invalid voltage, and the higher the frequency of the light-emitting control signal is, the better the frequency of the light-emitting control signal is, for example, when the fundamental frequency is 120Hz, the frequency of the light-emitting control signal can be 240Hz, 360Hz or 480Hz.
The display control circuit provided by the embodiment of the invention is simultaneously applicable to LTPO (low temperature polycrystalline oxide) display products and LTPS (low temperature polycrystalline silicon) display products.
The embodiment of the invention can realize the fine and smooth frequency-reducing function, can enable the picture refreshing of the terminal product to be more timely, and the picture of the GPU (graphic processing unit) at the whole machine end can be displayed more timely after being rendered, so that the picture connection is better, and the user experience is better.
In at least one embodiment of the present invention, the pixel circuit is further connected to a data writing control signal, and the display control circuit is further configured to, when the potential of the data providing indication signal is an effective voltage after the end of the refresh frame, control the potential of the data writing control signal to be an effective voltage before a next effective voltage period of the data providing indication signal when the determination result indicates that the current picture is a still picture, and further configured to, when the potential of the data providing indication signal is an effective voltage after the end of the refresh frame, control the potential of the data writing control signal to be an effective voltage at least in part of a next ineffective voltage period of the light emitting control signal when the determination result indicates that the current picture is a dynamic picture, so as to perform data voltage writing.
In at least one embodiment of the present invention, the maintaining of the potential of the data write control signal to the inactive voltage finger may be:
when the transistor controlled by the data writing control signal is an n-type transistor, the potential of the data writing control signal is low voltage; when the transistor controlled by the data writing control signal is a p-type transistor, the potential of the data writing control signal is high voltage; the maintaining of the potential of the data write control signal to the effective voltage finger may be:
when the transistor controlled by the data writing control signal is an n-type transistor, the potential of the data writing control signal is high voltage; when the transistor controlled by the data writing control signal is a p-type transistor, the potential of the data writing control signal is a low voltage.
Optionally, the pixel circuit is also connected with a data writing control signal;
the display control circuit is used for controlling the frequency of the data writing control signal to be a second frequency, and the second frequency is a fixed frequency.
Optionally, the second frequency is 1/m times of the light emission control frequency, and m is a positive integer.
In at least one embodiment of the present invention, the pixel circuit is further connected to a first initial control signal, and is configured to control to initialize a potential of a control end of a driving circuit in the pixel circuit under control of the first initial control signal;
The display control circuit is used for controlling the potential of the first initial control signal to be maintained to be an invalid voltage before the next valid voltage time period of the data providing indication signal when the judging result indicates that the current picture is a static picture when the potential of the data providing indication signal is the valid voltage after the refresh frame is finished, and controlling the potential of the first initial control signal to be the valid voltage when the judging result indicates that the current picture is a dynamic picture when the potential of the data providing indication signal is the valid voltage after the refresh frame is finished.
As shown in fig. 2, on the basis of at least one embodiment of the display control circuit shown in fig. 1, the pixel circuit P1 is further connected to a first initial control signal SI1, and is configured to control to initialize a potential of a control terminal of a driving circuit in the pixel circuit P1 under the control of the first initial control signal SI 1;
the display control circuit 10 is configured to control the potential of the first initial control signal SI1 to be maintained at an inactive voltage before a next active voltage period of the data supply indication signal TE when the determination result indicates that the current picture is a still picture when the potential of the data supply indication signal TE is an active voltage after the end of the refresh frame, and to control the potential of the first initial control signal SI1 to be an active voltage at least in part of the next inactive voltage period of the light emission control signal EM when the determination result indicates that the current picture is a moving picture when the potential of the data supply indication signal T3 is an active voltage after the end of the refresh frame.
Optionally, the pixel circuit is further connected to a second initial control signal, and is used for controlling to initialize the potential of the first pole of the light-emitting element in the pixel circuit under the control of the second initial control signal;
the display control circuit is used for controlling the frequency of the second initial control signal to be a third frequency, and the third frequency is a fixed frequency.
Optionally, the third frequency is 1/a times of the light emission control frequency, and m is a positive integer.
As shown in fig. 3, in at least one embodiment of the present invention, the pixel circuit may include a light emitting element, a driving circuit, a data writing circuit, a compensation control circuit, a first light emitting control circuit, a second light emitting control circuit, a first initialization circuit, a second initialization circuit, and a tank circuit; the light emitting element may be an organic light emitting diode O1;
the first initialization circuit comprises a first transistor T1, the compensation control circuit comprises a second transistor, the driving circuit comprises a driving transistor T3, the data writing circuit comprises a fourth transistor T4, the first light emitting control circuit comprises a fifth transistor T5, the second light emitting control circuit comprises a sixth transistor T6, the second initialization circuit comprises a seventh transistor T7, and the energy storage circuit comprises a storage capacitor Cst;
The grid electrode of the T1 is electrically connected with a first initial control end, and a first initial control signal accessed by the first initial control end is an N-1 th-level first driving signal GateN (N); the source electrode of the T1 is electrically connected with the first initial voltage end I1, and the drain electrode of the T1 is electrically connected with the first node N1; the first initial voltage terminal I1 is configured to provide a first initial voltage Vinit1; n is a positive integer;
the grid electrode of the T2 is electrically connected with the compensation control end, and an initial control signal accessed by the initial control end is an N-th-stage first driving signal GateN (N+1); the source electrode of the T2 is electrically connected with the first node N1, and the drain electrode of the T2 is electrically connected with the third node N3;
the grid electrode of the T3 is electrically connected with the first node N1, the source electrode of the T3 is electrically connected with the second node N2, and the drain electrode of the T3 is electrically connected with the third node N3;
the grid electrode of the T4 is electrically connected with the writing control end, the source electrode of the T4 is electrically connected with the Data line Data, and the drain electrode of the T4 is electrically connected with the second node N2; the data writing control signal accessed by the writing control terminal is an N+1th-stage second driving signal GateP (N+1);
the grid electrode of the T5 is electrically connected with a light emitting control end, and the light emitting control end is connected with a light emitting control signal EM; the source electrode of the T5 is electrically connected with the power supply voltage end VDD, and the drain electrode of the T5 is electrically connected with the second node N2;
The grid electrode of the T6 is electrically connected with the light-emitting control end, the source electrode of the T6 is electrically connected with the third node N3, the drain electrode of the T6 is electrically connected with the anode of the organic light-emitting diode O1, and the cathode of the organic light-emitting diode O1 is electrically connected with the low-voltage end VSS;
the grid electrode of the T7 is electrically connected with a second initial control end, and a second initial control signal accessed by the second initial control end is an N-th-stage second driving signal GateP (N); the source electrode of the T7 is electrically connected with the second initial voltage end I2, and the drain electrode of the T7 is electrically connected with the anode of the O1; the second initial voltage terminal I2 is configured to provide a second initial voltage Vinit2;
the first terminal of Cst is electrically connected to the first node N1, and the second terminal of Cst is electrically connected to the power voltage terminal VDD.
In at least one embodiment of the pixel circuit shown in FIG. 3, T1 and T2 are n-type transistors and T3, T4, T5, T6 and T7 are p-type transistors.
In at least one embodiment of the pixel circuit shown in fig. 3, a first GOA module may provide a compensation control signal for the compensation control circuit and a first initial control signal for the first initialization circuit; the second GOA module can be used for providing a data writing control signal for the data writing circuit and providing a second initial control signal for the second initializing circuit; the light emission control signals may be provided to the first light emission control circuit and the second light emission control circuit by the light emission control signal generation module.
In fig. 4, a TE signal is denoted by TE, and the TE signal provides an indication signal for data, and when the TE signal is a signal provided from the driving integrated circuit to the main board, the main board is indicated to provide a data voltage to the driving integrated circuit when the TE signal has an upward pulse; an MCU (micro controller) is arranged in the main board, a picture generator is arranged in the MUC, the picture generator can judge whether the picture to be displayed is a dynamic picture or a static picture, if the picture is the static picture, the data does not need to be refreshed, and if the picture is the dynamic picture, the data needs to be refreshed.
As shown in fig. 4, at least one embodiment of the pixel circuit shown in fig. 3 is in operation with a fundamental frequency of 120Hz, a first refresh frame labeled Ts1, and a frequency of the emission control signal EM of 240Hz; in the first refresh frame Ts1, the frequency of the TE signal is 120Hz;
after the first refreshing frame Ts1 is finished, the frequency of the TE signal is changed to 240Hz, and the picture generator judges that the current picture to be displayed is a dynamic picture in the second upward pulse of the TE signal, and the second frame is also a refreshing frame;
in the second refresh frame Ts2, in the first high level sustain period of EM, the potential of gate (N) and the potential of gate (n+1) rise successively to control T1 to turn on first to initialize the potential of the first node N1, then control T2 to turn on to control communication between the first node N1 and the third node N3, T4 is turned on under control of gate (n+1) at least a part of the time period in which T2 is turned on to write the Data voltage Vdata supplied from the Data line Data to the second node and to write the first node N1 through turned on T2 to charge Cst, and T7 is turned on to initialize the anode of O1 through Vinit2 before T4 is turned on;
In the second refresh frame Ts2, the frequency of the TE signal is 120Hz;
after the second refreshing frame Ts2 is finished, the frequency of the TE signal is changed to 240Hz, and the picture generator judges that the current picture to be displayed is a static picture without data voltage refreshing when the picture is in the first holding frame Tb1;
after the second refreshing frame Ts2 is finished, the picture generator judges that the current picture to be displayed is a dynamic picture in the fourth upward pulse of the TE signal, and then enters a third refreshing frame Ts3;
in the third refresh frame Ts3, in the first high level sustain period of EM, the potential of gate (N) and the potential of gate (n+1) rise successively to control T1 to turn on first to initialize the potential of the first node N1, then to control T2 to turn on to control communication between the first node N1 and the third node N3, T4 is turned on under the control of gate (n+1) at least part of the time period in which T2 is turned on to write the Data voltage Vdata supplied by the Data line Data to the second node and to write the first node N1 through turned on T2 to charge Cst, and T7 is turned on to initialize the anode of O1 through Vinit2 before T4 is turned on;
After the third refreshing frame Ts3 is finished, the frequency of the TE signal is changed to 240Hz, and the picture generator judges that the current picture to be displayed is a static picture and does not need to carry out data voltage refreshing when the picture generator is positioned in the second holding frame Tb2; in the seventh pulse of the TE signal, the picture generator judges that the current picture to be displayed is a dynamic picture, and enters a fourth refreshing frame Ts4;
in the fourth refresh frame Ts4, in the first high level sustain period of EM, the potential of gate (N) and the potential of gate (n+1) rise successively to control T1 to turn on first to initialize the potential of the first node N1, then to control T2 to turn on to control communication between the first node N1 and the third node N3, T4 is turned on under control of gate (n+1) at least a part of the time period in which T2 is turned on to write the Data voltage Vdata supplied from the Data line Data to the second node and to write the first node N1 through turned-on T2 to charge Cst, and T7 is turned on to initialize the anode of O1 through Vinit2 before T4 is turned on;
after the fourth refresh frame Ts4 is finished, the frequency of the TE signal becomes 240Hz, and the picture generator judges that the current picture to be displayed is a still picture and does not need to perform data voltage refresh in the eighth pulse of the TE signal, the ninth pulse of the TE signal, the tenth pulse of the TE signal, the eleventh pulse of the TE signal, the twelfth pulse of the TE signal and the thirteenth pulse of the TE signal, and the period of time is the third holding frame Tb3;
In each holding frame, gateN (n+1) and GateN (N) are both low voltage signals.
As shown in fig. 4, the refresh frequency of the pixel circuit is 120Hz, 80Hz, and 60Hz in this order.
In fig. 4, a communication interface control signal is denoted by the reference numeral MIPI, and when MIPI is a clock signal, it is indicated that a data voltage can be transmitted through a communication interface.
As shown in fig. 4, the frequency of the gate (N) and the frequency of the gate (n+1) are both 240Hz to control the high-frequency turn-on of T7, and the high-frequency reset of the anode of O1 is performed to improve the flicker phenomenon.
As shown in fig. 5, in at least one embodiment of the present invention, the pixel circuit may include a light emitting element, a driving circuit, a data writing circuit, a compensation control circuit, a first light emitting control circuit, a second light emitting control circuit, a first initialization circuit, a second initialization circuit, and a tank circuit; the light emitting element may be an organic light emitting diode O1;
the first initialization circuit comprises a first transistor T1, the compensation control circuit comprises a second transistor, the driving circuit comprises a driving transistor T3, the data writing circuit comprises a fourth transistor T4, the first light emitting control circuit comprises a fifth transistor T5, the second light emitting control circuit comprises a sixth transistor T6, the second initialization circuit comprises a seventh transistor T7, and the energy storage circuit comprises a storage capacitor Cst;
The grid electrode of the T1 is electrically connected with a first initial control end, and a first initial control signal accessed by the first initial control end is an N-th-stage first driving signal GateN (N); the source electrode of the T1 is electrically connected with the first initial voltage end I1, and the drain electrode of the T1 is electrically connected with the first node N1; the first initial voltage terminal I1 is configured to provide a first initial voltage Vinit1; n is a positive integer;
the grid electrode of the T2 is electrically connected with the compensation control end, and an initial control signal accessed by the initial control end is an N+1st-stage first driving signal GateN (N+1); the source electrode of the T2 is electrically connected with the first node N1, and the drain electrode of the T2 is electrically connected with the third node N3;
the grid electrode of the T3 is electrically connected with the first node N1, the source electrode of the T3 is electrically connected with the second node N2, and the drain electrode of the T3 is electrically connected with the third node N3;
the grid electrode of the T4 is electrically connected with the writing control end, the source electrode of the T4 is electrically connected with the Data line Data, and the drain electrode of the T4 is electrically connected with the second node N2; the data writing control signal accessed by the writing control terminal is an N-th second driving signal GateP (N);
the grid electrode of the T5 is electrically connected with a light emitting control end, and the light emitting control end is connected with a light emitting control signal EM; the source electrode of the T5 is electrically connected with the power supply voltage end VDD, and the drain electrode of the T5 is electrically connected with the second node N2;
The grid electrode of the T6 is electrically connected with the light-emitting control end, the source electrode of the T6 is electrically connected with the third node N3, the drain electrode of the T6 is electrically connected with the anode of the organic light-emitting diode O1, and the cathode of the organic light-emitting diode O1 is electrically connected with the low-voltage end VSS;
the grid electrode of the T7 is electrically connected with a second initial control end, and a second initial control signal accessed by the second initial control end is an N-th-stage first reset signal ResetP (N); the source electrode of the T7 is electrically connected with the second initial voltage end I2, and the drain electrode of the T7 is electrically connected with the anode of the O1; the second initial voltage terminal I2 is configured to provide a second initial voltage Vinit2;
the first terminal of Cst is electrically connected to the first node N1, and the second terminal of Cst is electrically connected to the power voltage terminal VDD.
In at least one embodiment of the pixel circuit shown in FIG. 5, T1 and T2 are n-type transistors and T3, T4, T5, T6 and T7 are p-type transistors.
In at least one embodiment of the pixel circuit shown in fig. 5, a first GOA module may provide a compensation control signal for the compensation control circuit and a first initial control signal for the first initialization circuit; a second GOA module can provide a data writing control signal for the data writing circuit; a second initial control signal can be provided for the second initialization circuit by the third GOA module; the light emission control signals may be provided to the first light emission control circuit and the second light emission control circuit by the light emission control signal generation module.
As shown in fig. 6, the frequency of the nth stage first reset signal ResetP (N) may be 240Hz to control the T7 to be turned on at a high frequency, and to reset the anode of O1 at a high frequency, thereby improving the flicker phenomenon.
As shown in fig. 6, at least one embodiment of the pixel circuit shown in fig. 5 is in operation with a fundamental frequency of 120Hz, a first refresh frame labeled Ts1, and a frequency of the emission control signal EM of 240Hz; in the first refresh frame Ts1, the frequency of the TE signal is 120Hz;
after the first refreshing frame Ts1 is finished, the frequency of the TE signal is changed to 240Hz, and the picture generator judges that the current picture to be displayed is a dynamic picture in the second upward pulse of the TE signal, and the second frame is also a refreshing frame;
in the second refresh frame Ts2, in the first high level sustain period of EM, the potential of gate (N) and the potential of gate (n+1) rise successively to control T1 to be turned on first to initialize the potential of the first node N1, then control T2 to be turned on to control communication between the first node N1 and the third node N3, and T4 to be turned on under the control of gate (N) at least part of the time period in which T2 is turned on to write the Data voltage Vdata supplied from the Data line Data into the second node and to write the first node N1 through the turned-on T2 to charge Cst;
In the second refresh frame Ts2, the frequency of the TE signal is 120Hz;
after the second refreshing frame Ts2 is finished, the frequency of the TE signal is changed to 240Hz, and the picture generator judges that the current picture to be displayed is a static picture without data voltage refreshing when the picture is in the first holding frame Tb1;
after the second refreshing frame Ts2 is finished, the picture generator judges that the current picture to be displayed is a dynamic picture in the fourth upward pulse of the TE signal, and then enters a third refreshing frame Ts3;
in the third refresh frame Ts3, during the first high level sustain period of the EM, the potential of gate (N) and the potential of gate (n+1) are sequentially raised to control T1 to be turned on first to initialize the potential of the first node N1, then T2 to be turned on to control communication between the first node N1 and the third node N3, and T4 is turned on under the control of gate (N) at least a part of the time period in which T2 is turned on to write the Data voltage Vdata supplied from the Data line Data into the second node and to write the Data voltage Vdata into the first node N1 through the turned-on T2 to charge Cst;
after the third refreshing frame Ts3 is finished, the frequency of the TE signal is changed to 240Hz, and the picture generator judges that the current picture to be displayed is a static picture and does not need to carry out data voltage refreshing when the picture generator is positioned in the second holding frame Tb2; in the seventh pulse of the TE signal, the picture generator judges that the current picture to be displayed is a dynamic picture, and enters a fourth refreshing frame Ts4;
In the fourth refresh frame Ts4, during the first high level sustain period of the EM, the potential of gate (N) and the potential of gate (n+1) are sequentially raised to control T1 to be turned on first to initialize the potential of the first node N1, then T2 to be turned on to control communication between the first node N1 and the third node N3, T4 is turned on under the control of gate (N) at least a part of the time period in which T2 is turned on to write the Data voltage Vdata supplied from the Data line Data into the second node and to write the first node N1 through the turned-on T2 to charge Cst;
after the fourth refresh frame Ts4 is finished, the frequency of the TE signal becomes 240Hz, and the picture generator judges that the current picture to be displayed is a still picture and does not need to perform data voltage refresh in the eighth pulse of the TE signal, the ninth pulse of the TE signal, the tenth pulse of the TE signal, the eleventh pulse of the TE signal, the twelfth pulse of the TE signal and the thirteenth pulse of the TE signal, and the period of time is the third holding frame Tb3;
in each holding frame, gateN (n+1) and GateN (N) are both low voltage signals.
As shown in fig. 6, the refresh frequency of the pixel circuit is 120Hz, 80Hz, and 60Hz in this order.
As shown in fig. 7, in at least one embodiment of the present invention, the pixel circuit may include a light emitting element, a driving circuit, a data writing circuit, a compensation control circuit, a first light emitting control circuit, a second light emitting control circuit, a first initialization circuit, a second initialization circuit, and a tank circuit; the light emitting element may be an organic light emitting diode O1;
The first initialization circuit comprises a first transistor T1, the compensation control circuit comprises a second transistor, the driving circuit comprises a driving transistor T3, the data writing circuit comprises a fourth transistor T4, the first light emitting control circuit comprises a fifth transistor T5, the second light emitting control circuit comprises a sixth transistor T6, the second initialization circuit comprises a seventh transistor T7, and the energy storage circuit comprises a storage capacitor Cst;
the grid electrode of the T1 is electrically connected with a first initial control end, and a first initial control signal accessed by the first initial control end is an N-1 th-level first driving signal GateN (N-1); the source electrode of the T1 is electrically connected with the first initial voltage end I1, and the drain electrode of the T1 is electrically connected with the first node N1; the first initial voltage terminal I1 is configured to provide a first initial voltage Vinit1; n is a positive integer;
the grid electrode of the T2 is electrically connected with the compensation control end, and an initial control signal accessed by the initial control end is an N-th-stage first driving signal GateN (N); the source electrode of the T2 is electrically connected with the first node N1, and the drain electrode of the T2 is electrically connected with the third node N3;
the grid electrode of the T3 is electrically connected with the first node N1, the source electrode of the T3 is electrically connected with the second node N2, and the drain electrode of the T3 is electrically connected with the third node N3;
the grid electrode of the T4 is electrically connected with the writing control end, the source electrode of the T4 is electrically connected with the Data line Data, and the drain electrode of the T4 is electrically connected with the second node N2; the data writing control signal accessed by the writing control terminal is an N+1th-stage second driving signal GateP (N+1);
The grid electrode of the T5 is electrically connected with a light emitting control end, and the light emitting control end is connected with a light emitting control signal EM; the source electrode of the T5 is electrically connected with the power supply voltage end VDD, and the drain electrode of the T5 is electrically connected with the second node N2;
the grid electrode of the T6 is electrically connected with the light-emitting control end, the source electrode of the T6 is electrically connected with the third node N3, the drain electrode of the T6 is electrically connected with the anode of the organic light-emitting diode O1, and the cathode of the organic light-emitting diode O1 is electrically connected with the low-voltage end VSS;
the grid electrode of the T7 is electrically connected with a second initial control end, and a second initial control signal accessed by the second initial control end is an N-th-stage second driving signal GateP (N); the source electrode of the T7 is electrically connected with the second initial voltage end I2, and the drain electrode of the T7 is electrically connected with the anode of the O1; the second initial voltage terminal I2 is configured to provide a second initial voltage Vinit2;
the first terminal of Cst is electrically connected to the first node N1, and the second terminal of Cst is electrically connected to the power voltage terminal VDD.
In at least one embodiment of the pixel circuit shown in FIG. 7, T1 and T2 are n-type transistors and T3, T4, T5, T6 and T7 are p-type transistors.
In at least one embodiment of the pixel circuit shown in fig. 7, a first GOA module may provide a compensation control signal to the compensation control circuit and a first initial control signal to the first initialization circuit; the second GOA module can be used for providing a data writing control signal for the data writing circuit and providing a second initial control signal for the second initializing circuit; the light emission control signals may be provided to the first light emission control circuit and the second light emission control circuit by the light emission control signal generation module.
As shown in fig. 8, at least one embodiment of the pixel circuit shown in fig. 7 is in operation with a fundamental frequency of 120Hz, a first refresh frame labeled Ts1, and a frequency of the emission control signal EM of 240Hz; in the first refresh frame Ts1, the frequency of the TE signal is 120Hz;
after the first refreshing frame Ts1 is finished, the frequency of the TE signal is changed to 240Hz, and the picture generator judges that the current picture to be displayed is a dynamic picture in the second upward pulse of the TE signal, and the second frame is also a refreshing frame;
in the second refresh frame Ts2, in the first high level sustain period of EM, the potential of gate (N-1) and the potential of gate (N) rise successively to control T1 to turn on first to initialize the potential of the first node N1, then control T2 to turn on to control communication between the first node N1 and the third node N3, T4 is turned on under control of gate (n+1) at least part of the time period in which T2 is turned on to write the Data voltage Vdata supplied from the Data line Data to the second node and to write the first node N1 through turned on T2 to charge Cst, and T7 is turned on to initialize the anode of O1 through Vinit2 before T4 is turned on;
in the second refresh frame Ts2, the frequency of the TE signal is 120Hz;
After the second refreshing frame Ts2 is finished, the frequency of the TE signal is changed to 240Hz, and the picture generator judges that the current picture to be displayed is a static picture without data voltage refreshing when the picture is in the first holding frame Tb1;
after the second refreshing frame Ts2 is finished, the picture generator judges that the current picture to be displayed is a dynamic picture in the fourth upward pulse of the TE signal, and then enters a third refreshing frame Ts3;
in the third refresh frame Ts3, during the first high level sustain period of EM, the potential of gate (N-1) and the potential of gate (N) rise successively to control T1 to turn on first to initialize the potential of the first node N1, then to control T2 to turn on to control communication between the first node N1 and the third node N3, T4 is turned on under the control of gate (n+1) at least part of the time period in which T2 is turned on to write the Data voltage Vdata supplied by the Data line Data to the second node and to write the first node N1 through turned-on T2 to charge Cst, and T7 is turned on to initialize the anode of O1 through Vinit2 before T4 is turned on;
after the third refreshing frame Ts3 is finished, the frequency of the TE signal is changed to 240Hz, and the picture generator judges that the current picture to be displayed is a static picture and does not need to carry out data voltage refreshing when the picture generator is positioned in the second holding frame Tb2; in the seventh pulse of the TE signal, the picture generator judges that the current picture to be displayed is a dynamic picture, and enters a fourth refreshing frame Ts4;
In the fourth refresh frame Ts4, during the first high level sustain period of EM, the potential of gate (N-1) and the potential of gate (N) rise successively to control T1 to turn on first to initialize the potential of the first node N1, then to control T2 to turn on to control communication between the first node N1 and the third node N3, T4 is turned on under the control of gate (n+1) at least part of the time period in which T2 is turned on to write the Data voltage Vdata supplied by the Data line Data to the second node and to write the first node N1 through turned-on T2 to charge Cst, and T7 is turned on to initialize the anode of O1 through Vinit2 before T4 is turned on;
after the fourth refresh frame Ts4 is finished, the frequency of the TE signal becomes 240Hz, and the picture generator judges that the current picture to be displayed is a still picture and does not need to perform data voltage refresh in the eighth pulse of the TE signal, the ninth pulse of the TE signal, the tenth pulse of the TE signal, the eleventh pulse of the TE signal, the twelfth pulse of the TE signal and the thirteenth pulse of the TE signal, and the period of time is the third holding frame Tb3;
in each holding frame, gateN (N-1) and GateN (N) are both low voltage signals.
As shown in fig. 8, the refresh frequency of the pixel circuit is 120Hz, 80Hz, and 60Hz in this order.
In fig. 8, a communication interface control signal is denoted by the numeral MIPI, and when MIPI is a clock signal, it is indicated that a data voltage can be transmitted through the communication interface.
As shown in fig. 8, the frequency of the gate (N) and the frequency of the gate (n+1) are both 240Hz to control the high frequency turn-on of T7, and the high frequency reset of the anode of O1 is performed to improve the flicker phenomenon.
As shown in fig. 9, in at least one embodiment of the present invention, the pixel circuit may include a light emitting element, a driving circuit, a data writing circuit, a compensation control circuit, a first light emitting control circuit, a second light emitting control circuit, a first initialization circuit, a second initialization circuit, and a tank circuit; the light emitting element may be an organic light emitting diode O1;
the first initialization circuit comprises a first transistor T1, the compensation control circuit comprises a second transistor, the driving circuit comprises a driving transistor T3, the data writing circuit comprises a fourth transistor T4, the first light emitting control circuit comprises a fifth transistor T5, the second light emitting control circuit comprises a sixth transistor T6, the second initialization circuit comprises a seventh transistor T7, and the energy storage circuit comprises a storage capacitor Cst;
the grid electrode of the T1 is electrically connected with a first initial control end, and a first initial control signal accessed by the first initial control end is an N-1 th-level first driving signal GateN (N-1); the source electrode of the T1 is electrically connected with the first initial voltage end I1, and the drain electrode of the T1 is electrically connected with the first node N1; the first initial voltage terminal I1 is configured to provide a first initial voltage Vinit1; n is a positive integer;
The grid electrode of the T2 is electrically connected with the compensation control end, and an initial control signal accessed by the initial control end is an N-th-stage first driving signal GateN (N); the source electrode of the T2 is electrically connected with the first node N1, and the drain electrode of the T2 is electrically connected with the third node N3;
the grid electrode of the T3 is electrically connected with the first node N1, the source electrode of the T3 is electrically connected with the second node N2, and the drain electrode of the T3 is electrically connected with the third node N3;
the grid electrode of the T4 is electrically connected with the writing control end, the source electrode of the T4 is electrically connected with the Data line Data, and the drain electrode of the T4 is electrically connected with the second node N2; the data writing control signal accessed by the writing control terminal is an N-th second driving signal GateP (N);
the grid electrode of the T5 is electrically connected with a light emitting control end, and the light emitting control end is connected with a light emitting control signal EM; the source electrode of the T5 is electrically connected with the power supply voltage end VDD, and the drain electrode of the T5 is electrically connected with the second node N2;
the grid electrode of the T6 is electrically connected with the light-emitting control end, the source electrode of the T6 is electrically connected with the third node N3, the drain electrode of the T6 is electrically connected with the anode of the organic light-emitting diode O1, and the cathode of the organic light-emitting diode O1 is electrically connected with the low-voltage end VSS;
the grid electrode of the T7 is electrically connected with a second initial control end, and a second initial control signal accessed by the second initial control end is an N-th-stage first reset signal ResetP (N); the source electrode of the T7 is electrically connected with the second initial voltage end I2, and the drain electrode of the T7 is electrically connected with the anode of the O1; the second initial voltage terminal I2 is configured to provide a second initial voltage Vinit2;
The first terminal of Cst is electrically connected to the first node N1, and the second terminal of Cst is electrically connected to the power voltage terminal VDD.
In at least one embodiment of the pixel circuit shown in fig. 9, T1 and T2 are n-type transistors, and T3, T4, T5, T6, and T7 are p-type transistors.
In at least one embodiment of the pixel circuit shown in fig. 9, a first GOA module may provide a compensation control signal to the compensation control circuit and a first initial control signal to the first initialization circuit; a second GOA module can provide a data writing control signal for the data writing circuit; a second initial control signal can be provided for the second initialization circuit by the third GOA module; the light emission control signals may be provided to the first light emission control circuit and the second light emission control circuit by the light emission control signal generation module.
As shown in fig. 10, the frequency of the nth stage first reset signal ResetP (N) may be 240Hz to control the T7 to be turned on at a high frequency, and to reset the anode of O1 at a high frequency, thereby improving the flicker phenomenon.
As shown in fig. 10, at least one embodiment of the pixel circuit shown in fig. 9 is in operation with a fundamental frequency of 120Hz, a first refresh frame labeled Ts1, and a frequency of the emission control signal EM of 240Hz; in the first refresh frame Ts1, the frequency of the TE signal is 120Hz;
After the first refreshing frame Ts1 is finished, the frequency of the TE signal is changed to 240Hz, and the picture generator judges that the current picture to be displayed is a dynamic picture in the second upward pulse of the TE signal, and the second frame is also a refreshing frame;
in the second refresh frame Ts2, during the first high level sustain period of the EM, the potential of gate (N-1) and the potential of gate (N) are sequentially raised to control T1 to be turned on first to initialize the potential of the first node N1, then T2 to be turned on to control communication between the first node N1 and the third node N3, and T4 is turned on under the control of gate (N) at least a part of the time period in which T2 is turned on to write the Data voltage Vdata supplied from the Data line Data into the second node and to write the Data voltage Vdata into the first node N1 through the turned-on T2 to charge Cst;
in the second refresh frame Ts2, the frequency of the TE signal is 120Hz;
after the second refreshing frame Ts2 is finished, the frequency of the TE signal is changed to 240Hz, and the picture generator judges that the current picture to be displayed is a static picture without data voltage refreshing when the picture is in the first holding frame Tb1;
after the second refreshing frame Ts2 is finished, the picture generator judges that the current picture to be displayed is a dynamic picture in the fourth upward pulse of the TE signal, and then enters a third refreshing frame Ts3;
In the third refresh frame Ts3, during the first high level sustain period of the EM, the potential of gate (N-1) and the potential of gate (N) are sequentially raised to control T1 to be turned on first to initialize the potential of the first node N1, then T2 to be turned on to control communication between the first node N1 and the third node N3, T4 is turned on under the control of gate (N) at least a part of the time period in which T2 is turned on to write the Data voltage Vdata supplied from the Data line Data into the second node, and to write the Data voltage Vdata into the first node N1 through the turned-on T2 to charge Cst;
after the third refreshing frame Ts3 is finished, the frequency of the TE signal is changed to 240Hz, and the picture generator judges that the current picture to be displayed is a static picture and does not need to carry out data voltage refreshing when the picture generator is positioned in the second holding frame Tb2; in the seventh pulse of the TE signal, the picture generator judges that the current picture to be displayed is a dynamic picture, and enters a fourth refreshing frame Ts4;
in the fourth refresh frame Ts4, during the first high level sustain period of the EM, the potential of gate (N-1) and the potential of gate (N) are sequentially raised to control T1 to be turned on first to initialize the potential of the first node N1, then T2 to be turned on to control communication between the first node N1 and the third node N3, T4 is turned on under the control of gate (N) at least a part of the time period in which T2 is turned on to write the Data voltage Vdata supplied from the Data line Data into the second node and to write the first node N1 through the turned-on T2 to charge Cst;
After the fourth refresh frame Ts4 is finished, the frequency of the TE signal becomes 240Hz, and the picture generator judges that the current picture to be displayed is a still picture and does not need to perform data voltage refresh in the eighth pulse of the TE signal, the ninth pulse of the TE signal, the tenth pulse of the TE signal, the eleventh pulse of the TE signal, the twelfth pulse of the TE signal and the thirteenth pulse of the TE signal, and the period of time is the third holding frame Tb3;
in each holding frame, gateN (N-1) and GateN (N) are both low voltage signals.
As shown in fig. 10, the refresh frequency of the pixel circuit is 120Hz, 80Hz, and 60Hz in this order.
As shown in fig. 11, the data providing indication signal TE may be generated by a first control signal TE1 and a second control signal TE 2;
wherein, the second control signal TE2 may be a clock signal with a fixed frequency, and TE2 may have a fixed frequency of 240Hz, 360Hz or 480Hz;
TE1 may provide a high voltage signal in the hold frame and TE1 may have a frequency of fundamental frequency, e.g., 120Hz, in the refresh frame.
As shown in fig. 12, a first input terminal of the and gate AD is connected to TE1, a second input terminal of the and gate AD is connected to TE2, and the and gate AD outputs TE.
The display control method of the embodiment of the invention is applied to the display control circuit, and comprises the following steps: after the end of the refresh frame,
The display control circuit controls the frequency of the data providing indication signal to be a first frequency which is 1/n times of the light emitting control frequency, wherein n is a positive integer;
the picture generator judges the current picture as a dynamic picture or a static picture according to the current data voltage and provides a judging result to the display control circuit;
when the judgment result indicates that the current picture is a static picture when the potential of the data providing indication signal is an effective voltage, the display control circuit controls the potential of the compensation control signal to be maintained at an ineffective voltage before the next effective voltage period of the data providing indication signal; when the data supply indication signal has a valid voltage, and the current picture is a dynamic picture as indicated by the judgment result, the display control circuit controls the compensation control signal to have a valid voltage so as to refresh the potential of the control end of the driving circuit in the pixel circuit in at least part of the next invalid voltage period of the light emission control signal.
The embodiment of the invention can realize the fine and smooth frequency-reducing function, can enable the picture refreshing of the terminal product to be more timely, and the picture of the GPU (graphic processing unit) at the whole machine end can be displayed more timely after being rendered, so that the picture connection is better, and the user experience is better.
In at least one embodiment of the present invention, the pixel circuit is further connected to a data writing control signal, and the display control method further includes: after the end of the refresh frame,
when the judgment result indicates that the current picture is a static picture when the potential of the data providing indication signal is an effective voltage, the display control circuit controls the potential of the data writing control signal to be maintained at an ineffective voltage before the next effective voltage period of the data providing indication signal;
when the judgment result indicates that the current picture is a dynamic picture, the display control circuit controls the potential of the data writing control signal to be an effective voltage so as to perform data voltage writing in at least part of the next ineffective voltage period of the light emitting control signal.
The display panel according to at least one embodiment of the present invention includes the display control circuit described above.
The display panel according to at least one embodiment of the present invention further includes a pixel circuit, a driving integrated circuit, and a picture generator;
the drive integrated circuit is used for providing a data providing indication signal;
The picture generator is used for judging whether the current picture is a dynamic picture or a static picture according to the current data voltage and providing a judging result to the display control circuit;
the pixel circuit comprises a light emitting element, a driving circuit, a compensation control circuit, a first light emitting control circuit and a second light emitting control circuit;
the control end of the driving circuit is electrically connected with a first node, the first end of the driving circuit is electrically connected with a second power-saving node, the second end of the driving circuit is electrically connected with a third node, and the driving circuit is used for controlling the communication between the second node and the third node under the control of the potential of the first node;
the control end of the compensation control circuit is electrically connected with the compensation control end, and the compensation control circuit is respectively electrically connected with the first node and the third node and is used for controlling the communication between the first node and the third node under the control of a compensation control signal provided by the compensation control end;
the first light emitting control circuit is respectively and electrically connected with the light emitting control end, the power supply voltage end and the second node and is used for controlling the communication between the power supply voltage end and the second node under the control of a light emitting control signal provided by the light emitting control end;
The second light-emitting control circuit is respectively and electrically connected with the light-emitting control end, the third node and the first electrode of the light-emitting element and is used for controlling the communication between the third node and the first electrode of the light-emitting element under the control of the light-emitting control signal;
the second pole of the light emitting element is electrically connected with the low voltage terminal.
In at least one embodiment of the present invention, the pixel circuit further includes a data writing circuit, a first initializing circuit, and a second initializing circuit;
the data writing circuit is respectively and electrically connected with the writing control end, the data line and the second node and is used for writing the data voltage provided by the data line into the second node under the control of the data writing control signal provided by the writing control end;
the first initialization circuit is electrically connected with the first initial control end, the first initial voltage end and the first node respectively and is used for writing the first initial voltage provided by the first initial voltage end into the first node under the control of a first initial control signal provided by the first initial control end;
the second initializing circuit is electrically connected with the second initial control end, the second initial voltage end and the first pole of the light-emitting element respectively, and is used for writing the second initial voltage provided by the second initial voltage end into the first pole of the light-emitting element under the control of the second initial control signal provided by the second initial control end.
The display device provided by the embodiment of the invention comprises the display panel.
In at least one embodiment of the present invention, a pixel circuit in the display panel includes a compensation control circuit, a data writing circuit, a first initialization circuit, and a second initialization circuit; the display device comprises a first GOA (Gate On Array) module and a second GOA module;
the first GOA module is used for providing a compensation control signal for the compensation control circuit and providing a first initial control signal for the first initialization circuit;
the second GOA module is used for providing a data writing control signal for the data writing circuit and providing a second initial control signal for the second initializing circuit.
In at least one embodiment of the present invention, a pixel circuit in the display panel includes a compensation control circuit, a data writing circuit, a first initialization circuit, and a second initialization circuit; the display device comprises a first GOA module, a second GOA module and a third GOA module;
the first GOA module is used for providing a compensation control signal for the compensation control circuit and providing a first initial control signal for the first initialization circuit;
The second GOA module is used for providing a data writing control signal for the data writing circuit;
the third GOA module provides a second initial control signal for the second initialization circuit.
The display device provided by the embodiment of the invention can be any product or component with a display function, such as a mobile phone, a tablet personal computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.
While the foregoing is directed to the preferred embodiments of the present invention, it will be appreciated by those skilled in the art that various modifications and adaptations can be made without departing from the principles of the present invention, and such modifications and adaptations are intended to be comprehended within the scope of the present invention.

Claims (15)

1. The display control circuit is contained in a display panel, and the display panel further comprises a pixel circuit, a driving integrated circuit and a picture generator; the drive integrated circuit is used for providing a data providing indication signal; the pixel circuit is connected with a compensation control signal and a light-emitting control signal and is used for carrying out threshold voltage compensation under the control of the compensation control signal and carrying out light-emitting control under the control of the light-emitting control signal; it is characterized in that the method comprises the steps of,
The display control circuit is used for controlling the frequency of the data providing indication signal to be a first frequency after the refresh frame is finished, wherein the first frequency is 1/n times of the light-emitting control frequency, and n is a positive integer; the light-emitting control frequency is the frequency of the light-emitting control signal;
the picture generator is used for judging whether the current picture is a dynamic picture or a static picture according to the current data voltage and providing a judging result to the display control circuit;
the display control circuit is used for controlling the potential of the compensation control signal to be kept at the invalid voltage before the next valid voltage time period of the data providing indication signal when the judging result indicates that the current picture is a static picture when the potential of the data providing indication signal is the valid voltage after the refresh frame is finished, and controlling the potential of the compensation control signal to be the valid voltage when the judging result indicates that the current picture is the dynamic picture and at least part of the stages in the next invalid voltage time period of the light emitting control signal when the potential of the data providing indication signal is the valid voltage after the refresh frame is finished.
2. The display control circuit according to claim 1, wherein the pixel circuit is further connected to a data write control signal, the display control circuit is further configured to control the potential of the data write control signal to be maintained at an inactive voltage before a next active voltage period of the data supply instruction signal when the determination result indicates that the current picture is a still picture when the potential of the data supply instruction signal is an active voltage after the end of the refresh frame, and to control the potential of the data write control signal to be an active voltage at a next at least partial stage in the inactive voltage period of the light emission control signal when the determination result indicates that the current picture is a dynamic picture when the potential of the data supply instruction signal is an active voltage after the end of the refresh frame.
3. The display control circuit of, wherein the pixel circuit is further coupled to a data write control signal;
the display control circuit is used for controlling the frequency of the data writing control signal to be a second frequency, and the second frequency is a fixed frequency.
4. A display control circuit according to claim 3, wherein the second frequency is 1/m times the emission control frequency, m being a positive integer.
5. The display control circuit according to claim 1, wherein the pixel circuit is further connected to a first initial control signal for controlling initializing a potential of a control terminal of a driving circuit in the pixel circuit under control of the first initial control signal;
the display control circuit is used for controlling the potential of the first initial control signal to be maintained to be an invalid voltage before the next valid voltage time period of the data providing indication signal when the judging result indicates that the current picture is a static picture when the potential of the data providing indication signal is the valid voltage after the refresh frame is finished, and controlling the potential of the first initial control signal to be the valid voltage when the judging result indicates that the current picture is a dynamic picture when the potential of the data providing indication signal is the valid voltage after the refresh frame is finished.
6. The display control circuit according to claim 1, wherein the pixel circuit is further connected to a second initial control signal for controlling initializing the potential of the first electrode of the light emitting element in the pixel circuit under the control of the second initial control signal;
the display control circuit is used for controlling the frequency of the second initial control signal to be a third frequency, and the third frequency is a fixed frequency.
7. The display control circuit of claim 6 wherein the third frequency is 1/a times the emission control frequency and m is a positive integer.
8. A display control method applied to the display control circuit according to any one of claims 1 to 7, characterized by comprising: after the end of the refresh frame,
the display control circuit controls the frequency of the data providing indication signal to be a first frequency which is 1/n times of the light emitting control frequency, wherein n is a positive integer;
the picture generator judges the current picture as a dynamic picture or a static picture according to the current data voltage and provides a judging result to the display control circuit;
when the judgment result indicates that the current picture is a static picture when the potential of the data providing indication signal is an effective voltage, the display control circuit controls the potential of the compensation control signal to be maintained at an ineffective voltage before the next effective voltage period of the data providing indication signal; when the judgment result indicates that the current picture is a dynamic picture when the potential of the data providing indication signal is an effective voltage, the display control circuit controls the potential of the compensation control signal to be an effective voltage in at least part of the next invalid voltage period of the light emission control signal.
9. The display control method according to claim 8, wherein the pixel circuit is further connected to a data write control signal, the display control method further comprising: after the end of the refresh frame,
when the judgment result indicates that the current picture is a static picture when the potential of the data providing indication signal is an effective voltage, the display control circuit controls the potential of the data writing control signal to be maintained at an ineffective voltage before the next effective voltage period of the data providing indication signal;
when the judgment result indicates that the current picture is a dynamic picture when the potential of the data supply indication signal is an effective voltage, the display control circuit controls the potential of the data writing control signal to be an effective voltage in at least part of the next invalid voltage period of the light emission control signal.
10. A display panel comprising the display control circuit according to any one of claims 1 to 7.
11. The display panel of claim 10, further comprising a pixel circuit, a driving integrated circuit, and a picture generator;
the drive integrated circuit is used for providing a data providing indication signal;
The picture generator is used for judging whether the current picture is a dynamic picture or a static picture according to the current data voltage and providing a judging result to the display control circuit;
the pixel circuit comprises a light emitting element, a driving circuit, a compensation control circuit, a first light emitting control circuit and a second light emitting control circuit;
the control end of the driving circuit is electrically connected with a first node, the first end of the driving circuit is electrically connected with a second power-saving node, the second end of the driving circuit is electrically connected with a third node, and the driving circuit is used for controlling the communication between the second node and the third node under the control of the potential of the first node;
the control end of the compensation control circuit is electrically connected with the compensation control end, and the compensation control circuit is respectively electrically connected with the first node and the third node and is used for controlling the communication between the first node and the third node under the control of a compensation control signal provided by the compensation control end;
the first light emitting control circuit is respectively and electrically connected with the light emitting control end, the power supply voltage end and the second node and is used for controlling the communication between the power supply voltage end and the second node under the control of a light emitting control signal provided by the light emitting control end;
The second light-emitting control circuit is respectively and electrically connected with the light-emitting control end, the third node and the first electrode of the light-emitting element and is used for controlling the communication between the third node and the first electrode of the light-emitting element under the control of the light-emitting control signal;
the second pole of the light emitting element is electrically connected with the low voltage terminal.
12. The display panel of claim 11, wherein the pixel circuit further comprises a data write circuit, a first initialization circuit, and a second initialization circuit;
the data writing circuit is respectively and electrically connected with the writing control end, the data line and the second node and is used for writing the data voltage provided by the data line into the second node under the control of the data writing control signal provided by the writing control end;
the first initialization circuit is electrically connected with the first initial control end, the first initial voltage end and the first node respectively and is used for writing the first initial voltage provided by the first initial voltage end into the first node under the control of a first initial control signal provided by the first initial control end;
the second initializing circuit is electrically connected with the second initial control end, the second initial voltage end and the first pole of the light-emitting element respectively, and is used for writing the second initial voltage provided by the second initial voltage end into the first pole of the light-emitting element under the control of the second initial control signal provided by the second initial control end.
13. A display device comprising the display panel according to any one of claims 10 to 12.
14. The display device according to claim 13, wherein the pixel circuit in the display panel includes a compensation control circuit, a data writing circuit, a first initialization circuit, and a second initialization circuit; the display device comprises a first GOA module and a second GOA module;
the first GOA module is used for providing a compensation control signal for the compensation control circuit and providing a first initial control signal for the first initialization circuit;
the second GOA module is used for providing a data writing control signal for the data writing circuit and providing a second initial control signal for the second initializing circuit.
15. The display device according to claim 13, wherein the pixel circuit in the display panel includes a compensation control circuit, a data writing circuit, a first initialization circuit, and a second initialization circuit; the display device comprises a first GOA module, a second GOA module and a third GOA module;
the first GOA module is used for providing a compensation control signal for the compensation control circuit and providing a first initial control signal for the first initialization circuit;
The second GOA module is used for providing a data writing control signal for the data writing circuit;
the third GOA module provides a second initial control signal for the second initialization circuit.
CN202310165141.8A 2023-02-24 2023-02-24 Display control circuit, display control method, display panel and display device Pending CN116504181A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310165141.8A CN116504181A (en) 2023-02-24 2023-02-24 Display control circuit, display control method, display panel and display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310165141.8A CN116504181A (en) 2023-02-24 2023-02-24 Display control circuit, display control method, display panel and display device

Publications (1)

Publication Number Publication Date
CN116504181A true CN116504181A (en) 2023-07-28

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN202310165141.8A Pending CN116504181A (en) 2023-02-24 2023-02-24 Display control circuit, display control method, display panel and display device

Country Status (1)

Country Link
CN (1) CN116504181A (en)

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