KR20070042636A - Liquid crystal display and driving method of the same - Google Patents

Abstract

The present invention relates to a liquid crystal display device and a driving method thereof for realizing EMI reduction and low power consumption.

According to an exemplary embodiment of the present invention, a liquid crystal display and a driving method thereof may include a data driver for supplying data to a data line, a data controller for comparing data of a previous frame with data of a current frame, extracting change result data, and supplying the data to the data driver. It provides a liquid crystal display device comprising a.

Description

Liquid crystal display and driving method thereof {LIQUID CRYSTAL DISPLAY AND DRIVING METHOD OF THE SAME}

1 is a block diagram illustrating a driver of a liquid crystal display according to the related art.

2 is a block diagram illustrating a liquid crystal display according to the present invention.

3 is a block diagram illustrating a data controller shown in FIG. 2.

FIG. 4 is a block diagram illustrating a driving unit of the liquid crystal display shown in FIG. 2.

FIG. 5 is a flowchart for describing the data controller illustrated in FIG. 3.

FIG. 6 is a flowchart for explaining a hold memory shown in FIG. 3.

     <Explanation of symbols for the main parts of the drawings>

2, 106; Timing control unit 110; Liquid crystal display panel

112; gate driver IC 114; data driver IC

130; data controller 132; frame memory

134; data comparison / extraction unit 141; shift register

142; data latch 143; sampling memory

144; hold memory 145; level shifter

146; D / A converter 147; output circuit

148; gamma voltage generating circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device and a driving method thereof, and more particularly, to a liquid crystal display device and a driving method thereof that realize EMI reduction and low power consumption.

The liquid crystal display displays an image by adjusting light transmittance of liquid crystal cells according to a driving signal. The liquid crystal display device is implemented in an active matrix type in which switching elements are formed in each cell, and is applied to display devices such as computer monitors, office equipment, and cellular phones. As a switching element used in an active matrix liquid crystal display device, a thin film transistor (TFT) is mainly used.

Referring to FIG. 1, a driving circuit unit of a liquid crystal display according to the related art includes a data driving IC (IC) 6 for driving a data line, and a timing controller 2 for controlling the data drive IC 6. It includes.

The data driver IC 6 is connected to data lines (not shown) via a tape carrier package (TCP) and a pad of a liquid crystal display panel. The data driving IC 6 receives the data control signal, the display data, and the power signals from the power supply unit (not shown) from the timing controller 2. The data driver IC 6 converts display data, which is a digital signal, into an analog signal and supplies the data lines on the liquid crystal display panel one by one to implement an image on the liquid crystal display panel.

The timing control unit 2 generates a horizontal synchronizing signal for notifying the start of data and a synchronizing signal for transmitting data, or a signal for starting output from the data driving IC 6 after completion of data transfer, thereby generating the data drive IC 6. To send to.

The timing controller 2 generates data control signals and display data by using driving signals such as data signals and clock signals input through the interface.

Such a liquid crystal display must show a large number of frames in a short time when a video is implemented, and data must be supplied to a plurality of data lines to implement each frame. For this purpose, it is necessary to increase the data capacity of the timing controller and the data driver IC and increase the speed thereof. However, the increase in size and speed of data capacity has caused an increase in current consumption and EMI (Electro Magnetic Interference). In addition, there is a problem that the screen abnormality occurs due to the increase in interference between components due to the flow of high current.

Disclosure of Invention An object of the present invention is to provide a liquid crystal display device and a driving method thereof for realizing EMI reduction and low power consumption.

In order to achieve the above object, the liquid crystal display according to the present invention compares the data driver for supplying data to a data line, the data of the previous frame and the data of the current frame, extracts the comparison result change data, and supplies the data to the data driver. It characterized in that it comprises a data control unit.

Specifically, the data control unit generates a data correction / maintenance signal by comparing the data of the previous frame with the data of the current frame, and extracts change data, and responds to the data maintenance signal. And a frame memory configured to store data of a previous frame and store data of a current frame in response to the data correction signal.

The data driving IC includes a shift register, a data latch for storing data one line at a time in response to a clock signal from the shift register, a sampling memory for time-dividing the digital data from the data latch, and the sampling. A hold memory for receiving data from the memory and the data correction / maintenance signal, a level shifter for converting a level of the data received from the hold memory, and an analog gamma voltage for selection according to the level shifted data in the level shifter. And a gamma voltage generation circuit for outputting various analog gamma voltages for gray scale display to the DA converter, and an output circuit for supplying the analog gamma voltage selected from the DA converter to the data line. .

The frame memory may store input data in at least one frame unit.

The hold memory may include a memory capable of storing data of at least one frame to output or maintain data according to the data retention / correction signal.

On the other hand, it characterized in that it further comprises a timing controller for controlling the data driver.

The data controller may be built in the timing controller.

In order to achieve the above object, the driving method of the liquid crystal display according to the present invention includes comparing the data of the previous frame stored with the data of the received current frame in a data controller, and comparing the current frame according to the comparison result. And extracting change data different from data of a previous frame among data, and supplying the extracted change data to a data driver.

In detail, the comparing / extracting of the data may include outputting a data holding signal from the data controller without outputting data to the data driver when the data of the previous frame and the data of the current frame are the same; And when the data of the previous frame and the data of the current frame are different, outputting the change data and the data correction signal to the data driver.

The method may further include storing data of the current frame in a frame memory of the data controller when data of the previous frame and data of the current frame are different.

The step of supplying the data from the data driver IC to the data line includes storing the data in a data latch in response to a signal from a shift register, and storing digital data from the data latch in a sampling memory in time division. Storing data or change data from the sampling memory in a hold memory in response to the data holding / correction signal, converting a level of data supplied from the hold memory in a level shifter, And selecting an analog gamma voltage according to the level converted data and supplying the analog gamma voltage to the data line.

The method may further include outputting data stored in the hold memory according to the data holding signal, and storing and outputting changed data in the hold memory according to the data correction signal.

Other objects and advantages of the present invention in addition to the above objects will become apparent from the detailed description of the following embodiments with reference to the accompanying drawings.

Hereinafter, a preferred embodiment of the present invention will be described with reference to the accompanying drawings.

FIG. 2 is a block diagram illustrating a liquid crystal display according to the present invention, and FIG. 3 is a block diagram illustrating the data controller shown in FIG. 2.

2, a liquid crystal display according to the present invention includes a liquid crystal display panel 110, a timing controller 106 for controlling the data driver IC 114 and the gate driver IC 112, and a liquid crystal display panel ( And a gate driver IC 112 for supplying a scan signal to the gate line GL of the 110 and a data driver IC 114 for supplying data to the data line DL. The apparatus further includes a data controller 130 that controls data output of the timing controller 106.

The liquid crystal display panel 110 includes a plurality of liquid crystal cells Clc arranged in a matrix at the intersection of the data line DL and the gate lines GL. Each TFT formed in the liquid crystal cell Clc supplies a data signal supplied from the data line DL to the liquid crystal cell Clc in response to a scan signal supplied from the gate line GL. In addition, a storage capacitor Cst is formed in each of the liquid crystal cells Clc. The storage capacitor Cst is formed between the pixel electrode of the liquid crystal cell Clc and the front gate line, or is formed between the pixel electrode of the liquid crystal cell Clc and the common electrode line to maintain a voltage charged in the liquid crystal cell Clc. Keep it.

The timing controller 106 generates a gate control signal for controlling the gate driving IC 112 and a data control signal for controlling the data driving IC 114 using the vertical / horizontal synchronization signal and the clock signal. Here, the gate control signal for controlling the gate driving IC 112 includes a gate start signal, a gate clock signal, a gate output signal, and the like. The data control signal for controlling the data driver IC 114 includes a data start signal, a data clock signal, a horizontal synchronization signal, a polarity signal, and the like. The timing controller 106 rearranges the digital display data RGB and supplies the display data to the data controller 130.

As illustrated in FIG. 3, the data controller 130 stores digital display data corresponding to one frame from an external system, compares / extracts display data of the stored previous frame and display data of the current frame, and changes the changed data. And generate a data correction / maintenance signal. The data controller 130 outputs the generated change data and the data correction / maintenance signal to the data driver IC 114.

To this end, the data controller 130 includes a frame memory 132 for storing display data corresponding to one frame, and a data comparison / extraction unit 134 for comparing and extracting the stored data and the input data, respectively.

The frame memory 132 stores display data of one frame. The frame memory 132 stores the display data of the previous frame as it is in response to the data retention signal generated by the comparison / extraction unit 134. The frame memory 132 is updated with display data of the current frame in response to the data correction signal generated by the comparison / extraction unit 134.

The data comparison / extraction unit 134 compares the display data of the stored previous frame with the display data of the received current frame, extracts the changed data as a result of the comparison, and generates change data. That is, the display data of the previous frame and the display data of the current frame are compared line by line, and new data is not generated when the data is the same. At this time, a data holding signal for continuously holding display data of the previous frame is generated and output to the frame memory 132 and the data driving IC 114. On the other hand, the change data different from the data of the previous frame is extracted from the display data of the previous frame and the display data of the current frame and output to the data driver IC 114. At the same time, the data comparison / extraction unit 134 simultaneously outputs a data correction signal for controlling the change data to be output from the data driver IC 114 to the data line to the data driver IC 114.

The data controller 130 may be formed in the timing controller 106, may be formed separately, or may be formed inside the CPU.

 Here, the previous frame is a frame corresponding to the previous screen of the screen currently displayed on the liquid crystal display, and the current frame is a frame corresponding to the screen currently displayed on the liquid crystal display.

The gate driving IC 112 sequentially supplies scan pulses to the gate line GL in response to a gate control signal from the timing controller 106 to turn on the TFTs connected to the gate line, thereby to supply the liquid crystal display. Select the horizontal line of the panel 110.

The data driver IC 114 converts the digital display data R, G, and B into analog gamma voltages corresponding to grayscale values in response to data control signals and data correction signals from the timing controller 106 and the data controller 130. The analog gamma voltage is supplied to the data line DL.

To this end, as shown in FIG. 4, the data driver IC 114 stores data one line by one line in response to a clock signal from the shift register 141 and the shift register 141 and stores one line of data. And a data latch 142 for outputting at the same time. The sampling memory 143 stores time-divided digital data R, G, and B from the data latch 142, the hold memory 144 that receives an output signal from the sampling memory 143, and a signal. It further includes a level shifter 145 for converting levels, and a DA converter 146 for selecting analog gamma voltages according to the level shifted signal at the level shifter 145. In addition, selecting the data line DL to which the analog gamma voltage selected from the gamma voltage generation circuit 148 and the DA converter 146 which generate various analog gamma voltages for gray scale display and output them to the DA converter 146 is provided. Further includes an output circuit 147.

The horizontal synchronizing signal, the data clock signal, the data start signal, the polarity signal, the display data D1 ... Dn, the data correction signal, and the gamma voltage V1 ... Vm are input to the data driving IC 114. The data latch 142 latches the digital display data R, G, and B transmitted from the data controller 130 inside. On the other hand, the data start signal for controlling the transfer of the digital display data R, G, and B is transferred into the shift register 141 in synchronization with the data clock signal, and is transferred from the last stage of the shift register 141 to the next stage. The data drive IC 114 is output as a data start signal.

In the sampling memory 143, the digital display data (R, G, B) latched by the data latch 142 is stored once in time division in synchronization with the output signal from each stage of the shift resist 141. FIG. . The stored digital display data is output to the next hold memory 144. When the digital display data R, G, and B are stored in the sampling memory 143, the hold memory 144 receives the output signal from the sampling memory 143 based on the data correction signal, and then the next level shifter ( 145), and the display data is held until the next horizontal synchronizing signal is input. The hold memory 144 may further include a memory capable of storing data of one frame so as to output or maintain data according to the data correction / maintenance signal of the data controller 130. That is, the hold memory 144 outputs display data of the previous frame stored in the hold memory 144 to the level shifter 145 in response to the data holding signal. The hold memory 144 stores the display data of one frame made of the change data and the remaining data (same data as the display data of the previous frame) except for the change data in response to the data correction signal. Data is output to the level shifter 145.

As such, instead of supplying all the data every frame to the data driver, only the change data is input, thereby reducing the current consumption and reducing the EMI since the current does not flow excessively.

A driving method of the liquid crystal display of the present invention will be described with reference to FIGS. 5 and 6.

First, as shown in FIG. 5, in the state in which display data of the N−1th frame is stored in the data controller, display data of the Nth frame is input (S171). Next, N− in the data comparison / extraction unit is performed. The display data of the first frame is compared with the display data of the Nth frame (S172). If the display data of the N-th frame and the display data of the N-th frame stored in the frame result are the same, the data comparison / extraction unit generates a data retention signal (S173). Alternatively, when the display data of the N-th frame and the display data of the N-th frame stored in the frame memory are not the same, a change data and a data correction signal are generated (S174). The data correction signal and the change data are output to the driving IC (S175).

Subsequently, as shown in FIG. 6, when the data holding signal is input to the hold memory in the driving IC (C171), the display data of the N-th frame is maintained without storing the display data of the N-th frame. (C173). On the other hand, when the data correction signal is input to the hold memory in the driving IC (C172), the change data is stored in the hold memory (C174). Then, the data or the change data of the N-1th frame are output to the level shifter (C175).

Thereafter, the level shifter is a circuit for converting the signal level by boosting or the like in order to be suitable for the DA converter of the next stage which processes the voltage level applied to the liquid crystal display panel. On the other hand, the gamma voltage input from the power supply unit generates various analog gamma voltages for gray scale display by the gamma voltage generating circuit and outputs them to the DA converter. One analog pregamma voltage is selected according to the digital display data level-converted by the level shifter from various analog gamma voltages supplied from the gamma voltage generator circuit. The analog gamma voltage representing this gray scale display is output to the data line DL through an output circuit.

In this way, desired data can be implemented without operating multiple data lines, thereby reducing power consumption and EMI. In particular, power consumption and EMI can be significantly reduced in still pictures and still images.

Meanwhile, the FPC according to the present invention is not only a liquid crystal display device but also a plasma display panel (PDP), organic light emitting diodes (OLEDs), a field effect electron emission display (FED), and the like. It is applicable to a flat panel display device including a.

As described above, the liquid crystal display device and the driving method thereof according to the present invention further include a data controller for controlling data output to the data driver IC, so as to output new data only when the data is changed.

Accordingly, the liquid crystal display and the driving method thereof according to the present invention can implement an image by inputting only the change data instead of supplying all data every frame to the data driver, thereby greatly reducing power consumption and EMI.

In addition, since the interference between components is reduced due to the decrease of the current flow, the problem of screen abnormality is reduced and the reliability of the product is improved.

In the detailed description of the present invention described above with reference to the preferred embodiment of the present invention, those skilled in the art or those skilled in the art having ordinary knowledge of the present invention described in the claims to be described later It will be understood that various modifications and variations can be made in the present invention without departing from the spirit and scope of the art.

Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (12)

A data driver supplying data to the data line; And a data controller which compares data of a previous frame with data of a current frame, extracts the comparison result change data, and supplies the changed data to the data driver. The method of claim 1, The data control unit A data comparison / extraction unit configured to compare data of the previous frame with data of the current frame to generate a data correction / maintenance signal and to extract change data; And a frame memory configured to store data of a previous frame in response to the data holding signal and to store data of a current frame in response to the data correction signal. The method of claim 2, The data driver IC includes a shift register; A data latch for storing data one line at a time in response to a clock signal from the shift register; A sampling memory for time-dividing the digital data from the data latches; A hold memory for receiving data from the sampling memory and the data correction / maintenance signal; A level shifter for converting a level of data received from the hold memory; A DA converter for selecting an analog gamma voltage according to the data level-converted by the level shifter; A gamma voltage generator circuit for outputting various analog gamma voltages for gray scale display to the DA converter; And an output circuit for supplying the analog gamma voltage selected from the DA converter to the data line. The method of claim 2, And the frame memory stores input data in at least one frame unit. The method of claim 3, wherein And the hold memory includes a memory capable of storing data of at least one frame to output or maintain data according to the data hold / correction signal. The method of claim 1, And a timing controller for controlling the data driver. The method of claim 6, And the data controller is built in the timing controller. Comparing the data of the stored previous frame with the data of the received current frame in a data controller; Extracting change data different from data of a previous frame among data of the current frame according to the comparison result; And supplying the extracted change data to a data driver. The method of claim 8, The comparing / extracting of the data may include outputting a data holding signal without outputting data to a data driver in the data driver when the data of the previous frame and the data of the current frame are the same; And outputting the change data and the data correction signal to the data driver when the data of the previous frame and the data of the current frame are different. The method of claim 9, And storing the data of the current frame in the frame memory of the data controller when the data of the previous frame and the data of the current frame are different. The method of claim 8, Supplying the data from the data driver IC to a data line comprises storing the data in a data latch in response to a signal from a shift register; Storing digital data from the data latch in a time division in a sampling memory; Storing data from the sampling memory or change data in a hold memory in response to the data hold / correct signal; Converting at a level shifter the level of data supplied from the hold memory; And selecting an analog gamma voltage according to the level-converted data and supplying the analog gamma voltage to a data line. The method of claim 11, Outputting data stored in the hold memory according to the data holding signal; And storing and outputting changed data in the hold memory according to the data correction signal.

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