CN113096606A - GOA circuit, display panel and electronic device - Google Patents

GOA circuit, display panel and electronic device Download PDF

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Publication number
CN113096606A
CN113096606A CN201911340139.XA CN201911340139A CN113096606A CN 113096606 A CN113096606 A CN 113096606A CN 201911340139 A CN201911340139 A CN 201911340139A CN 113096606 A CN113096606 A CN 113096606A
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pull
thin film
film transistor
signal
tft
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CN201911340139.XA
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CN113096606B (en
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尹翔
金志河
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Shenzhen Royole Technologies Co Ltd
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Shenzhen Royole Technologies Co Ltd
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Priority to CN201911340139.XA priority Critical patent/CN113096606B/en
Priority to US17/129,165 priority patent/US11315515B2/en
Priority to EP20216363.0A priority patent/EP3843075A1/en
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

The invention provides a GOA circuit (10), wherein the GOA circuit (10) comprises a plurality of cascaded GOA units (100), each GOA unit (100) comprises a first pull-down control module (110), a second pull-down control module (120) and a pull-down maintaining module (130); at least one of the first pull-down control module (110) and the second pull-down control module (120) includes at least one thin film transistor of a type different from that of the thin film transistor in the pull-down sustain module (130). The invention also provides a display panel (20) and an electronic device (30). At least one of the first pull-down control module (110) and the second pull-down control module (120) of the GOA circuit comprises at least one thin film transistor with a type different from that of the thin film transistor in the pull-down maintaining module (130), so that the GOA circuit can output waveforms more accurately.

Description

GOA circuit, display panel and electronic device
Technical Field
The invention relates to the technical field of display driving, in particular to a GOA circuit, a display panel and an electronic device.
Background
At present, the driving of horizontal scanning lines of an AMOLED display panel is realized by an external integrated circuit, the external integrated circuit can control the gradual opening of all levels of line scanning lines, and a GOA (Gate Driver on array) method is adopted, so that the line scanning driving circuit can be integrated on a display panel substrate, the number of external ICs can be reduced, the production cost of the display panel is reduced, and the narrow frame of a display device can be realized. Currently, the types of thin film transistors used in the GOA circuit are all the same, for example, N-type thin film transistors or P-type thin film transistors are all used, and N-type thin film transistors are all N-type Low Temperature Polysilicon (LTPS) thin film transistors or N-type metal oxide thin film transistors. When the thin film transistors in the GOA circuit are all N-type LTPS thin film transistors, the leakage current is large, which results in that the refresh rate cannot be reduced and the overall power consumption of the display panel is large when the pixel units perform image display, and when the thin film transistors in the GOA circuit are all N-type metal oxide thin film transistors, drift is easily generated, which results in that the display brightness for the same image data in different pixel units is not completely the same, thereby failing to uniformly display the image data. In addition, in the current GOA circuit, one pull-down control module is usually used to control signals of a voltage node, and generally, signals of the voltage node include a high level signal and a low level signal.
Disclosure of Invention
Accordingly, the present invention provides a GOA circuit with better display effect. The specific technical scheme is as follows.
A GOA circuit comprises a plurality of cascaded GOA units, wherein each GOA unit comprises a first pull-down control module, a second pull-down control module and a pull-down maintaining module, each GOA unit further comprises a first voltage end, a clock signal end and a control signal end, the first voltage end, the clock signal end and the control signal end are used for providing signals, and one scanning cycle of each GOA unit comprises a pull-up stage and a pull-down stage;
the first pull-down control module is connected with the clock signal end and used for outputting a signal of the clock signal end to a pull-down node in a pull-down stage;
the second pull-down control module is connected with the first voltage end and used for outputting a signal of the first voltage end to a pull-down node in a pull-up stage;
the pull-down maintaining module is connected with the first pull-down control module and the second pull-down control module and is used for controlling a signal of the first voltage end to be output to an output end in a pull-down stage according to a received signal of the pull-down node and controlling the signal of the first voltage end to stop being output to the output end in a pull-up stage according to the received signal of the pull-down node;
at least one of the first pull-down control module and the second pull-down control module includes at least one thin film transistor of a type different from that of the thin film transistor in the pull-down sustain module.
The invention also provides a display panel which comprises the GOA circuit.
The invention also provides an electronic device comprising a GOA circuit as described above or comprising a display panel as described above.
The invention has the beneficial effects that: on one hand, the first pull-down control module and the second pull-down control module can respectively control the signals of the pull-down nodes to be different potential signals in the pull-down stage and the pull-up stage, so that the signals of the pull-down nodes can be accurately controlled, and the control accuracy of the GOA circuit can be improved; on the other hand, at least one of the first pull-down control module and the second pull-down control module of the invention comprises at least one thin film transistor of a type different from that of the thin film transistor in the pull-down maintaining module, so that the GOA circuit can output the waveform more accurately.
Drawings
Fig. 1 is a schematic block diagram of a GOA circuit according to the present invention.
Fig. 2 is a schematic structural diagram of a GOA circuit provided in the present invention.
Fig. 3 is a waveform diagram of signals provided by the present invention.
Fig. 4 is a schematic diagram of a GOA circuit in a pull-down holding stage according to the present invention.
Fig. 5 is a schematic diagram of a GOA circuit in a pull-up stage according to the present invention.
Fig. 6 is a schematic diagram of a GOA circuit in a pull-up hold stage according to the present invention.
Fig. 7 is a schematic diagram of a GOA circuit in a pull-down stage according to the present invention.
Fig. 8 is a display panel provided by the present invention.
Fig. 9 is an electronic device provided by the present invention.
Detailed Description
While the following is a description of the preferred embodiments of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention.
Referring to fig. 1 and fig. 2, an embodiment of the present invention provides a GOA circuit 10, where the GOA circuit 10 includes a plurality of cascaded GOA units 100, each of the GOA units 100 includes a first pull-down control module 110, a second pull-down control module 120, and a pull-down sustain module 130, the GOA unit 100 further includes a first voltage terminal VGL for providing signals, a clock signal terminal CLKn, and a control signal terminal Gn-1, and one scan cycle of the GOA unit 100 includes a pull-up stage H2 and a pull-down stage H4 (as shown in fig. 3).
The first pull-down control module 110 is connected to the clock signal terminal CLKn, and is configured to output a signal of the clock signal terminal CLKn to the pull-down node PD during the pull-down stage H4.
The second pull-down control module 120 is connected to the first voltage terminal VGL, and is configured to output a signal of the first voltage terminal VGL to the pull-down node PD during the pull-up period H2.
The pull-down maintaining module 130 is connected to the first pull-down control module 110 and the second pull-down control module 120, and is configured to control the signal of the first voltage terminal VGL to be output to the output terminal Gn during the pull-down phase PD according to the received signal of the pull-down node PD, and control the signal of the first voltage terminal VGL to stop being output to the output terminal Gn during the pull-up phase H2 according to the received signal of the pull-down node PD.
At least one of the first and second pull- down control modules 110 and 120 includes at least one thin film transistor of a type different from that of the pull-down sustain module 130.
The first pull-down control module 110 and the second pull-down control module 120 can respectively control the signal of the pull-down node PD, and respectively control the signal of the first voltage terminal VGL to be output to the output terminal Gn in the pull-down stage H4 according to the signal of the pull-down node PD, and control the signal of the first voltage terminal VGL to stop being output to the output terminal Gn in the pull-up stage H2. The first pull-down control module 110 and the second pull-down control module 120 can respectively control the signal of the pull-down node PD to be different potential signals in the pull-down stage H4 and the pull-up stage H2, so that the signal of the pull-down node PD in different stages can be accurately controlled, and the control accuracy of the GOA circuit can be further improved.
In the present invention, at least one of the first pull-down control module 110 and the second pull-down control module 120 includes at least one thin film transistor of a type different from that of the thin film transistor in the pull-down sustain module 130. The current GOA circuit usually adopts an N-type or P-type LTPS thin film transistor, but the leakage current of the N-type LTPS thin film transistor is large, and the output waveform of the output end in the GOA circuit is more and more distorted along with the increase of the leakage current, even turned on or off in advance, so that abnormal display is caused. Therefore, in this embodiment, it is preferable that at least one of the first pull-down control module 110 and the second pull-down control module 120 includes at least one thin film transistor of an N-type metal oxide thin film transistor, and the thin film transistor of the pull-down sustain module 130 is an N-type LTPS thin film transistor.
The N-type metal oxide thin film transistor has lower leakage current than an N-type LTPS thin film transistor, wherein the leakage current is that Vgs is defined by voltage difference between a grid electrode and a source electrode, Vth is used as a reference point, voltage in the opposite direction is switched to bias voltage in a range of Vgs 5-10V, and the drain current is set under the condition corresponding to Vds (voltage difference between a drain electrode and a source electrode). Since the nmos tft has a low leakage current, the first pull-down control module 110 and the second pull-down control module 120 connected to the pull-down node PD do not affect the voltage of the pull-down node PD, so that the voltage signal of the pull-down node PD is more stable, and the output waveform of the output terminal Gn of the GOA circuit is not affected.
In other embodiments, when at least one of the first pull-down control module 110 and the second pull-down control module 120 includes at least one tft of an N-type metal oxide tft type, the tft of the pull-down maintaining module 130 may also be a P-type tft type. The P-type thin film transistor can accurately receive a voltage signal of a fixed value of the first voltage end VGL, and the driving current is large, so that the output waveform is more accurate. In summary, the GOA circuit can output waveforms more accurately by adopting an arrangement in which at least one of the first pull-down control module 110 and the second pull-down control module 120 includes at least one thin film transistor of a type different from that of the thin film transistor in the pull-down sustain module 130.
In addition, when the N-type metal oxide thin film transistor with low leakage current is used for low-frequency driving, the stability of the node voltage connected with the thin film transistor cannot be influenced due to the very small leakage current. When low-frequency driving is adopted or driving frequency is lower, the stay time of the node voltage connected with the thin film transistor is longer, when leakage current of the thin film transistor is larger, a part of current can be leaked from the thin film transistor by the node voltage, the longer the stay time of the node voltage is, the more the leaked current is, the instable the node voltage is caused, other voltage output controlled by the node voltage is further unstable, and the display quality of the display panel is further reduced. Therefore, the N-type metal oxide thin film transistor with low leakage current can improve the leakage current influence during low-frequency driving, and further can be applied to a display panel with low-frequency driving, and can also be applied to a display panel with low-frequency driving and high-frequency driving, or a display panel with a large frequency conversion interval and low-frequency driving, such as a display panel with a frequency conversion interval of 1Hz-120Hz, also called a display panel with a refresh rate of 1Hz-120 Hz.
Therefore, in the present application, the refresh rate of the GOA circuit is preferably 1Hz to 120 Hz. The refresh rate refers to a minimum repetition period of the control signal. In the present invention, it may be a minimum repetition period of the control signal at the control signal terminal or a minimum repetition period of the clock signal at the clock signal terminal. Preferably, the refresh rate of the GOA circuit is 1Hz to 30Hz, or the refresh rate of the GOA circuit is 30Hz to 60Hz, or the refresh rate of the GOA circuit is 30Hz to 90Hz, or the refresh rate of the GOA circuit is 90Hz to 120Hz, or the refresh rate of the GOA circuit is 1Hz to 60Hz, or the refresh rate of the GOA circuit is 60Hz to 120 Hz.
In this embodiment, when the output terminal Gn of the GOA circuit continuously outputs signals, the refresh rate of the GOA circuit dynamically changes if the frequency of the control signal terminal Gn-1 is changed. Namely, the GOA circuit can be dynamically adjusted in the frequency range of 1Hz-120Hz, and the output waveform of the GOA circuit is not influenced by the dynamic change of the refresh rate.
In a further embodiment, the N-type metal oxide transistor includes at least one or more metal oxide combinations of indium gallium zinc oxide, indium gallium tin oxide, and indium tin oxide in the channel layer.
In a further embodiment, at least one of the first pull-down control module and the second pull-down control module comprises at least one thin film transistor having a leakage current of less than 10-12A. It is preferable to use a thin film transistor capable of making the leakage current of the thin film transistor less than 10-12The metal oxide material of A is used as a channel layer material of the N-type metal oxide thin film transistor, and the influence of leakage current on a GOA circuit is further improved. For example, the channel layer of the N-type metal oxide transistor at least comprises one or more metal oxide combinations of indium gallium zinc oxide, indium gallium tin oxide and indium tin oxide.
Referring to fig. 2 again, in a further embodiment, the first pull-down control module 110 includes a fourth tft M4, a third tft M3 and a first capacitor C1, a gate of the fourth tft M4 is connected to the control signal terminal Gn-1, a first pole of the fourth tft M4 is connected to the first voltage terminal VGL, and a second pole of the fourth tft M4 is connected to the first terminal of the first capacitor C1 and the gate of the third tft M3; a second terminal of the first capacitor C1 is connected to the second pole of the third tft M3 and the clock signal terminal CLKn; the first pole of the third thin film transistor M3 is connected to the pull-down node PD.
Referring to fig. 3 and 7, in the pull-down stage H4, the control signal terminal Gn-1 inputs a first control signal, the clock signal terminal CLKn inputs a second clock signal, the first control signal controls the fourth tft M4 to be turned off, the first capacitor C1 transmits the second clock signal of the clock signal terminal CLKn to the gate of the third tft M3 to control the third tft M3 to be turned on, and transmits the second clock signal of the clock signal terminal CLKn to the pull-down node PD through the third tft M3.
In a further embodiment, at least one of the fourth thin film transistor M4 and the third thin film transistor M3 is an N-type metal oxide thin film transistor. The leakage current of the N-type metal oxide thin film transistor is low, the third thin film transistor M3 is connected with the pull-down node PD, and the leakage current of the third thin film transistor M3 is low, so that the influence on the pull-down node PD is small. The fourth tft M4 is electrically connected to the gate of the third tft M3, and if the leakage current of the fourth tft M4 is large, it will affect the stability of turning on or off the third tft M3, resulting in unstable voltage input from the third tft M3 to the pull-down node PD, so in this example, the third tft M3 is preferably an N-type metal oxide tft, and more preferably, the third tft M3 and the fourth tft M4 are both N-type metal oxide tfts.
In a further embodiment, the second pull-down control module 120 includes a fifth tft M5, a gate of the fifth tft M5 is connected to the control signal terminal CLKn, a first pole of the fifth tft M5 is connected to the first voltage terminal VGL, and a second pole of the fifth tft M5 is connected to the pull-down node PD. Specifically, the gate of the fifth tft M5 is connected to the control signal terminal CLKn through the pull-up control module 140.
Referring to fig. 5, in the pull-up stage H2, the control signal terminal CLKn inputs the second control signal, and the fifth tft M5 is turned on according to the second control signal of the control signal terminal CLKn and transmits the signal of the first voltage terminal VGL to the pull-down node PD.
In a further embodiment, the fifth thin film transistor M5 is an N-type metal oxide thin film transistor. The drain current of the N-type metal oxide thin film transistor is low, and the second pole and the pull-down of the fifth thin film transistor M5The node PD is connected, and the lower the drain current of the fifth thin film transistor M5, the smaller the influence on the pull-down node PD. Preferably, a leakage current of less than 10 is used-12The N-type metal oxide thin film transistor A further improves the influence of leakage current on a GOA circuit. More preferably, the channel layer of the N-type metal oxide thin film transistor comprises one or more metal oxide combinations including at least indium gallium zinc oxide, indium gallium tin oxide and indium tin oxide.
Referring to fig. 2 again, in a further embodiment, the pull-down maintaining module 130 includes an eighth tft M8, a ninth tft M9 and a second capacitor C2, the pull-down node PD is connected to the gate of the eighth tft M8, the gate of the ninth tft M9 and the second end of the second capacitor C2, a first electrode of the eighth tft M8 is connected to the first voltage terminal VGL, and a second electrode of the eighth tft M8 is connected to the first electrode of the ninth tft M9; the second pole of the ninth thin film transistor M9 is connected to the output terminal Gn; a first terminal of the second capacitor C2 is connected to the first voltage terminal VGL.
Referring to fig. 7, in the pull-down phase H4, the signal of the pull-down node PD controls the eighth tft M8 and the ninth tft M9 to be turned on, and the signal of the first voltage terminal VGL is transmitted to the output terminal Gn through the eighth tft M8 and the ninth tft M9.
Referring to fig. 5, in the pull-up stage H2, the signal of the pull-down node PD controls the eighth tft M8 and the ninth tft M9 to turn off, and the signal of the first voltage terminal VGL stops being transmitted to the output terminal Gn.
In a further embodiment, the eighth thin film transistor M8 and the ninth thin film transistor M9 are P-type thin film transistors or N-type thin film transistors. Preferably, the N-type thin film transistor is an N-type metal oxide transistor, and the P-type thin film transistor is a P-type low-temperature polycrystalline oxide transistor.
When the eighth and ninth thin film transistors M8 and M9 are N-type thin film transistors, the eighth and ninth thin film transistors M8 and M9 are in a turned-on state when the signal of the pull-down node PD is a high level signal to transmit the signal of the first voltage terminal VGH to the output terminal Gn.
When the eighth and ninth thin film transistors M8 and M9 are P-type thin film transistors, the eighth and ninth thin film transistors M8 and M9 are in a turned-on state when the signal of the pull-down node PD is a low level signal, so as to transmit the signal of the first voltage terminal VGH to the output terminal Gn.
In this application, the pull-down maintaining module 130 transmits the signal of the first voltage terminal VGL to the output terminal Gn under the control of the pull-down node PD, so that the eighth tft M8 and the ninth tft M9 preferably adopt tfts with stronger charging capability or smaller resistance, and preferably adopt N-type LIPS tfts with stronger charging capability, so as to quickly transmit the signal of the first voltage terminal VGL to the output terminal Gn.
Referring to fig. 2 again, in a further embodiment, the GOA unit 10 further includes a pull-up control module 140 and a pull-up sustain module 150, and the GOA unit 10 further includes a second voltage terminal VGH. The pull-up control module 140 is connected to the control signal terminal Gn-1 for outputting the signal of the control signal terminal Gn-1 to the pull-up node PU during the pull-up phase H2 and the pull-down phase H4. The pull-up maintaining module 150 is connected to the pull-up control module 140, and is configured to output the signal of the second voltage terminal VGH to the output terminal Gn during the pull-up phase H2 according to the received signal of the pull-up node PU, and stop outputting the signal of the second voltage terminal VGH to the output terminal Gn during the pull-down phase H4 according to the received signal of the pull-up node PU.
In a further embodiment, the pull-up control module 140 includes a first thin film transistor M1 and a second thin film transistor M2, a gate of the first thin film transistor M1 is connected to the clock signal terminal CLKn, a first pole of the first thin film transistor M1 is connected to the control signal terminal Gn-1, and a second pole of the first thin film transistor M1 is connected to a first pole of the second thin film transistor M2; the gate of the second thin film transistor M2 is connected to the second voltage terminal VGH, and the second pole of the second thin film transistor M2 is connected to the pull-up node PU. In the present embodiment, the first electrode of the second thin film transistor M2 is also connected to the gate of the fifth thin film transistor M5 in the second pull-down control module 120. The fifth thin film transistor M5 is connected to the control signal terminal Gn-1 through the second thin film transistor M2.
Referring to fig. 5, in the pull-up stage H2, the control signal terminal Gn-1 inputs a second control signal, the clock signal terminal CLKn inputs a second clock signal, the second clock signal controls the first tft M1 to be turned on, the signal of the second voltage terminal VGH controls the second tft M2 to be turned on, and the second control signal is transmitted to the pull-up node PU through the first tft M1 and the second tft M2.
Referring to fig. 7, in the pull-down stage H4, the control signal terminal Gn-1 inputs a first control signal, the clock signal terminal CLKn inputs a second clock signal, the second clock signal controls the first tft M1 to be turned on, the signal of the second voltage terminal VGH controls the second tft M2 to be turned on, and the first control signal is transmitted to the pull-up node PU through the first tft M1 and the second tft M2.
In a further embodiment, the first thin film transistor M1 is an N-type metal oxide thin film transistor. As shown in fig. 2, the pull-up node PU is connected to the control signal terminal Gn-1 through the first thin film transistor M1, and when the signal of the control signal terminal Gn-1 is a low level signal and the pull-up node PU is a high level signal, if the leakage current of the first thin film transistor M1 is large, the high level signal of the pull-up node PU will be leaked from the first thin film transistor M1, so that the level of the pull-up node PU cannot be effectively maintained stable, and therefore, it is preferable to use an N-type metal oxide thin film transistor as the first thin film transistor M1. Preferably, a leakage current of less than 10 is used-12The N-type metal oxide thin film transistor A further improves the influence of leakage current on a GOA circuit. More preferably, the channel layer of the N-type metal oxide thin film transistor comprises one or more metal oxide combinations including at least indium gallium zinc oxide, indium gallium tin oxide and indium tin oxide.
In a further embodiment, the pull-up control module 140 further includes a gate of the sixth thin film transistor M6 connected to the output terminal Gn, a first pole of the sixth thin film transistor M6 connected to the second voltage terminal VGH, and a second pole of the sixth thin film transistor M6 connected to the pull-down maintaining module 130. Specifically, the second pole of the sixth tft M6 is connected to the second pole of the eighth tft M8 in the pull-down sustain module 130.
In a further embodiment, the pull-up maintaining module 150 includes a seventh thin film transistor M7 and a third capacitor C3, a gate of the seventh thin film transistor M7 is connected to the pull-up node PU and the first terminal of the third capacitor C3, a first pole of the seventh thin film transistor M7 is connected to the output terminal Gn, and a second pole of the seventh thin film transistor M7 is connected to the second voltage terminal VGH; a second terminal of the third capacitor C3 is connected to the output terminal Gn.
In the pull-up stage H2, the signal at the pull-up node PU controls the seventh tft M7 to be turned on, and the signal at the second voltage terminal VGH is transmitted to the output terminal Gn through the seventh tft M7.
During the pull-down period H4, the signal at the pull-up node PU controls the seventh tft M7 to turn off, and the signal at the second voltage terminal VGH stops being transmitted to the output terminal Gn.
The seventh thin film transistor M7 may be a P-type thin film transistor or an N-type thin film transistor. Preferably, the N-type thin film transistor is an N-type metal oxide transistor, and the P-type thin film transistor is a P-type low-temperature polycrystalline oxide transistor.
When the seventh thin film transistor M7 is an N-type thin film transistor, the seventh thin film transistor M7 is in a conducting state when the signal at the pull-up node PU is a high level signal, so as to transmit the signal at the second voltage terminal VGH to the output terminal Gn.
When the seventh tft M7 is a P-type tft, the seventh tft M7 is in a conducting state when the signal at the pull-up node PU is a low level signal, so as to transmit the signal at the second voltage terminal VGH to the output terminal Gn.
In this application, the pull-up maintaining module 150 transmits the signal of the second voltage terminal VGH to the output terminal Gn under the control of the pull-up node PU, so that the seventh tft M7 preferably employs a tft with a stronger charging capability or a smaller resistance, and does not need to employ an N-type metal oxide tft, and preferably employs an N-type LIPS tft, which has a stronger charging capability, and can rapidly transmit the signal of the second voltage terminal VGH to the output terminal Gn.
It should be noted that the mirror circuit of the GOA circuit of the present application is also within the scope of the present application, for example, the polarities of all the electronic elements in fig. 2 are changed, and those skilled in the art can obtain a corresponding mirror circuit according to the embodiments of the present application.
Please refer to the signal waveform diagram shown in fig. 3, which is analyzed in conjunction with the GOA circuit diagrams of fig. 4 to 7. The following describes specific operation timing of the GOA unit, in this embodiment, the GOA unit includes a pull-down sustain phase H1, a pull-up sustain phase H2, a pull-up sustain phase H3 and a pull-down phase H4 in a time period, wherein the pull-down sustain phase H1 of the next time period is adjacent to the pull-down phase H4 of the previous time period. It should be noted that, compared to the signal waveform diagram shown in fig. 3, in other time periods, the time period of the signal waveform diagram may be shifted forward or backward by one or more phases.
Referring to fig. 3 and 4, in the pull-down hold period H1, the control signal terminal Gn-1 inputs the second control signal as a high level signal, the clock signal terminal CLKn inputs the first clock signal as a low level signal, the first voltage terminal VGL is a low level signal, and the second voltage terminal VGH is a high level signal.
At this time, the first thin film transistor M1 is turned off, the fourth thin film transistor M4 is turned on, the low level signal of the first voltage terminal VGL is input from the fourth thin film transistor M4 to the gate of the third thin film transistor M3, and the third thin film transistor M3 is turned off.
The pull-up node PU maintains the low signal of the pull-down period H4 (refer to the pull-down period H4) of the previous time period, and the fifth tft M5 is kept turned off.
The pull-down node PD and the second capacitor C2 are charged in a pull-down period H4 (specifically, refer to a pull-down period H4 described below) of a previous time period, the pull-down node PD is a high level signal, and the second capacitor C2 is fully charged, so that in the pull-down maintaining period H1 of the present signal scanning period, the pull-down node PD continues to maintain the high level signal through the second capacitor C2, the eighth thin film transistor M8 and the ninth thin film transistor M9 are turned on when the pull-down node PD is the high level signal, and the low level signal of the first voltage terminal VGL is transmitted to the output terminal Gn through the eighth thin film transistor M8 and the ninth thin film transistor M9, that is, in the pull-down maintaining period H1, the output terminal Gn outputs the low level signal.
In the pull-down maintaining stage H1, the pull-down node PD is a high level signal, the pull-down node PD is connected to the third thin film transistor M3 and the fifth thin film transistor M5, and the third thin film transistor M3 and the fifth thin film transistor M5 employ N-type indium gallium zinc oxide thin film transistors with low leakage current, so that the pull-down node PD can be effectively prevented from being influenced by the third thin film transistor M3 and the fifth thin film transistor M5, and the pull-down node PD maintains a stable high level signal.
Referring to fig. 3 and 5, in the pull-up stage H2, the control signal terminal Gn-1 inputs the second control signal as a high level signal, the clock signal terminal CLKn inputs the second clock signal as a high level signal, the first voltage terminal VGL is a low level signal, and the second voltage terminal VGH is a high level signal.
At this time, the fourth thin film transistor M4 is turned on, the low level signal of the first voltage terminal VGL is inputted to the gate of the third thin film transistor M3 from the fourth thin film transistor M4, and the third thin film transistor M3 is kept turned off.
The first thin film transistor M1 is turned on, a high level signal of the control signal terminal Gn-1 is inputted from the first thin film transistor M1 to the gate of the fifth thin film transistor M5, the fifth thin film transistor M5 is turned on, a low level signal of the first voltage terminal VGL is inputted from the fifth thin film transistor M5 to the gates of the eighth thin film transistor M8 and the ninth thin film transistor M9, the pull-down node PD transitions from a high level signal to a low level signal, and the eighth thin film transistor M8 and the ninth thin film transistor M9 are turned off.
The gate of the second tft M2 is connected to the second voltage VGH, the second tft M2 is turned on, the high level signal of the control signal terminal Gn-1 is transmitted from the first tft M1 and the second tft M2 to the gate of the seventh tft M7, the pull-up node PU jumps from the low level signal to the high level signal, the seventh tft M7 is turned on and charges the third capacitor C3, and the high level signal of the second voltage terminal VGH is transmitted from the seventh tft M7 to the output terminal Gn, that is, the output terminal Gn outputs the high level signal in the pull-up stage H2.
The first pole of the seventh tft M7 is connected to the gate of the sixth tft M6, so that the high level signal of the second voltage terminal VGH is also transmitted from the seventh tft M7 to the gate of the sixth tft M6, and the sixth tft M6 is turned on, at this time, the high level signal of the second voltage terminal VGH is transmitted from the sixth tft M6 to the first pole of the ninth tft M9, and the ninth tft M9 is further maintained in an off state, so that the high level signal transmitted from the seventh tft M7 to the output terminal Gn is prevented from flowing out of the ninth tft M9, and the stability of the high level signal output by the output terminal Gn is not affected. That is, the sixth thin film transistor M6 is used to maintain the output terminal Gn to output a high-level signal stably, so as to avoid the high-level signal output by the output terminal Gn from being distorted due to part of the voltage being pulled by the ninth thin film transistor M9.
Referring to fig. 3 and 6, in the pull-up hold stage H3, the first control signal is input to the control signal terminal Gn-1 as a low level signal, the first clock signal is input to the clock signal terminal CLKn as a low level signal, the first voltage terminal VGL as a low level signal, and the second voltage terminal VGH as a high level signal.
At this time, the first, third, and fourth thin film transistors M1, M3, and M4 are turned off. The second tft M2 is still turned on, since the third capacitor C3 is fully charged during the pull-up period H2, the pull-up node PU continues to maintain to the high level signal under the action of the third capacitor C3, that is, the gate of the seventh tft M7 is the high level signal, the seventh tft M7 is turned on, the high level signal of the second voltage terminal VGH continues to be transmitted from the seventh tft M7 to the output terminal Gn, and the sixth tft M6 continues to maintain the stability of the output of the high level signal from the output terminal Gn, that is, the output terminal Gn outputs the high level signal during the pull-up maintenance period H3.
The high level signal of the pull-up node PU is transmitted from the second thin film transistor M2 to the gate of the fifth thin film transistor M5, the fifth thin film transistor M5 is turned on, the pull-down node PD continues to maintain the low level signal, and the eighth thin film transistor M8 and the ninth thin film transistor M9 continue to maintain the off state.
At this stage, the second thin film transistor M2 is connected to the first thin film transistor M1, and if the leakage current of the first thin film transistor M1 is large, a part of the voltage of the pull-up node PU is pulled away, which results in instability of the high level signal of the pull-up node PU and thus instability of the signal output by the output terminal Gn.
Referring to fig. 3 and 7, in the pull-down stage H4, the control signal terminal Gn-1 inputs the first control signal as a low level signal, the clock signal terminal CLKn inputs the second clock signal as a high level signal, the first voltage terminal VGL is a low level signal, and the second voltage terminal VGH is a high level signal.
At this time, the fourth thin film transistor M4 is turned off, the first thin film transistor M1 is turned on, a low level signal of the control signal terminal Gn-1 is transmitted to the fifth thin film transistor M5 and the seventh thin film transistor M7 through the first thin film transistor M1, and the fifth thin film transistor M5 and the seventh thin film transistor M7 are turned off.
A high level signal of the clock signal terminal CLKn is transmitted to the second terminal of the first capacitor C1 and the second pole of the third tft M3, the first capacitor C1 jumps from a low level signal to a high level signal, the first capacitor C1 is turned on, a high level signal is transmitted to the gate of the third tft M3 connected to the first terminal of the first capacitor C1, and the third tft M3 is turned on.
The high level signal of the clock signal terminal CLKn is transmitted to the pull-down node PD through the turned-on third tft M3 to charge the pull-down node PD and the second capacitor C2, the eighth tft M8 and the ninth tft M9 are turned on, and the low level signal of the first voltage terminal VGL is transmitted to the output terminal Gn from the eighth tft M8 and the ninth tft M9, that is, the output terminal Gn outputs the low level signal in the pull-down stage H4.
At this stage, when the leakage current of the fifth thin film transistor M5 connected to the pull-down node PD is large, the voltage of the pull-down node PD is pulled down, which affects the stability of the voltage of the pull-down node PD, and further causes distortion of the signal output by the output terminal Gn, so in this embodiment, it is preferable to adopt an N-type indium gallium zinc oxide thin film transistor with low leakage current as the fifth thin film transistor M5, which can improve the influence of the leakage current. When the leakage current of the fourth tft M4 connected to the first end of the first capacitor C1 is large, the current of the first capacitor C1 flows out from the fourth tft M4, so that the gate of the third tft M3 cannot effectively receive a high-level signal, the third tft M3 is turned off in advance, the voltage of the pull-down node PD jumps to a low-level signal in advance, the eighth tft M8 and the ninth tft M9 are turned off in advance, and finally the signal of the output terminal Gn is turned off in advance. Therefore, in this embodiment, an N-type indium gallium zinc oxide thin film transistor with low leakage current is preferably used as the fourth thin film transistor M4, so that the influence of leakage current can be improved, and the signal at the output terminal Gn can be stably output.
The duration of the GOA circuit in the pull-down stage H4 is relatively long, and the third thin film transistor M3 and the fifth thin film transistor M5 employ the N-type inga-zno thin film transistor with low leakage current, so as to effectively improve the influence of the leakage current on the signal output by the output terminal Gn.
In other embodiments, at least one of the first thin film transistor M1, the third thin film transistor M3, the fourth thin film transistor M4, and the fifth thin film transistor M5 may be an N-type indium gallium zinc oxide thin film transistor, which may also improve the effect of leakage current.
Referring to fig. 8, the present invention further provides a display panel 20, wherein the display panel 20 includes the GOA circuit 10 as described above. In a further embodiment, the refresh rate of the display panel 20 is 1Hz-120 Hz. Wherein the refresh rate refers to a minimum repetition period of the control signal. In the present invention, it may be a minimum repetition period of the control signal at the control signal terminal or a minimum repetition period of the clock signal at the clock signal terminal. For the display panel with the refresh rate of 1Hz to 120Hz, the GOA circuit works stably, and the output waveform of the GOA circuit is not influenced by the dynamic change of the refresh rate. Preferably, the refresh rate of the display panel 20 is 1Hz to 30Hz, or the refresh rate of the display panel 20 is 30Hz to 60Hz, or the refresh rate of the display panel 20 is 30Hz to 90Hz, or the refresh rate of the display panel 20 is 90Hz to 120Hz, or the refresh rate of the display panel 20 is 1Hz to 60Hz, or the refresh rate of the display panel 20 is 60Hz to 120 Hz.
Referring to fig. 9, the present invention further provides an electronic device 30, wherein the electronic device 30 includes the GOA circuit 10 or includes the display panel 20. The electronic device 30 may be, but not limited to, an electronic book, a smart Phone (e.g., an Android Phone, an iOS Phone, a Windows Phone, etc.), a tablet computer, a flexible palm computer, a flexible notebook computer, a Mobile Internet device (MID, Mobile Internet Devices), a wearable device, etc., or may be an Organic Light-Emitting Diode (OLED) electronic device, an Active Matrix Organic Light-Emitting Diode (AMOLED) electronic device.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the present invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims (21)

1. A GOA circuit is characterized by comprising a plurality of cascaded GOA units, wherein each GOA unit comprises a first pull-down control module, a second pull-down control module and a pull-down maintaining module, each GOA unit further comprises a first voltage end, a clock signal end and a control signal end, each first voltage end is used for providing a signal, and one scanning period of each GOA unit comprises a pull-up stage and a pull-down stage;
the first pull-down control module is connected with the clock signal end and used for outputting a signal of the clock signal end to a pull-down node in a pull-down stage;
the second pull-down control module is connected with the first voltage end and used for outputting a signal of the first voltage end to a pull-down node in a pull-up stage;
the pull-down maintaining module is connected with the first pull-down control module and the second pull-down control module and is used for controlling a signal of the first voltage end to be output to an output end in a pull-down stage according to a received signal of the pull-down node and controlling the signal of the first voltage end to stop being output to the output end in a pull-up stage according to the received signal of the pull-down node;
at least one of the first pull-down control module and the second pull-down control module includes at least one thin film transistor of a type different from that of the thin film transistor in the pull-down sustain module.
2. The GOA circuit of claim 1, wherein at least one of the first pull-down control module and the second pull-down control module comprises at least one thin film transistor that is an N-type metal oxide thin film transistor.
3. The GOA circuit of claim 2, wherein the first pull-down control module comprises a fourth TFT, a third TFT and a first capacitor, a gate of the fourth TFT is connected to the control signal terminal, a first pole of the fourth TFT is connected to the first voltage terminal, and a second pole of the fourth TFT is connected to a first terminal of the first capacitor and a gate of the third TFT; a second end of the first capacitor is connected with a second pole of the third thin film transistor and the clock signal end; a first pole of the third thin film transistor is connected with the pull-down node;
in a pull-down stage, a first control signal is input into the control signal terminal, a second clock signal is input into the clock signal terminal, the first control signal controls the fourth thin film transistor to be turned off, the first capacitor transmits a second clock signal of the clock signal terminal to the gate of the third thin film transistor to control the third thin film transistor to be turned on, and the second clock signal of the clock signal terminal is transmitted to the pull-down node through the third thin film transistor.
4. The GOA circuit of claim 3, wherein at least one of the fourth thin film transistor and the third thin film transistor is an N-type metal oxide thin film transistor.
5. The GOA circuit according to claim 2, wherein the second pull-down control module comprises a fifth TFT, a gate of the fifth TFT is connected to the control signal terminal, a first pole of the fifth TFT is connected to the first voltage terminal, and a second pole of the fifth TFT is connected to the pull-down node;
in the pull-up stage, a second control signal is input into the control signal terminal, the fifth thin film transistor is turned on according to the second control signal of the control signal terminal, and the signal of the first voltage terminal is transmitted to the pull-down node.
6. The GOA circuit of claim 5, wherein the fifth thin film transistor is an n-type metal oxide thin film transistor.
7. The GOA circuit of claim 1, wherein the pull-down maintaining module comprises an eighth TFT, a ninth TFT and a second capacitor, the pull-down node is connected to the gate of the eighth TFT, the gate of the ninth TFT and a second terminal of the second capacitor, a first pole of the eighth TFT is connected to the first voltage terminal, and a second pole of the eighth TFT is connected to the first pole of the ninth TFT; a second pole of the ninth thin film transistor is connected with the output end; the first end of the second capacitor is connected with the first voltage end;
in a pull-down stage, the signal of the pull-down node controls the eighth thin film transistor and the ninth thin film transistor to be turned on, and the signal of the first voltage end is transmitted to an output end through the eighth thin film transistor and the ninth thin film transistor;
in the pull-up stage, the signal of the pull-down node controls the eighth thin film transistor and the ninth thin film transistor to be turned off, and the signal of the first voltage end stops being transmitted to the output end.
8. The GOA circuit of claim 7, wherein the eighth thin film transistor and the ninth thin film transistor are P-type thin film transistors or N-type thin film transistors;
when the eighth thin film transistor and the ninth thin film transistor are N-type thin film transistors, the eighth thin film transistor and the ninth thin film transistor are in a conducting state when a signal of the pull-down node is a high-level signal, so as to transmit a signal of the first voltage end to an output end;
when the eighth thin film transistor and the ninth thin film transistor are P-type thin film transistors, the eighth thin film transistor and the ninth thin film transistor are in a conducting state when a signal of the pull-down node is a low-level signal, so as to transmit a signal of the first voltage end to an output end.
9. The GOA circuit of claim 1, wherein the GOA unit further comprises a pull-up control module and a pull-up maintenance module, the GOA unit further comprising a second voltage terminal;
the pull-up control module is connected with the control signal end and used for outputting a signal of the control signal end to a pull-up node in a pull-up stage and a pull-down stage;
the pull-up maintaining module is connected with the pull-up control module and used for outputting a signal of the second voltage end to an output end in a pull-up stage according to the received signal of the pull-up node, and stopping outputting the signal of the second voltage end to the output end in a pull-down stage according to the received signal of the pull-up node.
10. The GOA circuit of claim 9, wherein the pull-up control module comprises a first thin film transistor and a second thin film transistor, a gate of the first thin film transistor being connected to the clock signal terminal, a first pole of the first thin film transistor being connected to the control signal terminal, a second pole of the first thin film transistor being connected to a first pole of the second thin film transistor; the grid electrode of the second thin film transistor is connected with the second voltage end, and the second pole of the second thin film transistor is connected with the pull-up node;
in a pull-up stage, a second control signal is input into the control signal terminal, a second clock signal is input into the clock signal terminal, the second clock signal controls the conduction of the first thin film transistor, a signal of the second voltage terminal controls the conduction of the second thin film transistor, and the second control signal is transmitted to the pull-up node through the first thin film transistor and the second thin film transistor;
in a pull-down stage, a first control signal is input into the control signal end, a second clock signal is input into the clock signal end, the second clock signal controls the first thin film transistor to be conducted, a signal of the second voltage end controls the second thin film transistor to be conducted, and the first control signal is transmitted to the pull-up node through the first thin film transistor and the second thin film transistor.
11. The GOA circuit of claim 10, wherein the first thin film transistor is an N-type metal oxide thin film transistor.
12. The GOA circuit of claim 10, wherein the pull-up control module further comprises a sixth thin film transistor, a gate of the sixth thin film transistor is connected to the output terminal, a first pole of the sixth thin film transistor is connected to the second voltage terminal, and a second pole of the sixth thin film transistor is connected to the pull-down sustain module.
13. The GOA circuit of claim 9, wherein the pull-up maintenance module comprises a seventh tft and a third capacitor, the gate of the seventh tft is connected to the pull-up node and the first terminal of the third capacitor, the first pole of the seventh tft is connected to the output terminal, and the second pole of the seventh tft is connected to the second voltage terminal; the second end of the third capacitor is connected with the output end;
in a pull-up stage, a signal of the pull-up node controls the seventh thin film transistor to be switched on, and a signal of the second voltage end is transmitted to an output end through the seventh thin film transistor;
in a pull-down stage, the signal of the pull-up node controls the seventh thin film transistor to be turned off, and the signal of the second voltage end stops being transmitted to the output end.
14. The GOA circuit of claim 13, wherein the seventh thin film transistor is a P-type thin film transistor or an N-type thin film transistor;
when the seventh thin film transistor is an n-type thin film transistor, the seventh thin film transistor is in a conducting state when a signal of the pull-up node is a high-level signal, so as to transmit a signal of the second voltage end to an output end;
when the seventh thin film transistor is a P-type thin film transistor, the seventh thin film transistor is in a conducting state when a signal of the pull-up node is a low level signal, so as to transmit a signal of the second voltage end to an output end.
15. The GOA circuit according to claim 1, wherein when the output terminal of the GOA circuit continuously outputs signals, if the frequency of the control signal terminal is changed, the refresh rate of the GOA circuit is dynamically changed.
16. The GOA circuit of claim 1, wherein the GOA circuit has a refresh rate of 1Hz-120 Hz.
17. A GOA circuit according to claim 8 or 14, wherein the N-type thin film transistor is an N-type metal oxide transistor and the P-type thin film transistor is a P-type low temperature poly-oxide transistor.
18. The GOA circuit of any of claims 2-6, 11, and 17, wherein the N-type metal oxide transistor channel layer comprises at least one or more metal oxide combinations of indium gallium zinc oxide, indium gallium tin oxide, and indium tin oxide.
19. The GOA circuit of claim 1, wherein at least one of the first pull-down control module and the second pull-down control module comprises at least one thin film transistor having a leakage current of less than 10-12A。
20. A display panel comprising a GOA circuit according to any one of claims 1-19.
21. An electronic device, characterized in that the electronic device comprises a GOA circuit according to any one of claims 1 to 19 or comprises a display panel according to claim 20.
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