CN116487377A - Semiconductor package assembly and electronic device - Google Patents

Semiconductor package assembly and electronic device Download PDF

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Publication number
CN116487377A
CN116487377A CN202310037177.8A CN202310037177A CN116487377A CN 116487377 A CN116487377 A CN 116487377A CN 202310037177 A CN202310037177 A CN 202310037177A CN 116487377 A CN116487377 A CN 116487377A
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CN
China
Prior art keywords
chip
package
electronic device
silicon
memory
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CN202310037177.8A
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Chinese (zh)
Inventor
朱立寰
郑凯哲
林明宗
刘胜峯
游季格
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MediaTek Inc
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MediaTek Inc
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Priority claimed from US18/147,986 external-priority patent/US20230238360A1/en
Application filed by MediaTek Inc filed Critical MediaTek Inc
Publication of CN116487377A publication Critical patent/CN116487377A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/162—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits the devices being mounted on two or more different substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

The invention provides a semiconductor package assembly and an electronic device. In one embodiment, the semiconductor package assembly provided by the present invention may include: a base having a first surface and a second surface opposite the first surface; a system-on-chip (SOC) package disposed on the first surface of the base, the SOC package comprising: an SOC chip with a pad; and a redistribution layer (RDL) structure electrically connected to the SOC chip through the bond pad; the semiconductor package assembly further includes a memory package 400 stacked on the SOC package, the memory package including: a memory package substrate having a top surface and a bottom surface; and a memory chip mounted on the top surface of the memory package substrate and electrically connected to the memory package substrate; the semiconductor package assembly further includes a silicon capacitor chip disposed on and electrically connected to the second surface of the submount.

Description

Semiconductor package assembly and electronic device
Technical Field
The present invention relates to a semiconductor package and an electronic device, and more particularly, to a semiconductor package and an electronic device using a silicon capacitor as a heat sink.
Background
Package-On-Package (PoP) assemblies are an integrated circuit packaging method for combining vertically discrete System-On-Chip (SOC) and memory packages. Two or more packages are mounted on top of each other, i.e. stacked, and signals are routed between them using standard interfaces. This allows for higher component densities in mobile phones, personal Digital Assistants (PDAs), and digital cameras.
Improving heat dissipation, fine-pitch, fine-size routing, and package height shrink are important approaches to improving electrical performance for high-end smart phone applications.
Accordingly, there is a need for a new electronic device that includes a semiconductor package assembly.
Disclosure of Invention
The invention provides a semiconductor package assembly and an electronic device.
In one embodiment, the semiconductor package assembly provided by the present invention may include: a base having a first surface and a second surface opposite the first surface; a system-on-chip (SOC) package disposed on the first surface of the base, the SOC package comprising: an SOC chip with a pad; and a redistribution layer (RDL) structure electrically connected to the SOC chip through the bond pad; the semiconductor package assembly further includes a memory package 400 stacked on the SOC package, the memory package including: a memory package substrate having a top surface and a bottom surface; and a memory chip mounted on the top surface of the memory package substrate and electrically connected to the memory package substrate; the semiconductor package assembly further includes a silicon capacitor chip disposed on and electrically connected to the second surface of the submount.
In one embodiment, the electronic device provided by the invention comprises: a first base having a first surface and a second surface opposite the first surface; a system-on-chip (SOC) package stacked on the first surface of the first base, the SOC package comprising: an SOC chip and a redistribution layer (RDL) structure having a bond pad electrically connected to the SOC chip through the bond pad; the electronic device further includes a memory package stacked on the SOC package, the memory package including: a memory package substrate and a memory chip having a top surface and a bottom surface, mounted on the top surface of the memory package substrate and electrically connected to the memory package substrate; the electronic device further comprises a silicon capacitor chip arranged on the second surface of the first base; a heat dissipation structure connected to the silicon capacitor chip; and a screen disposed on the heat dissipation structure.
Drawings
Fig. 1 is a cross-sectional view of an electronic device 600A including a semiconductor package assembly 500 according to some embodiments of the invention.
Fig. 2 is a cross-sectional view of an electronic device 600B including a semiconductor package assembly 500 according to some embodiments of the invention.
Fig. 3 is a cross-sectional view of an electronic device 600C including a semiconductor package assembly 500 according to some embodiments of the invention.
Detailed Description
The following description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined with reference to the appended claims.
The present inventive concept will be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments of the inventive concept are shown. The advantages and features of the inventive concept and the method of implementing them will be apparent from the following exemplary embodiments described in more detail with reference to the accompanying drawings. It should be noted, however, that the present inventive concept is not limited to the following exemplary embodiments and may be implemented in various forms. Accordingly, the exemplary embodiments are provided only for the purpose of disclosing the inventive concept and letting those skilled in the art understand the category of the inventive concept. Furthermore, the drawings described are only schematic and are non-limiting. In the drawings, the size of some of the elements may be exaggerated and not drawn on scale for illustrative purposes. The dimensions and relative dimensions in the drawings do not correspond to actual dimensions in the practice of the invention.
Fig. 1 is a cross-sectional view of an electronic device 600A including a semiconductor package assembly 500 according to some embodiments of the invention. In some embodiments, electronic device 600A is part of a mobile phone, a Personal Digital Assistant (PDA), and a digital camera. As shown in fig. 1, the electronic device 600A includes bases (base) 200A and 200B, a semiconductor package assembly 500, a silicon capacitor chip (die) 430A, a heat dissipation structure 450, a back plane 452, and a screen 460.
In some embodiments, the semiconductor package assembly 500 is a three-dimensional (3D) package on package (PoP) semiconductor package assembly. The semiconductor package assembly 500 may include at least two vertically stacked wafer-level semiconductor packages mounted on the base 200A and disposed between the bases 200A and 200B. As shown in fig. 1, in some embodiments, a semiconductor package assembly 500 includes a system on a chip (SOC) package 300 and a memory package 400 vertically stacked on the SOC package 300.
As shown in fig. 1, the pedestals 200A and 200B are disposed between the backplate 452 and the screen 460. The back plate 452 is disposed above the semiconductor package assembly 500 in a manner opposite to the screen 460. The semiconductor package 500 is used to cover and protect the pedestals 200A and 200B, and the semiconductor package 500, the silicon capacitor chip 430A and the heat dissipation structure 450 are located inside the electronic device 600A. The screen 460 may be provided as a combination of input (e.g., a touch panel) and output (e.g., a display) devices. Each of the bases 200A and 200B, for example, a Printed Circuit Board (PCB), may be formed of polypropylene (PP). It should also be noted that the susceptors 200A and 200B may be of single-layer or multi-layer construction. The base 200A has a first surface 200A1 and a second surface 200A2 opposite the first surface 200A 1. The base 200A is provided for the semiconductor package 500 disposed on the first surface 200A 1. The base 200B is disposed on the first surface 200A1 of the base 200A and electrically connected to the base 200A.
As shown in fig. 1, a plurality of pads (not shown) and/or conductive traces (not shown) are disposed on the first surface 200A1 of the base 200A. In one embodiment, the conductive traces may include signal traces or ground traces for input/output (I/O) connection of the SOC package 300 and the memory package 400. In addition, the SOC package 300 is directly mounted to the trace lines. In some other embodiments, pads are disposed on the first surface 200A1 of the base 200A, connected to different ends of the wire trace. These pads are used by the SOC package 300a that is directly mounted on these pads.
The SOC package 300 is disposed on the first surface 200A1 of the base 200A. The SOC package 300 includes a system-on-chip (SOC) chip 302 and a redistribution layer (redistribution layer, RDL) structure 316F. For example, system On Chip (SOC) chip 302 may include a logic chip including a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), a Dynamic Random Access Memory (DRAM) controller, or any combination thereof.
As shown in fig. 1, SOC chip 302 has a back side 302B and a front side 302F. The SOC chip 302 is fabricated by flip-chip technology. The back side 302B of the SOC chip 302 may be proximate to the top side 300T of the SOC package 300. Pads 304 of the SOC chip 302 are disposed on the front side 302F to electrically connect to circuitry (not shown) of the SOC chip 302. In some embodiments, the bond pad 304 belongs to the uppermost metal layer of an interconnect structure (not shown) of the SOC chip 302. The pads 304 of the SOC chip 302 are in contact with corresponding vias 308. The SOC chip 302 is connected to a redistribution layer (RDL) structure 316F through vias 308.
A redistribution layer (RDL) structure 316F (e.g., a front side RDL structure) is disposed on the front side 302F of the SOC chip 302. In some other embodiments, the SOC package 300 further includes a redistribution layer (RDL) structure 316B (e.g., a backside RDL structure) disposed on the backside 302B of the SOC chip 302. RDL structure 316F is electrically connected to SOC chip 302 through bond pads 304 and vias 308 of SOC chip 302. In some embodiments, each of RDL structures 316F and 316B may have one or more conductive traces 318 disposed in one or more intermetallic dielectric (intermetal dielectric, IMD) layers 317. Conductive trace 318 is electrically connected to respective RDL contact pads 320F and 320B of RDL structures 316F and 316B. RDL contact pads 320F and 320B are exposed to openings of a corresponding solder mask layer (not shown). It should be noted, however, that the number of conductive traces 318, the number of IMD layers 317, and the number of RDL contact pads 320F and 320B shown in fig. 1 may be the same. Fig. 1 is merely an example, and is not intended to limit the present invention.
As shown in fig. 1, SOC package 300 also includes a conductive structure 322 disposed between redistribution layer (RDL) structure 316F and submount 200A. Conductive structures 322 are disposed on and in contact with RDL contact pads 320F remote from SOC chip 302. In some embodiments, the conductive structures 322 may include conductive bump structures, such as copper bump or solder bump structures, conductive pillar structures, wire structures, or conductive paste structures.
As shown in fig. 1, SOC package 300 also includes a molding compound 312 disposed between RDL structures 316F and 316B. The molding compound 312 surrounds the SOC chip 302 and fills any gaps around the SOC chip 302 and between RDL structures 316F and 316B. The molding compound 312 is in contact with redistribution layer (RDL) structures 316F and 316B and the SOC chip 302. In some embodiments, the molding compound 312 may be formed of a non-conductive material, such as an epoxy, a resin, a moldable polymer, or the like. The molding compound 312 may be applied while in a substantially liquid state and then may be cured in, for example, an epoxy or resin by a chemical reaction. In some other embodiments, the molding compound 312 may be an Ultraviolet (UV) or thermally curable polymer that is applied as a gel or malleable solid that can be disposed around the SOC chip 302 and then cured using a UV or thermally curable process. The molding compound 312 may be cured with a mold.
As shown in fig. 1, the SOC package 300 also includes a conductive structure 314 that passes through the molding compound 312 and is electrically connected to the RDL structures 316F and 316B, SOC chip 302 and the memory package 400. Conductive structure 314 is disposed between RDL structures 316F and 316B. Conductive structures 314 and SOC chip 302 may be disposed side-by-side. In addition, the conductive structures 314 may be arranged in an array along parallel edges (not shown) of the SOC package 300. Thus, SOC chip 302 is disposed between conductive structures 314. In some embodiments, conductive structure 314 may include a via (TV) structure, or a conductive pillar structure such as a copper pillar structure.
As shown in FIG. 1, SOC package 300 also includes an electronic component 330 mounted on RDL structure 316F opposite to SOC chip 302. In some embodiments, electronic component 330 has pads 332 thereon and is electrically connected to conductive traces 318 of RDL structure 316F. In some embodiments, the electronic component 330 is disposed between the conductive structures 322. The electronic component 330 need not be covered by molding compound. In some embodiments, the electronic assembly 330 includes an integrated passive device (Integrated Passive Device, IPD) including a capacitor, an inductor, a resistor, or a combination thereof. In some embodiments, electronic component 330 includes a DRAM chip.
As shown in fig. 1, a memory package 400 is stacked on an SOC package 300 through a bonding process. In some embodiments, memory package 400 comprises a Dynamic Random Access Memory (DRAM) package or another suitable memory package. In some embodiments, memory package 400 includes a memory package substrate (submount) 418, a conductive structure 429, and at least one memory chip, e.g., two memory chips 402 and 404 stacked on memory package substrate 418. In some embodiments, memory chip 402 includes a Dynamic Random Access Memory (DRAM) chip or another suitable memory chip. The memory package substrate 418 has a top surface 420 and a bottom surface 422. For example, the top surface 420 may serve as the die attach surface 420, while the bottom surface 422 may serve as the bump attach surface 422 opposite the die attach surface 420. In this embodiment, as shown in FIG. 1, there are two memory chips 402 and 404 mounted on a top surface (die attach surface) 420 of a memory package substrate 418. Memory chip 404 is stacked on memory chip 402 using an adhesive (not shown), and memory chip 402 is mounted on chip attach side 420 of memory package substrate 418 by an adhesive (not shown). Memory chips 402 and 404 may be electrically connected to memory package substrate 418 using bond wires 414 and 416 and metal pads 408 and 410. However, the number of stacked memory chips is not limited to the disclosed embodiments. Alternatively, memory chips 402 and 404 may be arranged side-by-side. Thus, memory chips 402 and 404 are mounted on top surface (die attach surface) 420 of memory package substrate 418 by an adhesive.
As shown in fig. 1, memory package substrate 418 may include circuitry 428 and metal pads 424, 426, and 427. Metal pads 424 and 426 are disposed on top of circuit 428 near top surface (die attach side) 420. Metal pads 427 are disposed on the bottom of the circuit 428 near the bottom surface (bump attach surface) 422 of the memory package substrate 418. The circuitry 428 of the memory package 400 is interconnected to the conductive traces 318 of the RDL structure 316B by conductive structures 429 disposed on the bottom (bump attach) surface 422 of the memory package substrate 418. In some embodiments, conductive structures 429 of memory package 400 are electrically coupled to conductive traces 318 of RDL structure 316F of SOC package 300 through RDL structure 316B and conductive structures 314 passing through molding compound 312 between memory package 400 and RDL structure 316F of SOC package 300. In some embodiments, conductive structures 429 may include conductive bump structures, such as copper bump or solder bump structures, conductive pillar structures, or conductive paste structures.
In some embodiments, as shown in fig. 1, memory package 400 further includes a molding compound 412 that covers a top surface 420 of memory package substrate 418, packages memory chips 402 and 404, and bond wires 414 and 416. The molding compounds 312 and 412 may include the same or similar materials and manufacturing processes.
As shown in fig. 1, one or more discrete silicon capacitor chips 430A are disposed on a second surface 200A2 of the submount 200A opposite the semiconductor package assembly 500 and electrically connected to the second surface 200A2. The silicon capacitor chip 430A is formed of a silicon substrate 432 and is formed by a semiconductor process. In some embodiments, the silicon capacitor chip 430A may include a first electrode (i.e., a silicon substrate 432), a dielectric material 434, a second electrode 436, a passivation layer 437, a first electrode pad 432P, a second electrode pad 436P, and conductive structures 432S and 436S. The silicon substrate 432 has a front surface (bump attach surface) 432F and a back surface 432B. Further, the silicon substrate 432 has a trench (not shown) formed from the front surface 432F and extending into a portion of the silicon substrate 432. A dielectric material 434 is arranged in the trench. A second electrode 436 formed of doped silicon or a conductive material fills the trench and covers the dielectric material 434 such that the dielectric material 434 is sandwiched between the first electrode and the second electrode 436 formed of the silicon substrate 432. The passivation layer 437 covers the silicon substrate 432 and the second electrode 436. The first electrode pad 432P is disposed on the protection layer 437 and electrically connected to the silicon substrate 432. The second electrode pad 436 is disposed on the passivation layer 437 and electrically connected to the second electrode 436. The conductive structures 432S and 436S are disposed on the front surface (bump attach surface) 432F of the silicon substrate 432 and electrically connected to the corresponding electrode pads 432P and 436P. In some embodiments, the back side 432B of the silicon substrate forms a top surface of the silicon capacitor chip 430A remote from the conductive structures 432S and 436S. In some embodiments, conductive structures 314, 332, 429, 432S, and 436S may have the same or similar structures.
In some embodiments, the thermal conductivity of the silicon capacitor chip 430A (about 150W/mK) is much higher than the thermal conductivity of air (about 0.026W/mK). In some embodiments, the silicon capacitor chip 430A formed from silicon feedstock may have a desired height (up to about 700 μm) that is much greater than the height of a conventional multilayer ceramic capacitor (Multilayer Ceramic Capacitor, MLCC) assembly. Thus, the silicon capacitor chip 430A may be in contact with the heat sink structure 450 and act as an in-situ heat sink to dissipate heat directly from the system-on-a-chip (SOC) package 300 to the screen 460.
As shown in fig. 1, the electronic device 600A further includes an underfill 438 that fills the gap between the silicon capacitor chip 430A and the submount 200A to reduce the thermal resistance from the SOC package 300 to the silicon capacitor chip 430A. In addition, the underfill 438 may fill the gap between adjacent silicon capacitor chips 430A. Conductive structures 432S and 436S are surrounded by an underfill 438 between silicon capacitor chip 430A and submount 200A. In some embodiments, the underfill 438 may surround and contact a portion of the silicon substrate 432 to further reduce the thermal resistance from the SOC package 300 to the silicon capacitor chip 430A. In some embodiments, the underfill 438 comprises capillary underfill (capillary underfill, CUF), molded Underfill (MUF), or a combination thereof.
As shown in fig. 1, the electronic device 600A further includes one or more discrete electronic components 440 disposed on the second surface 200A2 of the base 200A and beside the silicon capacitor chip 430A. In some embodiments, the electronic component 440 is electrically connected to the base 200A using the conductive structure 440B. In some embodiments, the electronic component 440 includes a power management integrated circuit (Power Management Integrated Circuit, PMIC). In some embodiments, electronic component 440 includes an Integrated Passive Device (IPD) including a capacitor, an inductor, a resistor, or a combination thereof. In some embodiments, electronic component 440 includes a DRAM chip. In some embodiments, conductive structures 314, 332, 429, 432S, 436S, and 440B may have the same or similar structure.
As shown in fig. 1, a heat dissipation structure 450 is disposed on the semiconductor package 500 and the pedestals 200A and 200B. In addition, the screen 460 is disposed above the heat dissipation structure 450, and the back plate 452 is disposed below the base 200A. In some embodiments, heat dissipation structure 450 is arranged to dissipate heat from SOC package 300 of electronic device 600A. The heat dissipation structure 450 is disposed on the second surface 200A2 of the base 200A opposite to the semiconductor package 500. In addition, a heat dissipation structure 450 is connected to the silicon capacitor chip 430A. Accordingly, the heat dissipation structure 450 is connected to the SOC package 300 through the silicon capacitor chip 430A and the submount 200A.
In some embodiments, the heat dissipating structure 450 includes a thermal interface material (Thermal Interface Material, TIM) 442 (or thermally conductive paste), a heat dissipating plate 444, and a carbon-based material film 446. The thermal interface material 442 and the top surface of the silicon capacitor chip 430A (i.e., the back surface 432B of the silicon substrate 432) are in contact without a gap (air gap) therebetween. A heat dissipation plate 444 is disposed on the thermal interface material 442 and in contact with the thermal interface material 442 such that the thermal interface material 442 is connected between the silicon capacitor chip 430A and the heat dissipation plate 444. Accordingly, the thermal resistance from the SOC package 300 may further reduce the impact on the heat dissipating plate 444. The heat dissipating plate 444 may dissipate heat in one dimension (e.g., x-direction or y-direction) or two dimensions (e.g., x-direction and y-direction). Further, a carbon-based material film 446 having excellent thermal conductivity is provided on (and/or in contact with) the heat dissipation plate 444. In some embodiments, the dimension D2 of the heat dissipation structure 450 is larger than the dimension D1 of the semiconductor package assembly 500 to improve heat dissipation capability. Accordingly, heat dissipation from the SOC package 300 to the screen 460 (or external environment) may be enhanced by using a thermal interface material 442 in contact with the silicon capacitor chip 430A, filling an air gap (having low thermal conductivity) between the capacitor chip 430A and the heat dissipating plate 444 silicon. In some embodiments, thermal interface material 442 is composed of a matrix material and a high volume fraction of electrically insulating but thermally conductive filler. For example, the matrix material may include epoxy, silicone, urethane acrylate, ceramic, metal, another suitable matrix material, or a combination thereof. In addition, adhesive tape may be used as a matrix material. For example, the filler may include aluminum oxide, boron nitride, zinc oxide, or a combination thereof. In some embodiments, the heat dissipating plate 444 includes a vapor chamber, a heat pipe, or a combination thereof. In some embodiments, carbon-based material film 446 includes single-walled Carbon Nanotubes (CNTs) (with a thermal conductivity of about 3500W/mK), multi-walled carbon nanotubes (with a thermal conductivity of about 3000W/mK), graphene (with a thermal conductivity of about 5300W/mK), or other suitable carbon-based material.
Fig. 2 is a cross-sectional view of an electronic device 600B including a semiconductor package assembly 500 according to some embodiments of the invention. For brevity, the components of the following embodiments are not repeated as are the same or similar components previously described with reference to fig. 1. The electronic device 600B may be designed to use silicon capacitors of different sizes to achieve a desired capacitance value. The electronic device 600B differs from the electronic device 600A in that the electronic device 600B includes one or more discrete silicon capacitor chips 430B stacked on the second surface 200A2 of the base 200A. In some embodiments, silicon capacitor chip 400B may have a dimension S2 that is smaller than a dimension S1 (fig. 1) of silicon capacitor chip 430A. Accordingly, the capacitance value of the silicon capacitor chip 400B may be adjusted by changing the size S2 of the silicon capacitor chip 400B so that it is different from the capacitance value of the silicon capacitor chip 430A.
Fig. 3 is a cross-sectional view of an electronic device 600C including a semiconductor package assembly 500 according to some embodiments of the invention. For brevity, the components of the following embodiments are not repeated as are the same or similar components previously described with reference to fig. 1-2. The electronic device 600C may be designed to use both silicon capacitors and multilayer ceramic capacitors (MLCCs) to achieve the goals of cost effectiveness and improved thermal performance. The electronic device 600C differs from the electronic device 600A in that the electronic device 600C further includes one or more multilayer ceramic capacitor (MLCC) components 470. The MLCC assembly 470 is mounted on the second surface 200A2 of the submount 200A and beside the silicon capacitor chip 430A. The MLCC assembly 470 is electrically connected to the submount 200A, the silicon capacitor chip 430A, and the semiconductor package assembly 500. In some embodiments, the silicon capacitor chip 430A has a height H1 and the MLCC assembly 470 has a height H2 that is lower than the height H1 of the silicon capacitor chip 430A (because the height of the silicon capacitor chip 430A can be adjusted by changing the height of the silicon substrate 432 shown in fig. 1). Thus, the thermal interface material 442 may be separate from the MLCC component 470. In other words, there is a gap between the MLCC component 470 and the heat dissipating structure 450. In some embodiments, the silicon capacitor chip 430A has a first capacitance value and the MLCC component 470 has a second capacitance value, which may be the same as or different from the first capacitance value of the silicon capacitor chip 430A depending on design requirements.
The embodiment of the invention provides a semiconductor packaging assembly and electronic equipment. The electronic device includes a semiconductor package assembly, at least one submount, at least one silicon capacitor chip, a heat dissipation structure, and a screen. In some embodiments, the electronic device comprises a portion of a mobile device that includes a mobile phone, a Personal Digital Assistant (PDA), and a digital camera. The semiconductor package assembly provides a system on a chip (SOC) package and a memory package stacked thereon and integrated into a three-dimensional (3D) package-on-package (PoP) semiconductor package assembly. The silicon capacitor chip and the semiconductor package assembly are disposed on opposite sides of the submount. In some embodiments, the electronic device uses one or more silicon capacitor chips in place of a multilayer ceramic capacitor (MLCC) component. The thermal conductivity of the silicon capacitor chip (about 150W/mK) is much higher than that of air (about 0.026W/mK) and MLCC components. Thus, the silicon capacitor chip may be used as a good heat spreader for a System On Chip (SOC) package. Furthermore, the silicon capacitor chip may be used as an in-situ heat sink for electronic devices. Furthermore, the silicon capacitor chip can be fabricated to a much higher desired height (up to about 700 μm) than the MLCC assembly. In mobile applications, silicon capacitor chips with higher heights can be easily connected to heat dissipation structures using Thermal Interface Materials (TIMs) without gaps (air gaps), thereby providing low power dissipation paths in addition to the original heat dissipation paths (e.g., conductive paths from SOC package to memory package), thermal resistance can also rapidly dissipate heat from the SOC package to the screen (or external environment). Therefore, the heat dissipation capacity of the semiconductor packaging component and the electronic equipment can be further improved. In some embodiments, the electronic device may be designed to achieve a desired capacitance value using silicon capacitors having various sizes. In some embodiments, the electronic device may be designed to use both silicon capacitors and multilayer ceramic capacitors (MLCCs) to achieve the goals of cost effectiveness and improved thermal performance.
While the invention has been described by way of example and in terms of preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. On the contrary, the invention is intended to cover various modifications and similar arrangements of the disclosed embodiments (as would be apparent to one of ordinary skill in the art). The scope of the appended claims is therefore to be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.

Claims (31)

1. A semiconductor package assembly, comprising:
a base having a first surface and a second surface opposite the first surface;
a system-on-chip package disposed on the first surface of the base, the system-on-chip package comprising:
a system-on-chip having a bond pad; and
a redistribution layer structure electrically connected to the system-on-chip through the bond pad;
the semiconductor package assembly further includes a memory package stacked on the system-on-chip package, the memory package comprising:
a memory package substrate having a top surface and a bottom surface; and
a memory chip mounted on the top surface of the memory package substrate and electrically connected to the memory package substrate; and
the semiconductor package assembly further includes a silicon capacitor chip disposed on and electrically connected to the second surface of the submount.
2. The semiconductor package assembly of claim 1, wherein the silicon capacitor chip comprises:
a dielectric material between a first electrode and a second electrode, wherein the first electrode is formed from a silicon substrate;
the first conductive structure and the second conductive structure are arranged on the front surface of the silicon substrate and are electrically connected with the first electrode and the second electrode.
3. The semiconductor package assembly of claim 2, wherein the back side of the silicon substrate forms a top side of the silicon capacitor chip away from the first and second conductive structures.
4. The semiconductor package assembly of claim 1, wherein the first conductive structure and the second conductive structure are surrounded by an underfill between the silicon capacitor chip and the submount.
5. The semiconductor package assembly of claim 3, wherein the underfill surrounds a portion of the silicon substrate.
6. The semiconductor package assembly of claim 1, further comprising: and an electronic component disposed on the second surface of the base and beside the silicon capacitor chip, wherein the electronic component is electrically connected to the base using a third conductive structure.
7. The semiconductor package assembly of claim 6, wherein the electronic component comprises a power management integrated circuit, a resistor, an inductor, a DRAM chip, or a combination thereof.
8. The semiconductor package assembly of claim 1, further comprising: a multilayer ceramic capacitor assembly mounted on the second surface of the submount and beside the silicon capacitor chip.
9. The semiconductor package assembly of claim 8, wherein the silicon capacitor chip has a first height and the multilayer ceramic capacitor assembly has a second height that is lower than the first height.
10. The semiconductor package according to claim 8, wherein the silicon capacitor chip has a first capacitance value and the multilayer ceramic capacitor component has a second capacitance value that is the same as the first capacitance value.
11. The semiconductor package according to claim 8, wherein the silicon capacitor chip has a first capacitance value and the multilayer ceramic capacitor component has a second capacitance value different from the first capacitance value.
12. The semiconductor package assembly of claim 1, wherein the system-on-chip package comprises:
a molding compound surrounding the system-on-chip, the molding compound in contact with the redistribution layer structure and the system-on-chip; and
a fourth conductive structure passing through the molding compound and electrically connected to the memory package; and
a fifth conductive structure disposed between the redistribution layer structure and the base.
13. The semiconductor package assembly of claim 12, wherein the memory package comprises:
and the sixth conductive structure is arranged on the bottom surface of the memory packaging substrate and is electrically connected with the system-on-chip package.
14. An electronic device, comprising:
a first base having a first surface and a second surface opposite the first surface;
a system-on-chip package stacked on the first surface of the first base, the system-on-chip package comprising:
a system-on-chip having a bond pad; and
a redistribution layer structure electrically connected to the system-on-chip through the bond pad;
the electronic device further includes a memory package stacked on the system-on-chip package, the memory package comprising:
a memory package substrate having a top surface and a bottom surface; and
a memory chip mounted on the top surface of the memory package substrate and electrically connected to the memory package substrate;
the electronic device further includes:
a silicon capacitor chip disposed on the second surface of the first base;
a heat dissipation structure connected to the silicon capacitor chip; and
and the screen is arranged on the heat dissipation structure.
15. The electronic device of claim 14, further comprising:
the second base is arranged on the first base and electrically connected with the first base, wherein the system-on-chip package and the memory package are arranged between the first base and the second base.
16. The electronic device of claim 14, wherein the heat dissipation structure comprises:
a thermal interface material in contact with the silicon capacitor chip;
a heat dissipation plate disposed on the thermal interface material such that the thermal interface material is connected between the silicon capacitor chip and the heat dissipation plate; and
and a carbon-based material film disposed on the heat dissipation plate.
17. The electronic device of claim 16, wherein the thermal interface material comprises an epoxy, a silicone, a polyurethane, an acrylate, a ceramic, a metal, or a combination thereof.
18. The electronic device of claim 16, wherein the heat spreader plate comprises a vapor chamber, a heat pipe, or a combination thereof.
19. The electronic device of claim 16, wherein the silicon capacitor chip comprises:
a dielectric material between the first electrode and the second electrode, wherein the first electrode is formed of a silicon substrate;
the first electrode connecting pad is arranged on the silicon substrate and is electrically connected with the silicon substrate;
the second electrode connecting pad is arranged on the silicon substrate and is electrically connected with the second electrode; and
the first conductive structure and the second conductive structure are arranged on the front surface of the silicon substrate and are electrically connected with the first electrode connecting pad and the second electrode connecting pad.
20. The electronic device of claim 19, wherein the back side of the silicon substrate forms a top side of the silicon capacitor chip away from the first and second conductive structures.
21. The electronic device of claim 20, wherein the thermal interface material is in contact with a top surface of the silicon capacitor chip.
22. The electronic device of claim 14, wherein the first conductive structure and the second conductive structure are surrounded by an underfill between the silicon capacitor chip and the first submount.
23. The electronic device of claim 19, wherein the underfill surrounds a portion of the silicon substrate.
24. The electronic device of claim 14, further comprising:
and an electronic component disposed on the second surface of the first base and beside the silicon capacitor chip, wherein the electronic component is electrically connected to the first base using a third conductive structure.
25. The electronic device of claim 24, wherein the electronic component comprises a power management integrated circuit, a resistor, an inductor, a DRAM chip, or a combination thereof.
26. The electronic device of claim 14, further comprising:
a multilayer ceramic capacitor assembly mounted on the second surface of the first submount and beside the silicon capacitor chip.
27. The electronic device of claim 26, wherein the silicon capacitor chip has a first height and the multilayer ceramic capacitor assembly has a second height that is lower than the first height.
28. The electronic device of claim 26, wherein the silicon capacitor chip has a first capacitance value and the multilayer ceramic capacitor assembly has a second capacitance value that is the same as the first capacitance value.
29. The electronic device of claim 26, wherein the silicon capacitor chip has a first capacitance value and the multilayer ceramic capacitor assembly has a second capacitance value different from the first capacitance value.
30. The electronic device of claim 14, wherein the system-on-chip package comprises:
a molding compound surrounding the system-on-chip, the molding compound in contact with the redistribution layer structure and the system-on-chip; and
a fourth conductive structure passing through the molding compound and electrically connected to the memory package; and
a fifth conductive structure disposed between the redistribution layer structure and the first base; and
wherein the memory package comprises:
and the sixth conductive structure is arranged on the bottom surface of the memory package substrate and is electrically connected with the system-on-chip package.
31. The electronic device of claim 14, further comprising:
and a back plate disposed on the system-on-chip package and the memory package opposite to the screen.
CN202310037177.8A 2022-01-21 2023-01-10 Semiconductor package assembly and electronic device Pending CN116487377A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US63/301,512 2022-01-21
US18/147,986 US20230238360A1 (en) 2022-01-21 2022-12-29 Semiconductor package assembly and electronic device
US18/147,986 2022-12-29

Publications (1)

Publication Number Publication Date
CN116487377A true CN116487377A (en) 2023-07-25

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN202310037177.8A Pending CN116487377A (en) 2022-01-21 2023-01-10 Semiconductor package assembly and electronic device

Country Status (1)

Country Link
CN (1) CN116487377A (en)

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