CN116483754A - RAM read-write control method, controller, RAM and electronic equipment - Google Patents
RAM read-write control method, controller, RAM and electronic equipment Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1673—Details of memory controller using buffers
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1689—Synchronisation and timing concerns
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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Abstract
The embodiment of the invention discloses a read-write control method of a RAM, a controller, the RAM and electronic equipment, wherein the RAM is provided with the controller, and the method is applied to the controller and comprises the following steps: if the controller of the RAM receives a first instruction for externally reading and writing the RAM, a two-way handshake mechanism is adopted to realize the external reading and writing of target data to the RAM, so that the design problem that Q-terminal data is required to be continuously maintained after the RAM is accessed in a dependent manner can be solved, and the control time sequence for reading and writing the RAM is simplified.
Description
Technical Field
The present invention relates to the field of data reading and writing technologies, and in particular, to a RAM reading and writing control method, a controller, a RAM, and an electronic device.
Background
RAM (Random Access Memory ) is an internal memory that can exchange data directly with a CPU (Central Processing Unit ) and is read and written at any time (except when refreshed) and is fast, typically as a temporary data storage medium for an operating system or other running program. RAM operates by writing (storing) or reading (retrieving) information from any given address at any time, the greatest difference from ROM (Read-Only Memory) being the volatility of the data, i.e. the stored data will be lost upon power-down.
In general, the peripheral logic design of the RAM determines the read-write timing of the RAM, which results in poor stability of the read-write timing of the RAM, and meanwhile, the peripheral logic of the RAM may also depend on whether the Q-terminal of the RAM is maintained, so that the Bug is very easy to occur when the RAM is read or written.
Disclosure of Invention
Aiming at the defects of the prior art, the invention provides a read-write control method of a RAM, a controller, the RAM and electronic equipment, and aims to solve the technical problems of complex read-write control logic and poor universality of the RAM in the prior art.
In order to solve the above problems, in a first aspect, an embodiment of the present invention provides a method for controlling read/write of a RAM, where the RAM is provided with a controller, and the method is applied to the controller, where the method includes:
and if the controller receives a first instruction for externally reading and writing the RAM, a two-way handshake mechanism is adopted to realize the external reading and writing of target data to the RAM.
Further, in the method for controlling reading and writing of the RAM, the implementing the external reading and writing of the target data to the RAM by adopting a bidirectional handshake mechanism includes:
the controller performs two-way handshake with the outside;
and the controller reads and writes target data from and to the RAM according to the address line and the data line of the RAM.
Further, in the method for controlling read/write of RAM, the controller performs a bidirectional handshake with the outside, including:
the controller sends a ready signal to the outside;
the controller receives an externally transmitted valid signal.
Further, in the method for controlling reading and writing of the RAM, the address lines of the RAM include write address lines, and the data lines include write data lines;
the controller reads and writes target data from and to the RAM according to the address line and the data line of the RAM, and the method comprises the following steps:
if the first instruction is a data writing instruction, the controller determines a writing address of the target data in the RAM according to the writing address line;
the controller writes the target data into the RAM according to the write data line.
Further, in the method for controlling reading and writing of the RAM, the address lines of the RAM include read address lines, and the data lines include read data lines;
the controller reads and writes target data from and to the RAM according to the address line and the data line of the RAM, and the method comprises the following steps:
if the first instruction is a read data instruction, the controller determines an address of read target data in the RAM according to the read address line;
the controller reads the target data in the RAM according to the read data line and sends the target data to the outside.
Further, in the method for controlling reading and writing of a RAM, the sending the target data to the outside includes:
the controller sends a second instruction to the outside and performs two-way handshake with the outside to realize that the target data is sent to the outside.
Further, in the read-write control method of the RAM, the controller includes an input unit, an output unit, and a plurality of data buffer units; the data buffer unit is arranged between the input unit and the output unit, and the input unit is connected with the RAM; the data buffer unit is used for buffering the target data so as to realize the completion of two-wire handshake between the controller and the outside or/and the internal unit of the controller;
wherein before the controller sends the second instruction to the outside, the method further comprises:
the input unit sends a third instruction to the data buffer unit and performs two-way handshake with the data buffer unit so as to realize the caching of the target data into the data buffer unit;
the data buffer unit sends a fourth instruction to the output unit and performs two-way handshake with the output unit to open a data channel between the data buffer unit and the output unit;
the output unit sends the second instruction to the outside and performs two-way handshake with the outside so as to send the target data to the outside.
Further, in the read-write control method of the RAM, the data buffer unit is configured with a state machine, and the state machine is used for representing the current state of the data buffer unit.
Further, in the method for controlling read/write of the RAM, the controller alternately buffers the two target data outputted from the RAM into the two data buffer units in the controller; or (b)
The controller polls and buffers the three target data outputted by the RAM into three data buffer units in the controller; or (b)
The controller polls and buffers N target data output by the RAM into N+1 data buffer units in the controller; wherein N is more than 3.
In a second aspect, an embodiment of the present invention further provides a controller, where the controller may implement a method for controlling reading and writing of a RAM according to any one of the first aspect.
In a third aspect, an embodiment of the present invention further provides a RAM, where the RAM is a dual-port RAM or a single-port RAM, and the RAM is provided with a controller, and after receiving a first instruction for externally reading and writing the RAM, the controller uses a two-way handshake mechanism to implement external reading and writing of target data to the RAM.
In a fourth aspect, an embodiment of the present invention further provides an electronic device, where the electronic device includes a RAM, where the RAM is a dual-port RAM or a single-port RAM, and a controller is disposed in the RAM, and after the controller receives a first instruction for externally reading and writing the RAM, a bidirectional handshake mechanism is used to implement external reading and writing of target data to the RAM.
The embodiment of the invention provides a read-write control method of a RAM, a controller, the RAM and electronic equipment. The method is characterized in that the RAM is provided with a controller, the read-write control method of the RAM is carried out in the controller, after the controller receives a first instruction for externally reading and writing the RAM, a two-way handshake mechanism is adopted to realize the external reading and writing of target data to the RAM, the design problem that Q-terminal data is required to be continuously kept after the RAM is accessed is solved, the read-write control time sequence of the RAM is simplified, and the complexity of the read-write control logic of the RAM is reduced.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic flow chart of a method for controlling reading and writing of a RAM according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a method for controlling read/write of a RAM according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a method for controlling read/write of a RAM according to an embodiment of the present invention;
fig. 4 is another flow chart of a read-write control method of RAM according to an embodiment of the present invention;
FIG. 5 is another flow chart of a method for controlling read/write of a RAM according to an embodiment of the present invention;
FIG. 6 is another flow chart of a method for controlling read/write of a RAM according to an embodiment of the present invention;
FIG. 7 is a timing chart of writing data in a read-write control method of a RAM according to an embodiment of the present invention;
FIG. 8 is another flow chart of a method for controlling read/write of a RAM according to an embodiment of the present invention;
FIG. 9 is a timing chart of read data of a read-write control method of a RAM according to an embodiment of the present invention;
fig. 10 is another flow chart of a read-write control method of RAM according to an embodiment of the present invention;
FIG. 11 is a frame diagram of read data in a read-write control method of a RAM according to an embodiment of the present invention;
FIG. 12 is another architecture diagram of a read-write control method for a RAM according to an embodiment of the present invention;
fig. 13 is a state diagram of a data buffer unit in a read-write control method of a RAM according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be understood that the terms "comprises" and "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It is also to be understood that the terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in this specification and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It should be further understood that the term "and/or" as used in the present specification and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes such combinations.
As analyzed in the background art of the present application, the control logic of reading and writing of the RAM in the prior art is complex and has poor generality, and in order to solve the above technical problems, as shown in fig. 1, 2 and 3, the present application provides a method for controlling reading and writing of the RAM.
Referring to fig. 1, fig. 1 is a flowchart illustrating a method for controlling reading and writing of a RAM according to an embodiment of the present invention.
As shown in fig. 1, the method includes step S110.
And S110, if the controller receives a first instruction for externally reading and writing the RAM, a two-way handshake mechanism is adopted to realize the external reading and writing of target data to the RAM.
Specifically, the two-way handshake mechanism, namely the VALID/READY handshake mechanism, is a mechanism capable of enabling both transmitting and receiving parties to have the capability of controlling the transmission rate, that is, after one party receives a VALID signal sent by the other party and the other party receives a READY signal sent by the one party, the two parties are marked to finish handshake, so that data transmission can be performed. The first is that the VALID signal arrives first and the READY signal arrives later; the second is that the VALID signal and READY signal arrive at the same time; the third is that the VALID signal arrives after the READY signal arrives first. The first instruction is an operation instruction which is sent to the controller from the outside and requests writing or reading of target data in the RAM.
The external device refers to a module or equipment for requesting to read and write the RAM, the RAM can be a dual-port RAM or a single-port RAM, and the external device can read and write data of the RAM through a controller.
Referring to fig. 2, fig. 2 is a schematic diagram of a method for controlling reading and writing of a RAM according to an embodiment of the invention. As shown in fig. 2, the RAM is provided with a controller, and is a single-port RAM, that is, the target data written into the RAM and the data read from the RAM are realized by providing a port on the controller. When the external needs to perform read-write operation on the RAM, the external sends a first instruction to the controller, and after the controller receives the first instruction, a two-way handshake mechanism can be adopted to realize the external read-write of target data on the RAM. When the external needs to write the target data into the RAM, the first instruction is transmitted to the controller in the form of an in_wr signal, and after the controller receives the in_wr signal, the controller can write the target data into the RAM by adopting a two-way handshake mechanism; when the external needs to read the target data from the RAM, the first instruction is transmitted to the controller in the form of an in_rd_ctrl signal and an in_wr signal, and after the controller receives the in-rd-ctrl signal and the in_wr signal, the controller can adopt a two-way handshake mechanism to realize the external reading of the target data in the RAM. Wherein in_rd_ctrl represents an external transmission carried command to the controller, which is transmitted along with the read data, for example, it may be a signal such as last, line_end, frame_end, etc., and an in_wr signal of 1 represents that the transmission is writing, and a signal of 0 represents that the transmission is reading.
Referring to fig. 3, fig. 3 is a schematic diagram of a method for controlling reading and writing of a RAM according to an embodiment of the present invention. As shown in fig. 3, the RAM is provided with a controller, and is a dual-port RAM, that is, the target data written into the RAM and the data read from the RAM can be realized through two ports provided on the controller. As can be seen from fig. 3, the signals in_rd_valid, in_rd_data, in_rd_addr, in_rd_ctrl, and in_rd_ready can be transmitted through a port provided on the controller; the signals in_wr_valid, in_wr_data, in_wr_addr, and in_wr_ready may be transmitted through another port provided on the controller.
In some embodiments, as shown in fig. 4, step S110 includes steps S111 and S112.
S111, the controller performs two-way handshake with the outside;
and S112, the controller reads and writes target data of the RAM externally according to the address line and the data line of the RAM.
In this embodiment, the controller performs a bidirectional handshake with the outside, that is, the controller sends a handshake signal to the outside, and the outside sends a handshake signal to the controller, so that the bidirectional handshake between the controller and the outside can be completed. After the controller completes the two-way handshake with the outside, the controller can send an enabling signal to the RAM, and the RAM can be read and written with target data through the address line and the data line of the RAM.
In some embodiments, as shown in fig. 5, step S111 includes steps S1111 and S1112.
S1111, the controller sends a ready signal to the outside;
s1112, the controller receives the externally transmitted valid signal.
In this embodiment, as shown in fig. 2, the ready signal, i.e., in_ready signal, sent by the controller to the outside indicates that the controller has ready to receive, and the valid signal, i.e., in_valid signal, sent by the outside to the controller indicates that data, address, or control information has been placed on the write bus and held by the outside. When the controller sends a ready signal to the outside and the controller receives an externally sent valid signal, it marks that the controller completes the two-way handshake with the outside.
In some embodiments, as shown in fig. 6, step S112 includes steps S1121 and S1122.
S1121, if the first instruction is a data writing instruction, the controller determines a writing address of the target data in the RAM according to the writing address line;
and S1122, the controller writes the target data into the RAM according to the write data line.
In this embodiment, the address lines of the RAM include write address lines, the data lines include write data lines, and the first instruction includes an in_wr signal, where an in_wr signal of 1 indicates that the transfer is write, and an in_wr signal of 0 indicates that the transfer is read. When the first instruction is determined to be a write data instruction. Specifically, the controller sends an enabling signal to the RAM, then the controller determines the write address of the target data according to the write address line of the RAM, and finally the controller writes the target data into the RAM according to the write data line of the RAM.
The sequential logic of external requests for writing target data to RAM may refer to fig. 7. In the embodiment shown in fig. 7, the clk signal is a clock signal, the in_valid signal is an active signal sent externally to the controller, the in_ready signal is a ready signal sent externally by the controller, the in_wr signal is in a high state to indicate that the transmission is writing, the in_data is in a low state to indicate that the transmission is reading, the in_addr is writing target data, the in_addr is a target address of the reading or writing, RAM [0], RAM [1] and RAM [2] are areas where the target data is written into the RAM, and one low pulse and one high pulse of the clock form a clock pulse signal.
In some embodiments, as shown in fig. 8, step S112 further includes steps S1124 and S1125.
S1124, if the first instruction is a read data instruction, the controller determines an address of the read target data in the RAM according to the read address line;
s1125, the controller reads the target data in the RAM according to the read data line and sends the target data to the outside.
In this embodiment, the address lines of the RAM include read address lines, the data lines include read data lines, and the first instruction includes an in_rd_ctrl signal and an in_wr signal. When the in_wr signal is in a low level state, the transmission is indicated as reading target data from the RAM, at this time, the controller sends an enabling signal to the RAM, determines an address of the reading target data according to a read address line of the RAM, and finally reads the target data from the RAM according to the read data line of the RAM and sends the target data to the outside.
The sequential logic of external requests for target data reads to RAM may refer to fig. 9. As shown in fig. 9, the out_ram_en signal is an enable signal sent by the controller to the RAM, the out_ram_wr signal is a read data signal sent by the controller to the RAM, the out_ram_rd_data is target data read from the RAM, and the out_rd_ctrl signal is a command carried by the controller to the outside.
In some embodiments, as shown in fig. 2, step S1126 further includes the steps of: the controller sends a second instruction to the outside and performs two-way handshake with the outside to realize that the target data is sent to the outside.
Specifically, after target data read from the RAM from the outside is transmitted to the controller for buffering, the controller also needs to perform a two-way handshake with the outside, and after the controller completes the two-way handshake with the outside again, the target data transmitted to the buffer in the RAM from the controller can be transmitted to the outside from the controller.
In this embodiment, the second instruction is transmitted to the outside in the form of out_rd_ctrl, and when the controller performs the bidirectional handshake with the outside again, the controller sends an effective signal out_valid to the outside, and the outside sends a ready signal out_ready to the controller, so that the bidirectional handshake between the controller and the outside can be completed, and the target data can be transmitted from the controller to the outside in the form of out_data.
It should be noted that, when the RAM is a single-port RAM, the present application may continuously read a plurality of target data from the RAM, that is, after the first target data is cached in the controller, an instruction for reading the second target data from the RAM is externally sent, and in a stage where the second target data is cached in the controller, the first target data may be sent to the outside by the controller; when the RAM is a dual-port RAM, the method can simultaneously and continuously read a plurality of target data from the RAM at one port of the RAM, and continuously write a plurality of target data from the RAM at the other port of the RAM. It should be noted that, the specific process of reading and writing the dual-port RAM may refer to other embodiments in the present application, which are not specifically described herein.
In some embodiments, as shown in fig. 10, 11 and 12, the controller includes an input unit, an output unit and a plurality of data buffer units; the data buffer unit is arranged between the input unit and the output unit, and the input unit is connected with the RAM; the data buffer unit is used for buffering the target data so as to achieve two-wire handshake between the controller and the outside or/and the internal unit of the controller.
Wherein, before the controller sends the second instruction to the outside, steps S210, S220, and S230 are further included.
S210, the input unit sends a third instruction to the data buffer unit and performs two-way handshake with the data buffer unit so as to realize the caching of the target data in the data buffer unit;
s220, the data buffer unit sends a fourth instruction to the output unit and performs two-way handshake with the output unit so as to open a data channel between the data buffer unit and the output unit;
and S230, the output unit sends the second instruction to the outside and performs two-way handshake with the outside so as to send the target data to the outside.
Specifically, when the external needs to write target data into the RAM, the target data is written into the RAM through the input unit; when the external needs to read the target data from the RAM, the target data is buffered into the data buffer unit through the input unit and then transmitted to the external through the output unit.
In this embodiment, when the external needs to read a plurality of target data in the RAM, the controller may use a bidirectional handshake mechanism to implement external reading of the target data from the RAM, so as to simplify the control timing for reading and writing of the RAM. Because the controller can adopt a two-way handshake mechanism to cause certain delay, and thus the target data can not be read continuously from the RAM easily, the embodiment can smoothly complete two-way handshake between the controller and the outside or/and between the internal units of the controller after the target is cached in the data buffer unit by adding a plurality of data buffer units into the controller, thereby ensuring the continuity of reading the data from the RAM.
Further, in some embodiments, the controller provided herein may alternately buffer two target data output by the RAM into two of the data buffer units in the controller, or the controller may poll and buffer three target data output by the RAM into three of the data buffer units in the controller, or N (N > 3) target data polls output by the controller into n+1 of the data buffer units in the controller.
In this embodiment, the number of data buffer units in the controller is related to the behavior of several beats of data in the RAM, that is, the behavior of several beats of data in the RAM determines the number of data buffer units in the controller, that is, when the RAM reads data as the next beat of data, two data buffer units in the controller are needed to buffer data alternately; when the RAM reads data, the data is shot out from the bottom, three data buffer units in the controller are needed to poll the cache data; when the RAM read data is N (N > 3) beats of data, then n+1 data buffer units are required to poll the buffered data.
It is understood that the controller mentioned in this application is not limited to the control of the read/write of the RAM, but can be applied to the control of the read/write of other types of memories. The number of the data buffer units in the controller can also be, but not limited to, determined by the behavior of the other types of memories for several beats of data when the controller controls the other types of memories to read data, and the number of the data buffer units in the controller can be specifically selected according to practical applications, and the application is not specifically limited.
In a specific embodiment, two data buffer units, such as buff0 and buff1 in fig. 11 and 12, respectively, may be provided in the controller, and two target data may be continuously read from the RAM from the outside. As can be seen from fig. 11 and 12, the two target data read in the RAM can be buffered into the buff0 and the buff1, respectively, and then sequentially and alternately transferred to the outside from the buff0 and the buff1, respectively. The third instruction is transmitted to the data buffer unit in the form of an in_ctrl signal as shown in fig. 12, the fourth instruction is transmitted to the output module in the form of an out_ctrl_0 signal or an out_ctrl_1 signal as shown in fig. 12, and the data buffer unit is configured with a state machine, and the state machine is used for representing the current state of the data buffer unit.
In the embodiment shown in fig. 9 and 12, the in_flag signal is an input lag time signal, the out_flag signal is an output lag time signal, the in_flag signal and the out_flag signal are both usable to represent the read state of the target signal, and the buff0 and the buff1 are each configured with the state machine shown in fig. 13, which includes three states of IDLE, FETCH, and VALID, the buff0_fsm is the state machine of buff0, and the buff1_fsm is the state machine of buff 1. IDLE indicates that the buff0/buff1 is in an IDLE state and can wait for being used, when the input unit is ping-pong trained to the buff0/buff1, a corresponding data buffer unit is enabled, the state of the data buffer unit can jump to a FETCH state, at the moment, the data read by the corresponding RAM can be written into the corresponding data buffer unit, and the state of the data buffer unit jumps to a VALID state; when the data in the data buffer unit is read, the VALID state will poll the other data buffer unit, the state of the data buffer unit after data reading will jump directly to the FETCH state, and if the data buffer unit has no command to read in, the state will jump directly to the IDLE state.
Further, in the specific embodiment shown in fig. 9, three pieces of target data can be read continuously from the RAM by the outside. Specifically, the three pieces of target data are target data 1000, target data 1001, and target data 1002, respectively. When buff0_fsm jumps from the FETCH state to the VALID state, the target data 1000 is cached in buff 0; when buff0_fsm jumps from the VALID state to the FETCH state, the target data 1000 is taken from the buff0 while the target data 1001 is cached in the buff1, and at this time, the buff1_fsm jumps from the FETCH state to the VALID state; when the buff1_fsm jumps from the VALID state to the IDLE state, the target data 1001 is taken away from the buff1, and at this time, the buff0_fsm jumps from the FETCH state to the VALID state, and the target data 1002 is cached in the buff 0; when buff0_fsm jumps from the VALID state to the IDLE state, the target data 1002 is taken from buff0, thereby marking that three target data are read from RAM.
The method for controlling the read-write of the RAM is carried out in the controller, and after the controller receives the first instruction for externally reading and writing the RAM, the method adopts a two-way handshake mechanism to realize the external read-write of target data to the RAM, thereby solving the design problem that the Q-terminal data is required to be continuously maintained after the RAM is accessed in a dependent manner, simplifying the control time sequence for the read-write of the RAM and reducing the complexity of control logic for the read-write of the RAM.
In some embodiments, the invention further provides a RAM, where the RAM is a dual-port RAM or a single-port RAM, and the RAM is provided with a controller, and after receiving a first instruction for externally reading and writing the RAM, the controller uses a two-way handshake mechanism to implement external reading and writing of target data to the RAM.
In some embodiments, the invention further provides an electronic device, which comprises a RAM, wherein the RAM is a dual-port RAM or a single-port RAM, a controller is arranged in the RAM, and after receiving a first instruction for externally reading and writing the RAM, the controller adopts a two-way handshake mechanism to realize external reading and writing of target data to the RAM.
It will be clear to those skilled in the art that, for convenience and brevity of description, specific working procedures of the apparatus and units described above may refer to corresponding procedures in the foregoing method embodiments, which are not described herein again. Those of ordinary skill in the art will appreciate that the elements and algorithm steps described in connection with the embodiments disclosed herein may be embodied in electronic hardware, in computer software, or in a combination of the two, and that the elements and steps of the examples have been generally described in terms of function in the foregoing description to clearly illustrate the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
In the several embodiments provided by the present invention, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative, and for example, the division of the units is merely a logical function division, there may be another division manner in actual implementation, or units having the same function may be integrated into one unit, for example, multiple units or components may be combined or may be integrated into another system, or some features may be omitted, or not performed. In addition, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices, or elements, or may be an electrical, mechanical, or other form of connection.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the embodiment of the present invention.
In addition, each functional unit in the embodiments of the present invention may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.
While the invention has been described with reference to certain preferred embodiments, it will be understood by those skilled in the art that various changes and substitutions of equivalents may be made and equivalents will be apparent to those skilled in the art without departing from the scope of the invention. Therefore, the protection scope of the invention is subject to the protection scope of the claims.
Claims (10)
1. A method for controlling read-write of a RAM, wherein the RAM is provided with a controller, and the method is applied to the controller, the method comprising:
and if the controller receives a first instruction for externally reading and writing the RAM, a two-way handshake mechanism is adopted to realize the external reading and writing of target data to the RAM.
2. The method for controlling reading and writing of a RAM according to claim 1, wherein said implementing external reading and writing of target data to the RAM by using a two-way handshake mechanism includes:
the controller performs two-way handshake with the outside;
and the controller reads and writes target data from and to the RAM according to the address line and the data line of the RAM.
3. The method of controlling reading and writing of a RAM according to claim 2, wherein the address lines of the RAM include write address lines, and the data lines include write data lines;
the controller reads and writes target data from and to the RAM according to the address line and the data line of the RAM, and the method comprises the following steps:
if the first instruction is a data writing instruction, the controller determines a writing address of the target data in the RAM according to the writing address line;
the controller writes the target data into the RAM according to the write data line.
4. The method of claim 2, wherein the RAM address lines comprise read address lines and the data lines comprise read data lines;
the controller reads and writes target data from and to the RAM according to the address line and the data line of the RAM, and the method comprises the following steps:
if the first instruction is a read data instruction, the controller determines an address of read target data in the RAM according to the read address line;
the controller reads the target data in the RAM according to the read data line, sends a second instruction to the outside, and performs two-way handshake with the outside so as to realize the sending of the target data to the outside.
5. The method for controlling reading and writing of a RAM according to claim 4, wherein the controller includes an input unit, an output unit, and a plurality of data buffer units; the data buffer unit is arranged between the input unit and the output unit, and the input unit is connected with the RAM; the data buffer unit is used for buffering the target data so as to realize the two-way handshake between the controller and the outside or/and the internal unit of the controller;
wherein before the controller sends the second instruction to the outside, the method further comprises:
the input unit sends a third instruction to the data buffer unit and performs two-way handshake with the data buffer unit so as to realize the caching of the target data into the data buffer unit;
the data buffer unit sends a fourth instruction to the output unit and performs two-way handshake with the output unit to open a data channel between the data buffer unit and the output unit;
the output unit sends the second instruction to the outside and performs two-way handshake with the outside so as to send the target data to the outside.
6. The method according to claim 5, wherein the data buffer unit is configured with a state machine for characterizing a current state of the data buffer unit.
7. The method for controlling reading and writing of a RAM according to claim 5, wherein the method further comprises:
the controller alternately buffers the two target data output by the RAM into two data buffer units in the controller; or (b)
The controller polls and buffers the three target data outputted by the RAM into three data buffer units in the controller; or (b)
The controller polls and buffers N target data output by the RAM into N+1 data buffer units in the controller; wherein N is more than 3.
8. A controller, wherein the controller can implement the read-write control method of the RAM as claimed in any one of claims 1 to 7.
9. The RAM is characterized by being a dual-port RAM or a single-port RAM, wherein the RAM is provided with a controller, and the controller adopts a two-way handshake mechanism to realize external reading and writing of target data on the RAM after receiving a first instruction for external reading and writing on the RAM.
10. The electronic equipment is characterized by comprising a RAM, wherein the RAM is a dual-port RAM or a single-port RAM, a controller is arranged in the RAM, and after receiving a first instruction for externally reading and writing the RAM, the controller adopts a two-way handshake mechanism to realize the external reading and writing of target data to the RAM.
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