KR100761374B1 - Method and Apparatus for controlling flash memory - Google Patents

Abstract

The present invention relates to a flash memory control method and apparatus capable of supporting multi-plane operation, comprising: a host interface unit for transmitting and receiving control signals and data with a host, and generating and flashing a control signal for controlling a flash memory. And a buffer including a flash memory interface for transmitting and receiving a memory, a control signal, and data, and at least two buffers for storing data received through the host interface, wherein the buffer is controlled by the control signal of the host interface. And storing the data received from the host interface unit in any one of the at least two buffers and simultaneously transmitting the data stored in the other one of the at least two buffers to the flash memory interface unit. It provides a re-control device.

Flash memory controller, multiplane

Description

Method and device for controlling flash memory {Method and Apparatus for controlling flash memory}

1 is a diagram illustrating a configuration of a flash memory having a multi-plane structure by way of example;

2 is a block diagram showing the configuration of a flash memory controller according to an embodiment of the present invention;

3 is a timing diagram illustrating a case in which data is written from a flash memory using a flash memory control apparatus according to an exemplary embodiment of the present invention;

4 is a block diagram showing a configuration of a flash memory control apparatus according to another embodiment of the present invention.

<Explanation of symbols for main parts of the drawings>

201... Host interface unit,

203... Buffer,

205... First buffer,

207... Second buffer,

209... Flash memory interface,

210... Flash memory controller,

220... Host,

230... Flash memory.

The present invention relates to a flash memory control method and apparatus, and more particularly, to a flash memory control method and apparatus capable of supporting multi-plane operation.

Flash memory is a nonvolatile memory whose contents are not erased even when power is not applied, and is widely used in various devices due to high stability, large capacity, and relatively low cost. In addition, as mobile devices and various applications such as mobile phones and PDAs are widely used, there is a demand for a flash memory and a control device for controlling the same.

On the other hand, in the conventional flash memory, all physical blocks are arranged in a single plane. In such a single plane flash memory, instructions can be executed for only one physical block at a time for electrical erasure and only one physical page at a time for writing and reading.

In order to make up for the shortcomings of flash memory having a single plane structure, a flash memory having a multi plane structure has recently been proposed. A flash memory having a multi-plane structure has an advantage of distributing physical blocks in a plurality of planes and simultaneously performing operations such as erasing, writing, or reading on physical blocks or physical pages located in different planes.

1 is a diagram exemplarily illustrating a configuration of a flash memory having such a multi-plane structure.

The flash memory of FIG. 1 has four planes, each plane has 4,096 physical blocks, and each physical block is composed of 32 pages. Each plane contains a separate page register, which stores the plane-specific data received from the flash memory interface unit in each page register, and at the same time, when data reception for each plane is finished, the corresponding page or block from each plane register You can also simultaneously perform operations such as recording data.

However, in order to properly support the flash memory of the multi-plane structure, the size of the internal buffer of the flash memory controller must be increased, which increases the size of the memory and increases the complexity of the design. In most cases, the flash memory control device does not properly support a multi-plane structure or merely provides a software control method to burden the device.

An object of the present invention is to provide a flash memory control method and apparatus capable of supporting a multi-plane operation with a simple and inexpensive configuration.

In order to achieve the above objects, the present invention provides a device for controlling a flash memory having a plurality of planes, the control signal for controlling the host interface unit flash memory for transmitting and receiving control signals and data with the host and flash memory And a buffer unit including a flash memory interface unit for transmitting and receiving a control signal and data and at least two buffers for storing data received through the host interface unit, wherein the buffer unit is configured to control the host interface by a control signal of the host interface unit. The flash memory system may further include storing data received in one of the at least two buffers and simultaneously transmitting data stored in the other of the at least two buffers to the flash memory interface unit. It provides an apparatus.

Here, the control signal received by the host interface unit from the host information on the number of multi-plane (multi plane), information on the type of multi-plane operation (multi plane operation) and the address of the flash memory to perform the multi-plane operation May contain information.

The flash memory interface unit may sequentially receive data from any one of at least two buffers of the buffer unit by the control signal from the host interface and transmit the data to the flash memory as many times as the number of the multiplanes. Can be done.

In addition, each of the at least two buffers of the buffer unit transmits a full signal (Full) when it has data and an empty signal (Empty) when it does not have data to the host interface unit and the flash memory interface unit. Can be configured.

In a preferred embodiment, at least two buffers included in the buffer unit may be a single port memory, and the flash memory may be a NAND type flash memory.

According to another aspect of the present invention, in the apparatus for controlling a flash memory having a plurality of planes, generating a control signal for controlling the flash memory and the host interface unit for transmitting and receiving a control signal and data with the host and the flash memory and data A flash memory interface unit for transmitting and receiving and a buffer unit for storing data received through the host interface unit, wherein the buffer unit stores the data received from the host interface unit by the control signal of the host interface unit and at the same time stored in advance It provides a flash memory control device characterized in that the transmission to the flash memory interface unit.

Here, the control signal received by the host interface unit from the host information on the number of multi-plane (multi plane), information on the type of multi-plane operation (multi plane operation) and the address of the flash memory to perform the multi-plane operation May contain information.

The buffer unit may be a dual port memory, and the flash memory may be a NAND type flash memory.

According to another aspect of the present invention, a method of controlling a flash memory having a plurality of planes in a flash memory control device including at least two buffers, the method comprising: receiving a control signal and data from a host and receiving the received data; Storing the data received from the host in another one of the at least two buffers while transmitting data stored in any one of the at least two buffers to a flash memory until one of the two buffers is full; A method of controlling a flash memory, the method comprising repeating a number of times corresponding to the number of multi-planes included in a control signal received from the host.

According to another aspect of the present invention, a method of controlling a flash memory having a plurality of planes in a flash memory control device including a buffer, the method comprising: receiving a control signal and data from a host and sequentially receiving the received data into the buffer A method of controlling a flash memory, the method comprising: repeating a process of sequentially storing the data and simultaneously transmitting the stored data to the flash memory, the number of times corresponding to the number of multi-planes included in the control signal received from the host.

Next, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram illustrating a configuration of a flash memory control apparatus according to an exemplary embodiment of the present invention.

Referring to FIG. 2, the flash memory controller 210 includes a host interface 201, a buffer 203, and a flash memory interface 205, and is connected to the host 220 and the flash memory 230. To transmit and receive control signals and data.

The host interface 201 is connected to the host 220 to transmit and receive control signals and data from the host 220, and transmit and store data to the buffer unit 203 as described below.

The control signal received from the host 220 may include the following information. That is, multiplane, which is information on the type of multi-plane operation (for example, write / read / erase, etc.) to be performed on the flash memory, and information about the number of planes to perform multi-plane operation on the flash memory. It may include at least the number information and the address information of the flash memory to perform the multi-plane operation.

The flash memory interface unit 209 generates a control signal for controlling the flash memory and receives data from the buffer unit 203 as described later by the control signal from the host interface unit 201 and the flash memory. Send and receive data and control signals.

The two interface units may operate independently of each other. That is, the flash memory interface unit 209 may operate while the host interface unit 201 operates, and in some cases, the flash memory interface unit 205 may not operate.

The buffer unit 203 includes at least two physically separated buffers, and stores data received from the host 220 through the host interface unit 201 and transmits the data to the flash memory interface unit 209. Perform the function. In FIG. 2, two buffers, that is, a first buffer 205 and a second buffer 207 are shown. The first buffer 205 and the second buffer 207 are input through one port. Use a single port of memory for output.

The flash memory controller 210 of such a configuration operates as follows.

First, the host interface unit 201 receives control signals and data from the host 220. Herein, as described above, the control signal includes information on the type (eg, write / read / erase) of a multi-plane operation to be performed on the flash memory, and perform the multi-plane operation on the flash memory. And at least information on the number of planes, which is information on the number of planes, and address information of a flash memory to perform a multi-plane operation.

The host interface 201 stores the received data in, for example, the first buffer 205 of the buffer unit 203, and stores information on the type of the multi-plane operation, the number of the multi-planes, and the address information of the flash memory. 209).

In this case, when the number of multi-planes is two or more, the host interface unit 201 first writes data input from the host 220 to the first buffer 205, and if the first buffer 205 is full, 2 are sequentially written to the buffer 207. Similarly, when the second buffer 207 is full, the process of writing back to the first buffer 205 is repeated. As will be described later, the first buffer 205 and the second buffer 207 sequentially transfer data to the flash memory interface unit 209 so that any one buffer receives data from the host interface unit 201. In the meantime, another buffer transfers data to the flash memory interface 209 so that the data does not have to overlap.

The flash memory interface unit 209 receives data while receiving data from the first buffer 205 and the second buffer 207 for a number of times corresponding to the number of multiplanes included in the control signal received from the host interface unit 201. The process of transferring the data and the corresponding address to the flash memory is repeated. As described above, since the data is stored in the first buffer 205, the flash memory interface unit 209 reads data from the first buffer 205 until the first buffer 205 is empty, and then the first buffer ( When 205 is empty, the process of reading data from the second buffer 207 is repeated.

The flash memory interface unit 209 receives data for a number corresponding to the number of multiplanes and transmits the data to the flash memory, and the flash memory simultaneously performs a task corresponding to the type of multiplane operation included in the control signal. .

Meanwhile, the first buffer 205 and the second buffer 207 of the buffer unit 203 provide a signal indicating whether they have data, for example, a full or empty signal, to the host interface unit 201. ) And the flash memory interface unit 209.

In this case, when the host interface unit 201 receives a full signal from the first buffer 205 of the buffer unit 403, the host interface unit 201 starts to transmit data to the second buffer 207, and similarly, the second signal is transmitted to the second buffer 207. When the data in the buffer 207 is full, the second buffer 207 transmits a full signal to the host interface 201 to transmit the data to the next buffer (first buffer).

Meanwhile, the flash memory interface unit 209 receives data from the first buffer 205 while data is written to the second buffer 207 and the first buffer 205 is empty when the data transfer is completed. The signal is transmitted to the flash memory interface unit 209 to read data from the next buffer (second buffer).

By repeating this process for as many times as the number of multiplanes, it is possible to effectively support multi-operation for the flash memory without losing time in the buffer.

3 is a timing diagram illustrating a case in which data is written from a flash memory using a flash memory control apparatus according to an exemplary embodiment of the present invention.

3 illustrates a case of writing data in a flash memory having two planes, wherein an NFL_REB signal is a signal indicating read enable, and an NFL_IO [7: 0] signal is a signal indicating an input / output port.

As shown in FIG. 3, data is first transmitted to a first plane by an NFL_IO [7: 0] signal, and a corresponding operation is performed. The type of this operation is received from the host 220 through the host interface unit 201 as described above. If this operation is, for example, a write command, the data is written to the plane register of the first plane.

Next, after some delay time 310, data is transmitted to the second plane and the corresponding operation is performed. In the case of the write command, the data is written to the plane register of the second plane, and when the operation is completed, the first plane is completed. And simultaneously perform multiplane operations at time 320 for each address of the second plane.

4 is a block diagram showing a configuration of a flash memory control apparatus according to another embodiment of the present invention.

4 is basically the same as the configuration described with reference to FIG. 2, but differs only in the configuration of the buffer unit 403. That is, the buffer unit 403 of FIG. 4 is characterized by using a single physical buffer rather than a plurality of buffers as shown in FIG.

However, since a single physical buffer is used, it is preferable that the buffer unit 403 uses a dual port memory capable of first in first out (FIFO) by separating input / output ports to fully support a multi-plane operation. That is, a memory capable of transmitting data to the flash memory interface unit 209 through the output port while simultaneously receiving data from the host interface unit 201 through the input port is used.

In the above, the present invention has been described with reference to preferred embodiments, but the present invention is not limited to the above embodiments, and various forms of modification and modification can be made with reference to the appended claims and drawings.

For example, the above embodiment may be mainly used for a NAND flash memory, but may be applied to other flash memories other than the NAND flash memory if the multi-plane operation is supported.

According to the present invention, it is possible to provide a flash memory control method and apparatus capable of supporting a multi-plane operation with a simple and inexpensive configuration.

Claims (12)

An apparatus for controlling a flash memory having a plurality of planes, A host interface unit for transmitting and receiving a control signal and data with a host, wherein the control signal includes information on the number of multiplanes; A flash memory interface unit generating a control signal for controlling the flash memory and transmitting and receiving a control signal and data with the flash memory; And A buffer unit including at least two buffers for storing data received through the host interface unit Including but not limited to: The buffer unit stores data received from the host interface unit in one of the at least two buffers according to a control signal of the host interface unit and simultaneously stores data stored in another one of the at least two buffers. Transfer to wealth, The flash memory interface unit may receive a data from any one of at least two buffers of the buffer unit by a control signal from the host interface unit and transmit the data to a flash memory in a control signal from the host interface unit. Sequentially performing the number of times corresponding to Flash memory control device characterized in that. The method of claim 1, The control signal received by the host interface unit from the host includes information on the type of multi-plane operation and address information of the flash memory to perform the multi-plane operation. Flash memory control device further comprises. delete The method of claim 1, Each of the at least two buffers of the buffer unit transmits a full signal (Full) when it has data and an empty signal (Empty) when it does not have data to the host interface unit and the flash memory interface unit. Flash memory control device characterized in that. The method of claim 1, At least two buffers included in the buffer unit are single port memory. Flash memory control device characterized in that. The method of claim 1, Said flash memory being a NAND type flash memory Flash memory control device characterized in that. An apparatus for controlling a flash memory having a plurality of planes, A host interface for transmitting and receiving control signals and data with a host, wherein the control signal includes information on the number of multiplanes; A flash memory interface unit generating a control signal for controlling the flash memory and transmitting and receiving data with the flash memory; And A buffer unit for storing data received through the host interface unit Including but not limited to: The buffer unit stores data received from the host interface unit by a control signal of the host interface unit and simultaneously transmits data stored in advance to the flash memory interface unit. The flash memory interface unit sequentially transmits the data transmitted from the buffer unit to the flash memory by the control signal from the host interface unit as many times as the number of multiplanes included in the control signal from the host interface. To do with Flash memory control device characterized in that. The method of claim 7, wherein The control signal received by the host interface unit from the host includes information on the type of multi-plane operation and address information of the flash memory to perform the multi-plane operation. Flash memory control device comprising a. The method of claim 7, wherein The buffer unit being a dual port memory Flash memory control device characterized in that. The method of claim 7, wherein Said flash memory being a NAND type flash memory Flash memory control device characterized in that. A method of controlling a flash memory having a plurality of planes in a flash memory control device including at least two buffers, the method comprising: Receive control signals and data from a host and store the received data until either one of the at least two buffers is full, and transmit data stored in any one of the at least two buffers to a flash memory simultaneously Repeating the process of storing data received from the host in one of four buffers corresponding to the number of multiplanes included in the control signal received from the host Flash memory control method characterized in that. In the flash memory control device including a buffer for controlling a flash memory having a plurality of planes, Receiving a control signal and data from the host and sequentially storing the received data in the buffer, and simultaneously transmitting the stored data to the flash memory corresponding to the number of multi-planes included in the control signal received from the host Repeating a number of times Flash memory control method characterized in that.

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