KR20050101838A - Compact flash card - Google Patents

Abstract

The present invention relates to a compact flash card controller. More particularly, the present invention relates to a compact flash card controller, and more particularly, to embed a sector buffer composed of eight sectors to perform a single read / write command and a multi read / write command, thereby providing a high data transfer rate. Discuss the technique.

The present invention provides a host interface that attempts to communicate with a host, a flash memory array having a plurality of cells for storing data, and a plurality of sectors to perform at least one of a multi-read or a multi-write operation. And a compact flash card controller configured to continuously store or output the data one by one of the plurality of sectors according to the command signal received from the host interface.

Description

Compact flash card {Compact flash card}

The present invention relates to a compact flash card controller. More particularly, the present invention relates to a compact flash card controller, and more particularly, to embed a sector buffer composed of eight sectors to perform a single read / write command and a multi read / write command, thereby providing a high data transfer rate. Technology.

Recently, interest in flash memory (flash EEPROM) has been increasing to replace magnetic disks such as hard disks and floppy disks. Flash memory is a nonvolatile, low power consumption type semiconductor memory that is electrically programmed, and is widely used in portable devices due to its small size, light weight, and resistance to vibration.

The flash memory card is implemented by mounting at least one flash memory (IC chip) on one card.

Among these flash memory cards, the compact flash card (hereinafter referred to as a CF card) has many advantages such as small volume and light weight, and high data retention, reliability, and power saving. Computer peripheral areas (copiers, printers, scanners, projectors, external memory card devices, card readers, etc.), information consumer (IA) areas (high definition digital television / HDTV, visual information changer STB, digital media player / Media Player, etc.), and It is widely used in the field of portable digital products (portable information terminal / PDA, digital camera / digital camera, digital worker / MP3 player, etc.).

1 is a diagram illustrating a connection between a conventional host 1 and a CF card 2.

The host 1 is a communication device such as a computer. The CF card 2 has a built-in flash memory that can temporarily store and delete data, and can transmit and receive data to and from the host 1.

2 is a detailed configuration diagram of the CF card 2 of FIG.

The conventional CF card 2 has a host interface 10, a CF card controller 20, and a flash memory array 30.

The host interface 10 is for transmitting and receiving between the host 1 and the CF card 2, and receives an address, a command signal, a control signal and data from the host 1 and transmits it to the CF card controller 20, Control signals, data and the like are received from the CF card controller 20 and transmitted to the host 1.

The CF card controller 20 includes an internal memory 21, a central processing unit (CPU) 22, a flash control unit 23, and a CF interface 24.

The CF interface 24 includes a control logic section 25, an ATA register 26, an attribute buffer 27, and a sector buffer 28.

The control logic unit 25 receives the control signal CTRL and the address ADD from the host interface 10 to control the attribute buffer 27 and the sector buffer 28.

The ATA register 26 stores transmission / reception information between the host interfaces 100.

The attribute buffer 27 stores attribute information of data received from the host interface 10 and is implemented with a size of 256 bytes.

The sector buffer 28 receives data from the host interface 10 or the flash memory array 30 and stores the data. The sector buffer 28 is implemented with one sector and one sector with a size of 512 bytes.

The flash memory array 30 includes a plurality of memory cells to store data.

The conventional CF card controller having the above configuration has only a buffer corresponding to one sector size to perform a single read / write sector command. However, the read / write sector is executed when the multi-read / write sector command is executed. There is a problem in that it is difficult to implement a high data transfer rate because the instruction cannot be continuously executed.

An object of the present invention for solving the above problems is to implement high-speed data transmission and reception by ensuring continuous data transmission and reception using a sector buffer consisting of eight sectors.

The present invention for achieving the above object is at least one of a multi-read or multi-write operation having a host interface attempting to communicate with the host, a flash memory array having a plurality of cells for storing data, and a plurality of sectors And a compact flash card controller configured to continuously store or output the data one by one of the plurality of sectors according to the command signal received from the host interface. .

The above and other objects and features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a diagram illustrating a connection between a host 11 and a compact flash card (CF card) 12 according to an embodiment of the present invention.

The host 11 is a communication device such as a computer. The CF card 12 may include a flash memory for temporarily storing and deleting data, and may transmit and receive data to and from the host 11.

4 is a detailed configuration diagram of the CF card 12 of FIG.

The CF card 12 includes a host interface 100, a CF card controller 200, and a flash memory array 300.

The host interface 100 is for transmitting and receiving between the host 11 and the CF card 12, receives an address, a command signal, a control signal and data from the host 11 and transmits it to the CF card controller 200, Control signals, data, and the like are received from the CF card controller 200 and transmitted to the host 11.

The CF card controller 200 includes an internal memory 201, a central processing unit (CPU) 202, a flash memory controller 203, and a CF interface 204.

The internal memory 201 temporarily stores an internal operation result of the central processing unit 202.

The central processing unit 202 controls the internal memory 201, the flash memory control unit 203, and the CF interface 204.

The flash memory controller 203 controls the flash memory array 300 under the control of the central processing unit 202 to transmit and receive data.

The CF interface 204 includes a control logic unit 205, an ATA register 206, an attribute buffer 207, and a driver 210. The control logic unit 205 receives the control signal CTRL and the address ADD from the host interface 100 to control the attribute buffer 207 and the driver 210. The ATA register 26 stores transmission / reception information between the host interfaces 100. The attribute buffer 207 stores attribute information of data received from the host interface 100 and is implemented with a size of 256 bytes.

The driver 210 includes a sector buffer 211, an address counter 212, a sector pointer 213, and a transfer counter 214.

The sector buffer 211 receives data from the host interface 100 or the flash memory array 300 and stores the data. The sector buffer 211 is implemented with 8 sectors in total and 512 bytes in one sector.

That is, the sector buffer 211 consists of two dual port RAMs of 2048 bytes, and logically divides two memories into eight regions. Each memory divided into eight areas has an even data register and an odd data register, and the data bus is 8 bits.

The address counter 212 counts the addresses of the sectors in use among the sectors of the sector buffer 211 and counts up to 256 values, and outputs an 8-bit counting value.

The sector pointer unit 213 is a pointer indicating a sector in which data is transmitted and received with the host 100, and is implemented in 3 bits. The sector pointer portion 213 points to the upper three bits of the 4096-byte sector buffer 208 when the sector buffer accesses the sector buffer. At this time, the sector pointer indicates which sector of the eight sectors of the sector buffer 211 is to be transferred.

The transfer counter 214 is a register that stores a sector count to be transferred data with the host 100. Transfer counter 214 is counted down to decrease the value by one each time one sector transmits data, and stops data transfer when the counting value reaches " 0 ".

The transfer counter 210 always maintains a sector counter value of "0" when performing an operation by a write sector command.

The transfer counter 214 is a down counter, and decreases by one for each data transfer from eight sectors of the sector buffer 211. When the counting value of the transfer counter 214 becomes "0", the compact flash card controller 200 Stops the data transfer operation.

The flash memory array 300 includes a plurality of memory cells to store data.

5 to 8, the operation and operation of the compact flash card according to the embodiment of the present invention will be described.

5 is a flowchart illustrating a single read method of the compact flash card of FIG. 4.

First, the host 11 transmits an address and read sector command signal to the compact flash card 12. The host interface 100 of the compact flash card 12 receives an address and a read command signal and transmits the received address and read command signal to the compact card controller 200 (S51).

 The compact card controller 200 sets the value of the transfer counter to 1 (S52), and reads data (512 bytes) corresponding to an address from the flash memory array 300. At this time, the overflow bit of the address counter 21 is set to "0", and the value of the sector pointer 213 is "0". The sector buffer 211 sequentially stores the read data (512 bytes) from the lowest address (S54).

The compact card controller 200 notifies that the host 11 is ready to transmit data by setting the DRQ bit of the status register (not shown) to "1" (S55).

The host 11 reads data (512 bytes) stored in the sector buffer 211 (S56). At this time, the address of the sector buffer 211 to be accessed by the host 11 is determined using the output 8 bits of the address counter 212 and the output 3 bits of the sector pointer 213.

When the host 11 reads data from the sector buffer 211, the overflow bit of the address counter 212 is set to "1", the value of the sector pointer 213 is maintained at "0", and the transfer is performed. The value of the counter 214 is cleared to "0" (S57).

6 is a flowchart illustrating a multi-read method of the compact flash card of FIG. 4.

First, the host 11 transmits an address and read sector command signal to the host interface 100 of the compact flash card 12. The host interface 100 transmits an address and read sector command signal to the compact flash card controller 200 (S61).

The compact flash card controller 200 copies and stores the value of the ATA register 206 to the transfer counter 214 (S62).

The compact flash card controller 200 reads data (512 bytes) corresponding to an address from the flash memory array 300 (S63) and stores data (512 bytes) in the sector buffer 211 (S64).

Thereafter, the sector pointer portion 213 increases the sector pointer value, and determines whether the increased sector pointer value is "4" (S65).

If the increased sector pointer value does not reach " 4 ", steps S63 and S64 are repeated to continuously read data from the flash memory array 300 and store the data in the sector buffer 211.

On the other hand, when the increased sector pointer value becomes "4", data is stored four times in 512 bytes each in the lower 2Kbyte areas (addresses 000h to 3FFh) of the sector buffer 211, thereby storing a total of 2048 bytes of data.

The compact flash card controller 200 sets the value of the DRQ bit in the status register (not shown) to "1" to inform the host 11 that the data transfer preparation is completed (S66).

The host 11 reads data (512 bytes) from the sector buffer 211 (S67).

When the data (512 bytes) read operation of step S67 is completed, the sector pointer unit 213 decreases the sector pointer value and determines whether the sector pointer value is "0".

If the sector pointer value is not " 0 ", the host 11 continues to read data from the sector buffer 211 by repeating the above step S67, until the sector pointer value becomes " 0 " Reads data from the sector buffer 211 four times by 512 bytes each to read a total of 2048 bytes of data.

When the data (2048 bytes) read operation is completed, the CPU 202 determines whether the overflow bit of the address counter 212 is "1". If the overflow bit is not "1", steps S63 to S68 are repeated. At this time, the sector buffer 211 stores the data read from the flash memory array 300 in the upper 2 Kbytes area (address 400h to 7FFh).

On the other hand, when the overflow bit value of the address counter 212 in step S69 is "1", the values of the sector pointer 213 and the transfer counter 214 become "0".

7 is a flowchart illustrating a single write method of the compact flash card of FIG. 4.

First, the host 11 transmits an address and a write sector command signal to the host interface 100. The host interface 100 transmits an address and a write sector command signal to the compact flash card controller 200 (S71).

The compact flash card controller 200 sets the value of the transfer counter 214 to "1" (S72).

The compact flash card controller 200 sets the DRQ bit value of the status register (not shown) to "1" to inform the host 11 that it is ready to write data (S73).

The host 11 transmits data (512 bytes) to be written to the sector buffer 211 and sequentially stores the data from the lowest address of the sector buffer 211 (S74).

The address counter 212 sets the overflow bit value to "1", sets the sector pointer value of the sector pointer portion 213 to "0", and clears the value of the transfer counter 214 to "0". (S75).

The sector buffer 211 transfers and stores data (512 bytes) to the flash memory array 300 (S76).

8 is a flowchart illustrating a multi-write method of the compact flash card of FIG. 4.

First, the host 11 transmits an address and a write sector command signal to the host interface 100. The host interface 100 transmits an address and a write sector command signal to the compact flash card controller 200 (S81).

The compact flash card controller 200 copies and stores the value of the ATA register 206 to the transfer counter 214 (S82).

The compact flash card controller 200 sets the DRQ bit value of the status register (not shown) to "1" to inform the host 11 that it is ready to receive data write (S83).

The host 11 transmits data (512 bytes) to be written to the sector buffer 211 and sequentially stores the data from the lowest address of the sector buffer 211 (S84).

Thereafter, the sector pointer portion 213 increases the sector pointer value and determines whether the increased sector pointer value is "4" (S85).

If the increased sector pointer value does not reach "4", the host 11 repeatedly stores the data in the sector buffer 211 by 512 bytes by repeating step S4.

On the other hand, when the increased sector pointer value becomes "4", the sector buffer 211 stores the data of 2048 bytes by storing 512 bytes of data four times in the lower 2Kbyte area (addresses 000h to 3FFh).

When a total of 2048 bytes of data is stored in the sector buffer 211, the compact flash card controller 200 transmits the stored data to the flash memory array 300 by 512 bytes (S86).

Thereafter, the sector pointer portion 213 decreases the sector pointer value and determines whether the sector pointer value is "0" (S87).

If the sector pointer value is not " 0 ", the above step S88 is repeated, until the sector pointer value is " 0 ". The compact flash card controller 200 flashes the data in the sector buffer 211 by 512 bytes of flash memory. By transmitting to the array 300, a total of four transfers are made, so that a total of 2048 bytes of data are stored in the flash memory array 300.

Thereafter, when the write operation of the data (2048 bytes) is completed, the central processing unit 202 determines whether the overflow bit of the address counter 212 is "1" (S88). If the overflow bit is not "1", the steps S83 to S87 are repeated. At this time, the sector buffer 211 stores the data received from the host 11 in the upper 2 Kbytes area (address 400h to 7FFh).

On the other hand, when the overflow bit value of the address counter 212 in step S88 is "1", the values of the sector pointer 213 and the transfer counter 214 become "0" (S89).

As described above, the present invention enables the high-speed operation by continuously transmitting and receiving data between the host and the compact flash card.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, replacements and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

1 is a connection diagram between a conventional host and a compact flash card.

FIG. 2 is a detailed configuration diagram of the compact flash card of FIG. 1. FIG.

Figure 3 is a connection diagram between the host and the compact flash card according to an embodiment of the present invention.

4 is a detailed configuration diagram of the compact flash card of FIG.

5 is a flow chart showing a single read method of the compact flash card of FIG.

6 is a flow chart showing a multi-read method of the compact flash card of FIG.

7 is a flow chart showing a single write method of the compact flash card of FIG.

8 is a flow chart showing a multi-write method of the compact flash card of FIG.

Claims (6)

A host interface attempting to communicate with the host; A flash memory array having a plurality of cells for storing data; Having a plurality of sectors, when performing at least one of a multi-read or a multi-write operation, storing or outputting the data continuously transmitted and received one by one of the plurality of sectors according to a command signal received from the host interface A compact flash card controller that performs one of the following; And Compact flash card, characterized in that the configuration, including. The method of claim 1, wherein the compact flash card controller, A compact flash interface for continuously transmitting and receiving data between the host interface and the flash memory array; A flash memory controller which controls data transmission and reception with the flash memory array; And A central processor configured to control operations of the compact flash interface and the flash memory controller; Compact flash card, characterized in that provided with. The method of claim 2, wherein the compact flash interface, A register for storing transmission and reception information with the host interface; A driver for sequentially storing and outputting data one by one of the plurality of sectors to continuously input and output the data of the host interface; And A control logic unit which receives the control signal and the address signal from the host interface and controls the driver; Compact flash card, characterized in that provided with. The method of claim 3, wherein the driving unit, A sector buffer consisting of a plurality of sectors; A sector pointer unit for indicating a position of a sector in use among the plurality of sectors; An address counter for generating an address of the sector in use; And A transmitter counter down counting each time the data is transmitted to the host interface; Compact flash card, characterized in that provided with. 5. The compact flash card of claim 4, wherein the sector buffer comprises dual port RAM. The method of claim 4, wherein the sector buffer And a size of 512 bytes per sector of the plurality of sectors.