CN110968538A

CN110968538A - Data buffering method and device

Info

Publication number: CN110968538A
Application number: CN201811141079.4A
Authority: CN
Inventors: 蔡飞
Original assignee: Loongson Technology Corp Ltd
Current assignee: Loongson Technology Corp Ltd
Priority date: 2018-09-28
Filing date: 2018-09-28
Publication date: 2020-04-07
Anticipated expiration: 2038-09-28
Also published as: CN110968538B

Abstract

The embodiment of the invention provides a data buffering method and a data buffering device, wherein the method comprises the following steps: acquiring the data length of the write/read operation, the start position information of the first valid byte data on the internal bus, and the data operation pointer on the multi-block dual port RAM, determining operation position information of the write/read operation on the plurality of dual port RAMs according to the data length of the write/read operation and the data operation pointer, rearranging the corresponding byte data of the plurality of dual port RAMs according to the operation position information and the start position information of the write/read operation, and performs a write/read operation of the data buffer, avoids the limitation that the source address and the destination address of the DMA controller need to be aligned, and the trigger is not added, so that the chip area occupied by adding the trigger is reduced, when the situation that the source address and the destination address are not aligned is processed, the data does not need to be shifted through a trigger, and the delay of reading the data from the read port of the dual-port RAM to the internal bus is reduced.

Description

Data buffering method and device

Technical Field

The present invention relates to the field of data processing technologies, and in particular, to a data buffering method and a data buffering device.

Background

A Direct Memory Access (DMA) controller is a common DMA controller in a System on chip (SoC). Such a DMA controller is used to carry data of a specified length from a source address to a destination address over a bus-on-chip network of the SoC.

In order to improve the utilization efficiency of the on-chip bus, the DMA controller typically internally buffers data read from a source address and writes the buffered data to a destination address. When the DMA controller buffers data, commonly used buffer resources include a dual-port RAM (random access memory) and a flip-flop. The trigger has the characteristic of flexible use. The use of dual port RAM is less flexible than flip-flops. When storing data of the same capacity, the area of the chip occupied by the dual port RAM is usually much smaller than the area of the chip occupied by the flip-flop.

Dual port RAMs typically have a write port and a read port that may share a clock input or may each use a separate clock input. The write port of a dual port RAM typically contains: write address, write data, write enable, write clock. At each rising edge of the write clock, if the write enable is valid, the write data is written to the location specified by the write address in the RAM. The read port of a dual port RAM typically contains: read address, read enable, read data, read clock. At each rising edge of the read clock, if the read enable is valid, the data specified by the read address appears on the read data port before the next rising edge of the read clock. When the read enable is valid, the data specified by the read address in the current clock cycle of the dual-port RAM read port appears on the read data port in the next clock cycle.

The DMA controller uses 1 block of dual port RAM with the same bit width as the on-chip bus as a data buffer. The DMA controller provides a write pointer and a read pointer for the dual port RAM. The DMA controller uses a counter for recording the amount of data in the dual port RAM. This counter counts the number of items of valid data stored in the dual port RAM based on write and read operations of the DMA controller to the dual port RAM. The DMA controller directly writes the data read from the internal bus into the write port of the dual port RAM and increments the write pointer each time the DMA controller obtains source data from the internal bus. When the data quantity counter of the dual-port RAM reaches a set threshold value, the DMA controller starts to read data from a read port of the dual-port RAM, and the data of the read port of the dual-port RAM is directly used as data on the internal bus and written into a specified destination address by the DMA controller. The DMA controller increments the read pointer every time data is read from the dual port RAM.

In the first scheme, since the DMA controller directly writes source data returned by the internal bus into the dual port RAM and directly sends data of the read port of the dual port RAM as destination data onto the internal bus, the DMA controller requires alignment of the lower order addresses of the start source address and the start destination address. The low bits of the address here refer to the portions that are less than the width of the bus bit. The DMA controller in this scheme requires the lower M bits of the start source address and the lower M bits of the start destination address to be the same value if the bit width of the internal bus is a power of M bytes of 2.

On the basis of the first scheme, a second scheme also exists, and a group of flip-flops with the same bit width as the internal bus are added outside a read port of the dual-port RAM. The mode of DMA data entering and exiting the dual port RAM is unchanged, when the low order bits of the source address and the destination address of the DMA are not aligned, the DMA firstly reads the data from the dual port RAM into the group of flip-flops, and then selects the DMA data from the group of flip-flops and the read port of the dual port RAM to be sent to the internal bus according to the difference of the low order bits of the source address and the destination address.

In the second scheme, the limitation of low order address alignment between the DMA source address and the DMA destination address in the first scheme is avoided, but adding a set of flip-flops having the same width as the internal bus causes an increase in the chip area occupied by the DMA controller. Such an influence on the increase of the chip area is more obvious in the implementation of a Field-Programmable Gate Array (FPGA).

Disclosure of Invention

The technical problem to be solved by the embodiments of the present invention is to provide a data buffering method and device, so as to avoid the limitation that the source address and the destination address of the DMA controller need to be aligned, reduce the chip area occupied by adding a trigger, and reduce the delay of reading data from the dual port RAM read port to the internal bus.

In order to solve the above problem, the present invention discloses a data buffering method, comprising:

acquiring the data length of the write/read operation;

acquiring initial position information corresponding to first effective byte data of write/read operation on an internal bus;

acquiring data operation pointers corresponding to write/read operations on a plurality of dual-port RAMs, wherein the dual-port RAMs store one byte of data at a time, and the number of the blocks of the dual-port RAMs is the same as the maximum number of the byte data transmitted by the internal bus at a time;

determining operation position information of the write/read operation on the multi-block dual-port RAM according to the data length of the write/read operation and the data operation pointer;

rearranging the byte data corresponding to the multiple dual-port RAMs according to the operation position information and the initial position information of the write/read operation, and executing the write/read operation of data buffering.

Optionally, the method further comprises:

and generating and recording the next data operation pointer according to the data length of the write/read operation and the recorded data operation pointer.

Optionally, the determining the operation position information on the multi-block dual port RAM according to the data length of the write/read operation and the data operation pointer includes:

and generating an intra-block position identifier of the write/read operation on each block dual-port RAM according to the data length of the write/read operation and the data operation pointer.

Optionally, the generating the intra-block location identifier of the write operation on each block dual port RAM according to the data length of the write operation and the data operation pointer includes:

determining enabling signals of write operation on the block dual-port RAMs according to the data length of the write operation and the block identifiers of the dual-port RAMs in the data operation pointers;

and determining the position identification in the block of the write operation on each block of the dual-port RAM according to the enabling signal of the write operation and the position identification in the block of the dual-port RAM in the data operation pointer.

Optionally, the determining, according to the data length of the write operation and the block identifier of the first dual port RAM, the enable signal of the write operation on each block dual port RAM includes:

determining enabling information corresponding to the intra-block position identifier of the write operation in the data operation pointer and the intra-block position identifier of the next data operation pointer according to the data length of the write operation and the block identifier of the dual-port RAM in the data operation pointer;

and determining an enabling signal of the write operation on each block of dual-port RAM according to the enabling information.

Optionally, the generating, by the data operation pointer, an intra-block location identifier of a read operation on each block of the dual port RAM includes:

determining enabling information corresponding to the intra-block position identifier of the read operation in the data operation pointer and the intra-block position identifier of the next data operation pointer according to the data length of the read operation and the block identifier of the dual-port RAM in the data operation pointer;

when the DMA controller sends an effective enabling signal to the dual-port RAM, determining the position identification in the block of the read operation on each dual-port RAM according to the enabling information and the position identification in the block in the data operation pointer;

and determining the position identification in the block of the read operation on each block of the dual-port RAM according to the enabling information and the position identification in the block in the next data operation pointer.

Optionally, the rearranging, according to the operation position information and the start position information of the write operation, the byte data corresponding to the multiple dual port RAMs, and performing a write operation of data buffering includes:

selecting byte data of the write operation for each dual-port RAM on the internal bus according to the operation position information and the initial position information of the write operation;

and writing the selected byte data into the corresponding dual-port RAM according to the operation position information.

Optionally, the selecting, on the internal bus, byte data of the write operation for each dual port RAM according to the operation position information and the start position information of the write operation includes:

arranging effective data returned by the internal bus according to the initial position information of the write operation and the sequence of the small tail end, and assigning the effective data to first temporary data, wherein the number of byte data in the first temporary data is the same as the maximum number of byte data transmitted by the internal bus at one time;

assigning the first temporary data to high-N byte data and low-N byte data of second temporary data, wherein the number 2N of the byte data in the second temporary data is the same as twice of the maximum number of the byte data transmitted by the internal bus at one time;

determining the bit number of the right shift of the second temporary data according to the operation position information of the write operation and the maximum number of the byte data transmitted by the internal bus at one time, assigning the second temporary data to third temporary data after the second temporary data is shifted to the right, wherein the number 2N of the byte data in the third temporary data is the same as twice of the maximum number of the byte data transmitted by the internal bus at one time;

the writing the selected byte data into the corresponding dual-port RAM according to the operation position information of the write operation comprises:

and writing the low N-bit byte data of the third temporary data into the corresponding dual-port RAM.

Optionally, the rearranging, according to the operation position information and the start position information of the read operation, the corresponding byte data of the multiple dual port RAMs, and performing a read operation of data buffering includes:

rearranging the byte data read out from the plurality of dual port RAMs in accordance with the output order of the internal bus in accordance with the operation position information and the start position information of the read operation;

and reading the byte data read out by the arranged dual-port RAM to the internal bus according to the initial position information of the read operation.

Optionally, the rearranging the byte data read out from the multiple dual port RAMs in the output order of the internal bus according to the operation position information and the start position information of the read operation includes:

assigning the byte data read by the multiple dual-port RAMs to fourth temporary data, wherein the number of the byte data in the fourth temporary data is the same as the maximum number of the byte data transmitted by the internal bus at one time;

assigning the fourth temporary data to high-N byte data and low-N byte data of fifth temporary data, wherein the number 2N of the byte data in the fifth temporary data is twice as large as the maximum number of the byte data transmitted by the internal bus at one time;

determining the number of bits of the fifth temporary data which are shifted to the right according to the operation position information, assigning the bits to sixth temporary data after the fifth temporary data are shifted to the right, wherein the number 2N of byte data in the sixth temporary data is the same as twice of the maximum number of byte data transmitted by the internal bus at one time;

arranging the sixth temporary data according to the sequence of the small tail end, assigning the low N byte data of the sixth temporary data to seventh temporary data, wherein the number of the byte data in the seventh temporary data is the same as the maximum number of the byte data transmitted by the internal bus at one time;

the reading the arranged byte data to the internal bus according to the start position information of the read operation includes:

and determining the number of bits of the seventh temporary data which are left-shifted according to the initial position information of the reading operation, and outputting the seventh temporary data to the internal bus after the seventh temporary data are left-shifted.

Correspondingly, an embodiment of the present invention further provides a data buffering apparatus, including:

the length acquisition module is used for acquiring the data length of the write/read operation;

the starting information acquisition module is used for acquiring the starting position information corresponding to the first effective byte data on the internal bus of the write/read operation;

the operation information acquisition module is used for acquiring data operation pointers corresponding to write/read operations on a plurality of dual-port RAMs, wherein the dual-port RAMs store one byte of data at a time, and the number of the blocks of the dual-port RAMs is the same as the maximum number of the byte data transmitted by the internal bus at a time;

the information determining module is used for determining the operation position information of the write/read operation on the multi-block dual-port RAM according to the data length of the write/read operation and the data operation pointer;

and the operation module is used for rearranging the corresponding byte data of the multiple double-port RAMs according to the operation position information and the initial position information of the write/read operation and executing the write/read operation of data buffering.

Optionally, the apparatus further comprises:

and the pointer generating module is used for generating and recording the next data operation pointer according to the write/read operation data length and the recorded data operation pointer.

Optionally, the operation location information includes an intra-block location identifier in a dual port RAM, and the information determining module includes:

and the mark generation submodule is used for generating the position marks in the blocks of the write/read operation on the dual-port RAM according to the write/read operation data length and the data operation pointer.

Optionally, the data operation pointer includes a block identifier of the dual port RAM and an intra-block location identifier in the dual port RAM, and the identifier generation sub-module includes:

a first signal determining unit, configured to determine, according to the data length of the write operation and the block identifier of the dual port RAM of the data operation pointer, an enable signal of the write operation on each block of the dual port RAM;

and the identification determining unit is used for determining the position identification in the dual-port RAM in the write operation according to the enabling signal of the write operation and the position identification in the dual-port RAM in the data operation pointer.

Optionally, the signal determination unit includes:

the information determining subunit is used for determining enabling information corresponding to the intra-block position identifier of the write operation in the data operation pointer and the intra-block position identifier of the next data operation pointer according to the data length of the write operation and the block identifier of the dual-port RAM in the data operation pointer;

and the signal determining subunit is used for determining an enabling signal of the write operation on each block of dual-port RAM according to the enabling information.

a second information determining unit, configured to determine, according to the data length of the read operation and the block identifier of the dual-port RAM in the data operation pointer, enable information corresponding to an intra-block location identifier of the read operation in the data operation pointer and an intra-block location identifier of a next data operation pointer;

an identification determining unit, configured to determine, when the DMA controller provides an effective enable signal to the dual port RAM, an intra-block location identification of a read operation on each dual port RAM according to the enable information and the intra-block location identification in the data operation pointer;

and the identification determining unit is used for determining the in-block position identification of the read operation on each block dual-port RAM according to the enabling information and the in-block position identification of the next data operation pointer.

Optionally, the operation module includes:

the selecting submodule is used for selecting byte data of the write operation for each dual-port RAM on the internal bus according to the operation position information and the initial position information of the write operation;

and the writing sub-module is used for writing the selected byte data into the corresponding dual-port RAM according to the operation position information.

Optionally, the selecting sub-module includes:

the first arranging unit is used for arranging the effective data returned by the internal bus according to the initial position information of the write operation and the sequence of the small tail end and assigning the effective data to first temporary data, wherein the number of byte data in the first temporary data is the same as the maximum number of byte data transmitted by the internal bus at one time;

a first assignment unit, configured to assign the first temporary data to high-N byte data and low-N byte data of second temporary data, where the number 2N of byte data in the second temporary data is equal to twice the maximum number of byte data transmitted by the internal bus at one time;

the first right shift unit is used for determining the bit number of the right shift of the second temporary data according to the operation position information of the write operation and the maximum number of the byte data transmitted by the internal bus at one time, assigning the second temporary data to third temporary data after the right shift of the second temporary data, wherein the number 2N of the byte data in the third temporary data is the same as twice of the maximum number of the byte data transmitted by the internal bus at one time;

the write submodule includes:

and the writing unit is used for writing the low N byte data of the third temporary data into the corresponding dual-port RAM.

Optionally, the operation module includes:

an arrangement submodule configured to rearrange the byte data read from the plurality of dual port RAMs in accordance with the output order of the internal bus based on the operation position information and the start position information of the read operation;

and the reading submodule is used for reading the byte data read out by the arranged dual-port RAM to the internal bus according to the initial position information of the reading operation.

Optionally, the permutation submodule includes:

a second assignment unit, configured to assign byte data read from the multiple dual port RAMs to fourth temporary data, where the number of byte data in the fourth temporary data is the same as the maximum number of byte data transmitted by the internal bus at one time;

a third assignment unit, configured to assign the fourth temporary data to high-N byte data and low-N byte data of fifth temporary data, where the number 2N of byte data in the fifth temporary data is equal to twice the maximum number of byte data transmitted by the internal bus at one time;

the second right shift unit is used for determining the right shift digit of the fifth temporary data according to the operation position information, assigning the fifth temporary data to sixth temporary data after the fifth temporary data is shifted to the right, and the number 2N of byte data in the sixth temporary data is the same as twice of the maximum number of byte data transmitted by the internal bus at one time;

the second arranging unit is used for arranging the sixth temporary data according to the sequence of the small tail end, assigning the low N byte data of the sixth temporary data to seventh temporary data, wherein the number of the byte data in the seventh temporary data is the same as the maximum number of the byte data transmitted by the internal bus at one time;

the reading sub-module includes:

and the output unit is used for determining the number of bits of the seventh temporary data which are left-shifted according to the initial position information of the reading operation, and outputting the seventh temporary data to the internal bus after the seventh temporary data are left-shifted.

According to the embodiment of the invention, by acquiring the data length of the write/read operation, acquiring the initial position information of the first effective byte data on the internal bus of the write/read operation and acquiring the data operation pointer of the write/read operation on the multi-block dual-port RAM, determining the operation position information of the write/read operation on the multi-block dual-port RAM according to the data length and the data operation pointer of the write/read operation, rearranging the corresponding byte data of the multi-block dual-port RAM according to the operation position information and the initial position information of the write/read operation, and executing the write/read operation of data buffering, the limitation that the source address and the destination address of the DMA controller need to be aligned is avoided, no additional trigger is provided, the chip area required to be occupied by the additional trigger is reduced, when the source address and the destination address are not aligned, the data is shifted without passing through a flip-flop, which in turn reduces the delay of reading data from the dual port RAM read port to the internal bus.

Drawings

FIG. 1 is a flow chart illustrating steps of a data buffering method according to a first embodiment of the present invention;

FIG. 2 is a flow chart illustrating steps of a data buffering method according to a second embodiment of the present invention;

fig. 3 is a block diagram illustrating a data buffering apparatus according to a third embodiment of the present invention.

Detailed Description

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.

Referring to fig. 1, a flowchart illustrating steps of a data buffering method according to a first embodiment of the present invention is shown, which may specifically include the following steps:

step 101, acquiring the data length of the write/read operation, the start position information of the first effective byte on the internal bus of the write/read operation, and the data operation pointer corresponding to the write/read operation on the multi-block dual-port RAM.

A device such as a DMA controller may internally buffer data read from a source address and then write to a destination address, where a write operation is a writing of data from an internal bus to a buffer by the DMA controller, and a read operation is a reading of data from the buffer to the internal bus by the DMA controller.

In the embodiment of the present invention, the buffer used by the DMA controller and other devices is composed of a plurality of identical dual port RAMs, and the data bit width of each dual port RAM is 1 byte, where a byte is the minimum storage unit when the DMA controller buffers data. The block number of the dual-port RAM is the same as the byte number of the bit width of the internal bus, namely the maximum number of byte data transmitted by the internal bus at one time.

In the embodiment of the invention, a device such as a DMA controller records the data operation pointer of the starting position of the current write data or the current read data on the multi-block dual port RAM. The data operation pointer includes a block identifier of the dual port RAM, an identifier of a location in a block in the single-block dual port RAM, or any other suitable form to record an operation location, which is not limited in this embodiment of the present invention. For the write operation and the read operation, it is necessary to record data operation pointers, respectively, the data operation pointer for the write operation being a position after a position where the last write operation was written in the multi-block dual port RAM, and the data operation pointer for the read operation being a position after a position where the last read operation was read in the multi-block dual port RAM.

For example, the bit width of the internal bus to which the DMA controller is connected is N bytes, N is the power of M of 2, the DMA controller uses N dual port RAMs having a bit width of 1 byte as data buffers, the depth of the dual port RAMs is K, and K is the power of L of 2. Recording all the positions on the multi-block dual-port RAM is realized using one write pointer wptr (i.e., a data operation pointer for write operation) for recording the start position of currently written data in the multi-block dual-port RAM and one read pointer rptr (i.e., a data operation pointer for read operation) for recording the start position of currently read data in the multi-block dual-port RAM, the bit widths of the write pointer and the read pointer being L + M bits, where the high L bits are used to record the intra-block position identification of data in the single-block dual-port RAM (i.e., the high L bits of the read/write pointer) and the low M bits are used to record the block identification of the dual-port RAM to which the data belongs (i.e., the low M bits of the read/.

In embodiments of the present invention, the DMA controller provides parameters for operations while writing/reading the buffer. The DMA controller provides the data length of the current read/write operation while reading/writing the buffer each time, and the unit of the data length is bytes, and the value of the data length is less than or equal to N. The DMA controller writes the buffer each time and provides initial position information WP of the first effective byte data of the currently written data on the internal bus data with the width of N bytes, wherein the value of WP is 0-N-1; the DMA controller provides start position information RP of the first valid byte data of the currently read data on the internal bus with the width of N bytes while reading the buffer each time, and the value of RP is 0 to N-1. For a write operation and a read operation, it is necessary to provide the data length and the start position information of the first valid byte data on the internal bus, respectively.

And 102, determining the operation position information of the write/read operation on the multi-block dual-port RAM according to the data length of the write/read operation and the data operation pointer.

In the embodiment of the invention, the operation position information of the current write operation on each block dual-port RAM can be generated through the data operation pointer and the data length of the write operation, and the data operation pointer of the next write operation can also be generated. The operation position information of the read operation on each dual-port RAM can be generated through the data operation pointer and the data length of the read operation, and the data operation pointer of the next read operation can also be generated.

In this embodiment of the present invention, specific implementation manners for determining the operation location information of the write/read operation on the multiple dual port RAMs according to the data length of the write/read operation and the data operation pointer may include multiple types, for example, an intra-block location identifier of the write/read operation on each block dual port RAM may be generated according to the data length of the write/read operation and the data operation pointer, and may specifically include any applicable implementation manner, which is not limited in this embodiment of the present invention.

For example, by means of the current write pointer wptr and the current write data length wstep: a write pointer (the current value of wptr is increased by wstep) of the next write operation, and write enable and write addresses of the N-block dual-port RAM; generated by the current read pointer rptr and the current read data length rstep: the read pointer of the next read operation (the current rptr value is increased by rstep), and the read address of the N-block dual-port RAM.

And 103, rearranging the byte data corresponding to the multiple dual-port RAMs according to the operation position information and the initial position information of the write/read operation, and executing the write/read operation of data buffering.

In an embodiment of the present invention, handling DMA data allows the source and destination addresses to be misaligned, that is, at the time of a write operation, write data on the internal bus may be written to different depths of the multi-block dual port RAM, and at the time of a read operation, the internal bus may read data from different depths of the multi-block dual port RAM. If one dual port RAM is considered as a column and the same depth of the multiple dual port RAMs is considered as a row, a write operation may start from the middle column of a row and end to the middle column of the next row, and a read operation may also start from the middle column of a row and end to the middle column of the next row. Therefore, it is necessary to rearrange the corresponding byte data of the plurality of dual port RAMs according to the operation position information and the start position information and then perform a write operation or a read operation of the data buffer.

In the embodiment of the present invention, the specific implementation manner of rearranging the corresponding byte data of the plurality of dual port RAMs according to the operation position information of the write/read operation and the start position information of the first valid byte data on the internal bus and performing the write operation or the read operation of the data buffer may include a plurality of types, for example, during the write operation, the byte data of the write operation is selected for each dual port RAM on the internal bus according to the operation position information and the start position information, and the selected byte data is written into the corresponding dual port RAM according to the operation position information; in a read operation, the read byte data of the multiple dual-port RAMs are rearranged according to the operation position information and the start position information of the valid data on the internal bus and according to the output order of the internal bus, and the arranged byte data is read to the internal bus according to the start position information of the valid data on the internal bus.

According to the embodiment of the invention, by acquiring the data length of the write/read operation, the initial position information of the first effective byte data on the internal bus of the write/read operation and the data operation pointer of the write/read operation on the plurality of dual-port RAMs, determining the operation position information of the write/read operation on the plurality of dual-port RAMs according to the data length of the write/read operation and the data operation pointer, rearranging the corresponding byte data of the plurality of dual-port RAMs according to the operation position information and the initial position information of the write/read operation, and executing the write/read operation of data buffering, the limitation that the source address and the destination address of a DMA controller need to be aligned is avoided, no trigger is added, the occupied chip area required by the trigger is reduced, and when the source address and the destination address are not aligned, the data is shifted without passing through a flip-flop, which in turn reduces the delay of reading data from the dual port RAM read port to the internal bus.

Referring to fig. 2, a flowchart illustrating steps of a data buffering method according to a second embodiment of the present invention is shown, which may specifically include the following steps:

step 201, acquiring the data length of the write/read operation, the start position information of the first effective byte data of the write/read operation on the internal bus, and the data operation pointer of the write/read operation on the multi-block dual-port RAM.

In the embodiment of the present invention, the specific implementation manner of this step may refer to the description in the foregoing embodiment, and details are not described herein.

And step 202, generating and recording a next data operation pointer according to the write/read operation data length and the recorded data operation pointer.

In the embodiment of the invention, the DMA controller records the data operation pointer, and when the data operation pointer increases the data length, the next data operation pointer can be generated and recorded for use in the next write operation or read operation.

For example, in a write operation, 1 write pointer wptr (i.e., data operation pointer) of L + M bits is used to record the start position of the current write to the multi-block dual port RAM, the DMA controller provides the data length wstep (in bytes) of the current write data each time data is written to the multi-block dual port RAM, and the data operation pointer of the next write operation is generated by incrementing wstep by the value of wptr each time the DMA controller writes data to the buffer. In the read operation, a read pointer rptr (i.e., data operation pointer) of L + M bits is used for recording the start position of data currently read from the multi-block dual port RAM. The DMA controller provides the data length rstep (unit is byte) of the current read data while reading the data from the buffer every time, the value of rptr increases rstep every time the DMA controller reads the data from the buffer, and a data operation pointer of the next read operation is generated.

And 203, generating an intra-block position identifier of the write/read operation on each block of the dual-port RAM according to the data length of the write/read operation and the data operation pointer.

In the embodiment of the invention, according to the data operation pointer, the block identifier of the corresponding dual port RAM and the position identifier, namely the depth, in the block dual port RAM can be determined. The operation position information comprises an intra-block position identifier in the dual-port RAM, during write operation, write-in data on the internal bus can be written into different depths of the multiple dual-port RAMs, and the intra-block position identifier of the write operation on each block of the dual-port RAM can be generated according to the data length and the data operation pointer of the write operation; during reading operation, the internal bus may read data from different depths of the multi-block dual-port RAM, and according to the data length of the reading operation and the data operation pointer, an intra-block position identifier of the reading operation on each block dual-port RAM may be generated. Any suitable implementation may be specifically included, and the embodiment of the present invention is not limited thereto.

In a preferred embodiment of the present invention, the implementation manner of generating the intra-block location identifier of the write operation on each block of the dual port RAM according to the data length of the write operation and the data operation pointer may include: determining enabling signals of write operation on the block dual-port RAMs according to the data length of the write operation and the block identifiers of the dual-port RAMs of the data operation pointers; and determining the position identification in the block of the write operation on each dual-port RAM according to the enabling signal of the write operation and the position identification in the block of the data operation pointer.

The data length of the write operation is less than or equal to the maximum number of byte data transmitted by the internal bus at one time, so that in a write operation, there may be a case where no write data exists on part of the dual port RAM, the enable signal of the corresponding write operation should be set to be invalid, and in a dual port RAM with write data, the enable signal of the corresponding write operation should be set to be valid. Determining that the enabling signal of the write operation on each block dual port RAM may include any applicable implementation manner according to the data length of the write operation and the block identifier of the first block dual port RAM, which is not limited in this embodiment of the present invention.

In a preferred embodiment of the present invention, the determining, according to the data length of the write operation and the block identifier of the first block dual port RAM, an implementation manner of the enable signal for the write operation on each block dual port RAM may include: determining enabling information corresponding to the position identifier in the block of the data operation pointer and the position identifier in the block of the next data operation pointer of the write operation according to the data length of the write operation and the block identifier of the dual-port RAM of the data operation pointer; and determining an enabling signal of the write operation on each block of dual-port RAM according to the enabling information.

Since the write data on the internal bus may be written into two depths of the multi-block dual-port RAM during a write operation, the enable information of the location identifier in the block of the data operation pointer and the enable information corresponding to the location identifier in the block of the next data operation pointer are determined, and then the enable signal of the write operation on each block of the dual-port RAM is determined according to the enable information.

For example, the N-block dual port RAMs as data buffers are sequentially numbered RAM _0 to RAM _ N-1. A 2N-bit write enable mask we _ dual is used, where the lower N bits are the enable information for the write operation that identifies the location within the block of the data operation pointer and the upper N bits are the corresponding enable information for the location within the block of the next data operation pointer. When wptr [ M-1:0] (i.e., the block identification of the dual port RAM of the data operation pointer) < ═ i < wptr [ M-1:0] + wstep (i.e., the block identification of the dual port RAM of the data operation pointer plus the data length), the ith bit write enable mask we _ dual [ i ] is 1, otherwise we _ dual [ i ] is 0. The upper N bits (2N-1 to N bits, namely, the enable information of the position identifier in the block of the next data operation pointer) and the lower N bits (N-1 to 0 bits, namely, the enable information corresponding to the position identifier in the block of the data operation pointer) of we _ dual are logically OR-ed to generate an N-bit RAM write enable we (namely, the enable signal of the write operation), we [ i ] is the write enable of RAM _ i, and we [ i ] is 1 to indicate that the write enable of RAM _ i is valid.

Then, according to the enable signal of the write operation and the intra-block location identifier of the data operation pointer, the intra-block location identifier of the write operation on each dual-port RAM is determined, for example, the write pointer (i.e. the intra-block location identifier) of the RAM _ i (i has a value of 0-N-1) is generated in the following way: if we _ dual [ i ] (i has a value of 0 to N-1) has a value of 1, the write pointer of RAM _ i has a value of the upper L bits of wptr (wptr [ M + L-1: M ]), otherwise the write pointer of RAM _ i has a value of the upper L bits of wptr plus 1. Any suitable implementation may be specifically included, and the embodiment of the present invention is not limited thereto.

In a preferred embodiment of the present invention, the implementation manner of generating the intra-block location identifier of the read operation on each block of the dual port RAM according to the data length of the read operation and the data operation pointer may include: determining enabling information corresponding to the intra-block position identifier of the data operation pointer and the intra-block position identifier of the next data operation pointer of the read operation according to the data length of the read operation and the block identifier of the dual-port RAM of the data operation pointer; when the DMA controller gives an effective enabling signal to the dual-port RAM, determining the in-block position identification of the read operation on each block of the dual-port RAM according to the enabling information and the in-block position identification of the data operation pointer; and when the DMA controller gives an effective enabling signal to the dual-port RAM, determining the in-block position identifier of the read operation on each block of the dual-port RAM according to the enabling information and the in-block position identifier of the next data operation pointer.

The read enable signal of the multi-block dual port RAM is fixed to a constant value of 1 (read active). The in-block position identification of the read operation of each dual-port RAM is generated according to a data operation pointer, the data length of the read operation of the DMA controller and the read enable given to the buffer by the DMA controller. The internal bus may read data from two depths of the multi-block dual port RAM, determine enable information corresponding to the intra-block location identifier of the data operation pointer and the intra-block location identifier of the next data operation pointer for the read operation, and determine the intra-block location identifier of the read operation on each block dual port RAM according to the enable information and the intra-block location identifier of the data operation pointer.

For example, the dual port RAM read pointer is generated as follows:

a read enable mask re _ dual of 2N bits is used, where N bits are the enable information for the read operation identified at the intra-block location of the data operation pointer and the other N bits are the corresponding enable information identified at the intra-block location of the next data operation pointer. When rptr [ M-1:0] (i.e., the block identification of the dual port RAM of the data operation pointer) < ═ i < rptr [ M-1:0] + rstep (i.e., the block identification of the dual port RAM of the data operation pointer plus the data length), the enable information re _ dual [ i ] of the i-th bit is 1, otherwise re _ dual [ i ] is 0.

The intra-block location identification for a read operation of RAM _ i is generated in the following manner: when the DMA controller sends a reading request signal to the buffer to be invalid, if re _ dual [ i ] (the value of i is 0-N-1) is 1, the reading pointer (i.e. the position identification in the block) of the RAM _ i is the value of the high L bit (rptr [ M + L-1: M ]) of rptr, otherwise, the reading pointer (i.e. the position identification in the block) of the RAM _ i is the value of the high L bit of rptr plus 1; when the DMA controller asserts the buffered read request signal, if re _ dual [ i ] (i has a value of 0 to N-1) is 1, the read pointer of RAM _ i is the value of the upper L bit of the updated value of rptr (the current value of rptr is incremented by rstep), otherwise the read pointer of RAM _ i is the value of the upper L bit of the updated value of rptr incremented by 1.

And 204, selecting the byte data of the write operation for each dual-port RAM on the internal bus according to the operation position information and the initial position information of the write operation.

In the embodiment of the present invention, in the write operation, each dual port RAM selects write data on the N-byte wide internal bus return data line bus _ rdata through the current write pointer wptr and the start position information WP of the first valid byte data of the current write data on the N-byte wide internal bus.

In a preferred embodiment of the present invention, one implementation manner of selecting byte data of the write operation for each dual port RAM on the internal bus according to the operation position information and the start position information of the write operation may include:

arranging effective data returned by the internal bus according to the initial position information of the write operation and the sequence of the small tail end, and assigning the effective data to first temporary data, wherein the number of byte data in the first temporary data is the same as the maximum number of byte data transmitted by the internal bus at one time; assigning the first temporary data to high N-bit byte data and low N-bit byte data of second temporary data, wherein the number 2N of byte data in the second temporary data is the same as twice of the maximum number of byte data transmitted by the internal bus at one time; and determining the right shift digit of the second temporary data according to the operation position information of the write operation and the maximum number of the byte data transmitted by the internal bus at one time, assigning the second temporary data to third temporary data after the second temporary data is shifted to the right, wherein the number 2N of the byte data in the third temporary data is the same as twice of the maximum number of the byte data transmitted by the internal bus at one time.

For example, the DMA controller shifts the internal bus return data line bus _ rdata with N bytes width by WP × 8 bits to the right to obtain valid data returned by the internal bus, and assigns the valid data to the data line din with N bytes width (i.e., the first temporary data). The effective data returned by the internal bus is arranged on din according to the sequence of the small tail end. The 0 th valid byte data is in din [7:0], the 1 st valid byte data is in din [15:8], and the N-1 st valid byte is in din [ N8-1 (N-1) 8 ]. One data line din _ dual (i.e., second temporary data) of 2N byte width is used. The value of din _ dual for the low N byte width is din, as is the value of din _ dual for the high N byte width. One data line din _ shift (i.e., third temporary data) 2N bytes wide is used. The value of din _ shift results from din _ dual shifting the WS bit to the right. Wherein WS ═ (N-wptr [ M-1:0]) 8.

And step 205, writing the selected byte data into the corresponding dual-port RAM according to the operation position information of the write operation.

In the embodiment of the invention, after the byte data is selected, the byte data is written into the corresponding dual-port RAM according to the operation position information, and the writing operation of data buffering is completed.

In a preferred embodiment of the present invention, an implementation manner of writing the selected byte data into the corresponding dual port RAM according to the operation location information of the write operation may include: and writing the low N-bit byte data of the third temporary data into the corresponding dual-port RAM.

For example, the data input to the dual port RAM numbered i is din _ shift [ i × 8+7: i × 8 ]. i has a value of 0 to N-1.

And step 206, rearranging the byte data of the read operation of the multiple dual-port RAMs according to the operation position information and the initial position information of the read operation and the output sequence of the internal bus.

In the embodiment of the present invention, in the read operation, the read port values of the N-block dual port RAM are rearranged to the internal bus data output line bus _ wdata having the bit width of N bytes according to the read pointer rptr (i.e., the operation position information) and the start position information RP of the first valid byte data of the read data on the internal bus having the bit width of N bytes.

In a preferred embodiment of the present invention, one implementation manner of rearranging byte data read out by the multiple dual port RAMs in the output order of the internal bus based on the operation position information and the start position information of the read operation may include:

assigning the byte data read out by the multiple double-port RAMs to fourth temporary data, wherein the number of the byte data in the fourth temporary data is the same as the maximum number of the byte data transmitted by the internal bus at one time; assigning the fourth temporary data to high-N-bit byte data and low-N-bit byte data of fifth temporary data, wherein the number 2N of byte data in the fifth temporary data is the same as twice of the maximum number of byte data transmitted by the internal bus at one time; determining the right shift digit of the fifth temporary data according to the operation position information, assigning the fifth temporary data to sixth temporary data after the fifth temporary data is shifted to the right, wherein the number 2N of byte data in the sixth temporary data is the same as twice of the maximum number of byte data transmitted by the internal bus at one time; and arranging the sixth temporary data according to the sequence of the small tail end, assigning the lower N-bit byte data of the sixth temporary data to seventh temporary data, wherein the number of the byte data in the seventh temporary data is the same as the maximum number of the byte data transmitted by the internal bus at one time.

For example, the read port of each block of dual port RAM is numbered, the read port of the dual port RAM numbered i is numbered q _ i, and the value of i is 0 to N-1. One data line qout (i.e., fourth temporary data) of N bytes wide is used. The value of q _ i is assigned to qout [ i 8+7: i 8 ]. One data line qout _ dual (i.e., fifth temporary data) 2N bytes wide is used. The low N byte wide value of qout _ dual is qout, as is the high N byte wide value of qout _ dual. One data line qout _ shift (i.e., sixth temporary data) 2N bytes wide is used. The value of qout shift results from a shift of qout _ dual to the right by an RS bit. RS ═ rptr [ M-1:0] × 8. One N-byte wide data line qout fix (i.e., seventh temporary data) is used. After the shift, a low N-byte wide value of qout _ shift is given to qout _ fix. The read data are arranged in the order of small tail end, the data of 0 th effective byte is in qout _ fix [7:0], the data of 1 st effective byte is in qout _ fix [15:8], and the data of N-1 th effective byte is in qout _ fix [ N8-1 (N-1) × 8 ].

Step 207, reading the arranged byte data to the internal bus according to the initial position information of the read operation.

In the embodiment of the invention, after the read ports of the multi-block dual-port RAM are rearranged into the sequence required by the internal bus, the byte data is read to the internal bus, and the read operation is completed.

In a preferred embodiment of the present invention, an implementation manner of reading the arranged byte data to the internal bus according to the start position information of the read operation may include: and determining the number of bits of the seventh temporary data which are left-shifted according to the initial position information of the reading operation, and outputting the seventh temporary data to the internal bus after the seventh temporary data are left-shifted. For example, after the qout _ fix (i.e., the seventh temporary data) is shifted to the left by RP × 8 bits, the resultant is assigned to the output line bus _ wdata of the internal bus, and the data sent to the internal bus is generated.

According to the embodiment of the invention, by acquiring the data length of write/read operation, the initial position information of the first effective byte data of the write/read operation on an internal bus, and the data operation pointers of the write/read operation on a plurality of dual-port RAMs, generating and recording the next data operation pointer according to the data length of the write/read operation and the recorded data operation pointers, generating the in-block position identification of the write/read operation on each dual-port RAM according to the data length of the write/read operation and the data operation pointers, selecting the byte data of the write operation for each dual-port RAM on the internal bus according to the operation position information and the initial position information of the write operation, writing the selected byte data into the corresponding dual-port RAM according to the operation position information of the write operation, and according to the operation position information and the initial position information of the read operation, and rearranging byte data of the read operation of the multiple dual-port RAMs according to the output sequence of the internal bus, and reading the arranged byte data to the internal bus according to the initial position information of the read operation, so that the limitation that a source address and a destination address of a DMA controller need to be aligned is avoided, no trigger is added, the chip area occupied by the trigger is reduced, when the source address and the destination address are not aligned, the data does not need to be shifted through the trigger, and the delay of reading the data from a dual-port RAM read port to the internal bus is reduced.

It should be noted that, for simplicity of description, the method embodiments are described as a series of acts or combination of acts, but those skilled in the art will recognize that the present invention is not limited by the illustrated order of acts, as some steps may occur in other orders or concurrently in accordance with the embodiments of the present invention. Further, those skilled in the art will appreciate that the embodiments described in the specification are presently preferred and that no particular act is required to implement the invention.

Referring to fig. 3, a block diagram of a data buffering apparatus according to a third embodiment of the present invention is shown, and specifically includes the following modules:

a length obtaining module 301, configured to obtain a data length of a write/read operation;

a start information obtaining module 302, configured to obtain start position information corresponding to first valid byte data on an internal bus for write/read operation;

an operation information obtaining module 303, configured to obtain a data operation pointer corresponding to a write/read operation on multiple dual-port RAMs, where the dual-port RAM stores one byte of data at a time, and the number of blocks of the dual-port RAM is the same as the maximum number of byte data transmitted by the internal bus at a time;

an information determining module 304, configured to determine, according to the data length of the write/read operation and the data operation pointer, operation position information of the write/read operation on the multi-block dual port RAM;

an operation module 305, configured to rearrange the corresponding byte data of the multiple dual port RAMs according to the operation location information and the start location information of the write/read operation, and perform a write/read operation of data buffering.

In a preferred embodiment of the present invention, the apparatus further comprises:

In a preferred embodiment of the present invention, the operation position information includes an intra-block position identifier in the dual port RAM, and the information determination module includes:

In a preferred embodiment of the present invention, the data operation pointer includes a block identifier of the dual port RAM and an intra-block location identifier in the dual port RAM, and the identifier generation submodule includes:

In a preferred embodiment of the present invention, the signal determination unit includes:

In a preferred embodiment of the present invention, the operation module includes:

In a preferred embodiment of the present invention, the selecting sub-module includes:

the write submodule includes:

In a preferred embodiment of the present invention, the permutation submodule includes:

the reading sub-module includes:

According to the embodiment of the invention, by acquiring the data length of the write/read operation, the initial position information of the first effective byte data on the internal bus of the write/read operation and the data operation pointer of the write/read operation on the plurality of dual-port RAMs, determining the operation position information of the write/read operation on the plurality of dual-port RAMs according to the data length of the write/read operation and the data operation pointer of the write/read operation, rearranging the corresponding byte data of the plurality of dual-port RAMs according to the operation position information and the initial position information of the write/read operation, and executing the write/read operation of data buffering, the limitation that the source address and the destination address of a DMA controller need to be aligned is avoided, and no trigger is added, so that the chip area occupied by adding the trigger is reduced, when the source address and the destination address are not aligned, the data is shifted without passing through a flip-flop, which in turn reduces the delay of reading data from the dual port RAM read port to the internal bus.

For the device embodiment, since it is basically similar to the method embodiment, the description is simple, and for the relevant points, refer to the partial description of the method embodiment.

The embodiments in the present specification are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.

As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, apparatus, or computer program product. Accordingly, embodiments of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, embodiments of the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

Embodiments of the present invention are described with reference to flowchart illustrations and/or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing terminal to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing terminal to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing terminal to cause a series of operational steps to be performed on the computer or other programmable terminal to produce a computer implemented process such that the instructions which execute on the computer or other programmable terminal provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

While preferred embodiments of the present invention have been described, additional variations and modifications of these embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the embodiments of the invention.

Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or terminal that comprises the element.

The data buffering method and the data buffering device provided by the present invention are described in detail above, and the principle and the implementation of the present invention are explained in this document by applying specific examples, and the description of the above examples is only used to help understanding the method and the core idea of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.

Claims

1. A method of buffering data, comprising:

acquiring the data length of the write/read operation;

2. The method of claim 1, further comprising:

3. The method of claim 1, wherein the operation location information comprises an intra-block location identifier in a dual port RAM, and wherein determining the operation location information on the multi-block dual port RAM based on the data length and the data operation pointer of the write/read operation comprises:

4. The method of claim 3, wherein the data operation pointer comprises a block identifier of the dual port RAM and an intra-block location identifier in the dual port RAM, and wherein generating the intra-block location identifier for the write operation on each block of the dual port RAM based on the data length of the write operation and the data operation pointer comprises:

5. The method of claim 4, wherein determining the enable signal for the write operation on each block dual port RAM based on the data length of the write operation and the block identification of the first dual port RAM comprises:

6. The method of claim 3, wherein the data operation pointers comprise block identifiers of the dual port RAM and intra-block location identifiers in the dual port RAM, and wherein generating the intra-block location identifiers for read operations on each block of the dual port RAM based on the data length of the read operations and the data operation pointers comprises:

7. The method according to any one of claims 1 to 6, wherein the rearranging byte data corresponding to the plurality of dual port RAMs according to the operation position information and the start position information of the write operation and performing the write operation of data buffering comprises:

8. The method of claim 7, wherein selecting byte data of the write operation for each dual port RAM on the internal bus according to the operation location information and the start location information of the write operation comprises:

9. The method according to any of claims 1-6, wherein the rearranging the corresponding byte data of the plurality of dual port RAMs according to the operation position information and the start position information of the read operation, and performing the read operation of the data buffer comprises:

10. The method of claim 9, wherein the rearranging the byte data read from the multi-block dual port RAM in the output order of the internal bus based on the operation position information and the start position information of the read operation comprises:

11. A data buffering device, comprising:

12. The apparatus of claim 11, further comprising:

13. The apparatus of claim 11, wherein the operation location information comprises an intra-block location identifier in a dual port RAM, and wherein the information determining module comprises:

14. The apparatus of claim 13, wherein the data operation pointer comprises an identification of a block of the dual port RAM and an identification of a location within the block of the dual port RAM, and wherein the identification generation submodule comprises:

15. The apparatus of claim 14, wherein the signal determination unit comprises:

16. The apparatus of claim 13, wherein the data operation pointer comprises an identification of a block of the dual port RAM and an identification of a location within the block of the dual port RAM, and wherein the identification generation submodule comprises:

17. The apparatus according to any one of claims 11-16, wherein the operation module comprises:

18. The apparatus of claim 17, wherein the selecting sub-module comprises:

the write submodule includes:

19. The apparatus according to any one of claims 11-16, wherein the operation module comprises:

20. The apparatus of claim 19, wherein the permutation submodule comprises:

the reading sub-module includes: