CN112328522B

CN112328522B - Data processing method and device

Info

Publication number: CN112328522B
Application number: CN202011355821.9A
Authority: CN
Inventors: 李为良
Original assignee: Beijing Runke General Technology Co Ltd
Current assignee: Beijing Runke General Technology Co Ltd
Priority date: 2020-11-26
Filing date: 2020-11-26
Publication date: 2023-05-26
Anticipated expiration: 2040-11-26
Also published as: CN112328522A

Abstract

The embodiment of the invention discloses a data processing method and a data processing device, which are used for storing at least two original data, wherein each original data is stored in a plurality of RAMs (namely RAM groups) in a distributed manner, so that when the data covered by a sliding window occupy a plurality of address units, different parts of the data covered by the sliding window can be simultaneously read from the plurality of RAM groups, and the parallel reading of the data of the sliding window in one reading clock period is realized, thereby improving the data processing efficiency of an embedded system.

Description

Data processing method and device

Technical Field

The present invention relates to the field of data processing technologies, and in particular, to a data processing method and apparatus.

Background

When the embedded system processes data, the general flow is to read data from a memory, send the read data to a computing unit to complete specific operation, and finally output a computing result. When the existing embedded system reads data, the data in one address can be read in sequence in each clock period, the processing mode makes the data read speed slower, and particularly a data processing algorithm with the sliding window extraction processing requirement possibly appears that the data in one sliding window needs to be read in a plurality of clock periods, and the data in the sliding window cannot be obtained efficiently, so that the real-time performance of data processing cannot meet the requirement of high-speed processing.

Therefore, how to improve the data processing efficiency of the embedded system is a technical problem to be solved.

Disclosure of Invention

The invention aims to provide a data processing method and a data processing device so as to improve the data processing efficiency of an embedded system. The method comprises the following technical scheme:

a data processing method, comprising:

dividing the original data into input data with the same length, numbering according to the sequence, and determining a write address line according to the pre-configuration information and the sequence number of the input data in each write clock period; the pre-configuration information includes: the number of RAMs in each RAM group, the width of the write address line of the RAMs, and the width of the write port data bit and the read port data bit of the RAMs; the number of the RAM groups is determined according to the bit width of the sliding window data, the number of the RAMs included in each RAM group, and the write port data bit width and the read port data bit width of the RAMs; or, the number of RAMs included in each RAM group, the write port data bit width and the read port data bit width of the RAMs are determined according to the number of the RAM groups and the bit width of the sliding window data;

determining a write RAM according to the input data sequence number, the number of RAMs in each RAM group, the write port data bit width and the read port data bit width of the RAMs, and writing the input data corresponding to the input data sequence number into the write RAM according to the determined write address line and the write RAM;

After all input data are written, when the data need to be read, determining the serial number of the sliding window in each reading clock period;

determining a read address line corresponding to the sliding window sequence number according to the input data sequence number corresponding to the sliding window sequence number, the read port data bit width and the write port data bit width of the RAM and the number of the RAMs in each RAM group;

reading storage data from a storage position corresponding to the determined read address line; when the number of the determined read address lines is greater than one, reading the storage data in the storage positions corresponding to the different read address lines in different RAM groups;

extracting corresponding sliding window data from the read storage data according to the input data sequence number corresponding to the sliding window sequence number, the read port data bit width and the write port data bit width of the RAMs, the number of RAMs in each RAM group and the determined read address line; when the number of the determined read address lines is greater than one, each part of the sliding window data is extracted from the storage data read in different RAM groups to be spliced, so that corresponding sliding window data is obtained.

The method, optionally, the determining the write address line according to the preconfiguration information and the input data sequence number includes:

The write address line is determined according to the following formula:

wr_addr＝{wr_data_num[addr_A_width-1:log2(M)+log2(lenB/lenA)],wr_data_num[log2(lenB/lenA)-1:0]}

wherein wr_addr represents the write address line; wrdatanum is the input data sequence number; lenA is the write port data bit width of RAM; lenB is the read port data bit width of RAM; m is the number of RAMs in each RAM group;

wrdatanum [ addr_a_width-1:log2 (M) +log2 (lenB/lenA) ] represents the upper bits of the write address line, taking the data of addr_a_width-1 bit of wrdatanum to the log2 (M) +log2 (lenB/lenA) bit; wrdata num [ log2 (lenB/lenA) -1:0] represents the lower bit of the write address line, and takes the data from log2 (lenB/lenA) -1 bit to 0 bit of wrdata num; addr_A_width is the write address line width of the RAM.

The method, optionally, the number of the RAM groups is determined according to the bit width of the sliding window data, the number of the RAMs included in each RAM group, and the write port data bit width and the read port data bit width of the RAMs, including:

determining the number of the RAM groups according to the following formula:

R≥(P-lenA+lenB)/(M×lenB)

wherein R represents the number of the RAM groups; lenA is the write port data bit width of RAM; lenB is the read port data bit width of RAM; m is the number of RAMs in each RAM group, and P represents the bit width of the sliding window data.

The method, optionally, determines the write RAM according to the input data sequence number, the number of RAMs in each RAM group, and the write port data bit width and the read port data bit width of each RAM, including:

Determining the write RAM according to the following formula:

wherein, RAM_num represents the sequence number of the write RAM;

we_v=1 indicates that the write port to be written to RAM is enabled;

wrdatanum [ log2 (M) +log2 (lenB/lenA) -1:log2 (lenB/lenA) ] represents data taking log2 (M) +log2 (lenB/lenA) -1 bit to log2 (lenB/lenA) bit of wrdatanum; wrdatanum represents an input data sequence number; lenA is the RAM write port data bit width; lenB is the read port data bit width of RAM; m is the number of RAMs in each RAM group.

The method, optionally, writes the input data corresponding to the input data sequence number according to the determined write address line and the write RAM, including:

determining the writing position of input data corresponding to the input data sequence number in a writing RAM according to the writing address line; the sequence of each data in the input data corresponding to the input data serial numbers is matched and written according to the position sequence of the RAM in each RAM group.

According to the method, optionally, the determining the read address line corresponding to the sliding window sequence number according to the input data sequence number corresponding to the sliding window sequence number, the read port data bit width and the write port data bit width of the RAM, and the number of the RAMs in each RAM group includes:

and determining a read address line corresponding to the serial number of the sliding window according to the following formula:

rd_B_addr＝floor(rd_data_num/(lenB/lenA×M))

Wherein rd_B_addr represents a read address line corresponding to the sliding window sequence number, and rd_data_num represents any one of the input data sequence numbers corresponding to the sliding window sequence number; lenA is the write port data bit width of RAM; lenB is the read port data bit width of RAM; m is the number of RAMs in each RAM group; floor means rounded down.

According to the method, optionally, the extracting corresponding sliding window data from the read stored data according to the input data sequence number corresponding to the sliding window sequence number, the read port data bit width and the write port data bit width of the RAM, the number of the RAMs in each RAM group and the determined read address line includes:

for any one of the input data sequence numbers corresponding to the sliding window sequence numbers, determining a read RAM according to the input data sequence number, the read port data bit width and the write port data bit width of the RAM, the number of RAMs in each RAM group and the read address line determined based on the input data sequence number;

determining a specific position of input data corresponding to the input data sequence number in a storage position corresponding to a read address line according to the input data sequence number, the read port data bit width and the write port data bit width of the RAM and the number of the RAMs in each RAM group based on the read address line and the read RAMs determined by the input data sequence number;

And extracting corresponding sliding window data from the read storage data according to the determined read RAM and the determined specific position.

The method, optionally, the process of determining the read RAM includes: the read RAM is determined according to the following formula:

k＝floor((rd_data_num-rd_B_addr×M×lenB/lenA)/(lenB/lenA))

wherein k represents the serial number of the read RAM corresponding to the input data serial number; rd_b_addr represents a read address line determined based on the input data sequence number, and rd_data_num represents the input data sequence number; lenA is the write port data bit width of RAM; lenB is the read port data bit width of RAM; m is the number of RAMs in each RAM group; floor means rounded down.

In the above method, optionally, the determining the specific location of the input data corresponding to the input data sequence number in the storage location corresponding to the read address line includes: determining a specific position of the input data corresponding to the input data sequence number in a storage position corresponding to the read address line according to the following formula:

w＝rd_data_num-rd_B_addr×M×lenB/lenA-k×lenB/lenA

wherein w represents a specific position of the input data corresponding to the input data sequence number in a storage position corresponding to the read address line; k represents the serial number of the read RAM corresponding to the input data serial number; rd_b_addr represents a read address line determined based on the input data sequence number, and rd_data_num represents the input data sequence number; lenA is the write port data bit width of RAM; lenB is the read port data bit width of RAM; m is the number of RAMs in each RAM group.

A data processing apparatus comprising:

the write address line determining module is used for dividing the original data into input data with the same length, numbering the input data in sequence, and determining a write address line according to the preset information and the sequence number of the input data in each write clock period; the pre-configuration information includes: the number of RAMs in each RAM group, the width of the write address line of the RAMs, and the width of the write port data bit and the read port data bit of the RAMs; the number of the RAM groups is determined according to the bit width of the sliding window data, the number of the RAMs included in each RAM group, and the write port data bit width and the read port data bit width of the RAMs; or, the number of RAMs included in each RAM group, the write port data bit width and the read port data bit width of the RAMs are determined according to the number of the RAM groups and the bit width of the sliding window data;

the data writing module is used for determining a data writing RAM according to the input data sequence number, the number of RAMs in each RAM group, the writing port data bit width and the reading port data bit width of each RAM, and writing the input data corresponding to the input data sequence number into the data writing RAM according to the determined writing address line and the determined writing RAM;

the serial number determining module is used for determining the serial number of the sliding window in each reading clock period when the data need to be read after all the input data are written;

The read address line determining module is used for determining the read address line corresponding to the serial number of the sliding window according to the input data serial number corresponding to the serial number of the sliding window, the read port data bit width and the write port data bit width of the RAM and the number of the RAMs in each RAM group;

the read data module is used for reading the stored data from the storage position corresponding to the determined read address line; when the number of the determined read address lines is greater than one, reading the storage data in the storage positions corresponding to the different read address lines in different RAM groups;

the data extraction module is used for extracting corresponding sliding window data from the read storage data according to the input data sequence number corresponding to the sliding window sequence number, the read port data bit width and the write port data bit width of the RAMs, the number of the RAMs in each RAM group and the determined read address line; when the number of the determined read address lines is greater than one, each part of the sliding window data is extracted from the storage data read in different RAM groups to be spliced, so that corresponding sliding window data is obtained.

According to the scheme, when data is stored, the original data is divided into input data with the same length, the input data are numbered sequentially, and in each write clock period, a write address line is determined according to preset information (comprising the number of RAMs in each RAM group, the write address line width of the RAMs, the write port data bit width and the read port data bit width of the RAMs, the number of the RAMs is determined according to the bit width of sliding window data, the number of RAMs in each RAM group and the write port data bit width and the read port data bit width of the RAMs, or the number of RAMs in each RAM group, the write port data bit width and the read port data bit width of the RAMs are determined according to the number of the RAMs and the bit width of sliding window data) and the input data sequence number; determining a write RAM according to the input data sequence number, the number of RAMs in each RAM group, the write port data bit width and the read port data bit width of each RAM, and writing the input data corresponding to the input data sequence number into the write RAM according to the determined write address line and the write RAM; after all input data are written, when the data need to be read, determining the serial number of the sliding window in each reading clock period; determining a read address line corresponding to the sliding window sequence number according to the input data sequence number corresponding to the sliding window sequence number, the read port data bit width and the write port data bit width of the RAM and the number of the RAMs in each RAM group; reading storage data from a storage position corresponding to the determined read address line; when the number of the determined read address lines is greater than one, reading the storage data in the storage positions corresponding to the different read address lines in different RAM groups; extracting corresponding sliding window data from the read storage data according to the input data sequence number corresponding to the sliding window sequence number, the read port data bit width and the write port data bit width of the RAMs, the number of RAMs in each RAM group and the determined read address line; when the number of the determined read address lines is greater than one, all parts of the sliding window data extracted from the storage data read in different RAM groups are spliced to obtain corresponding sliding window data. By improving the writing mode and the reading mode of the data, the invention can read all the data in the sliding window in one reading clock period, and realize the parallel reading of the data in the sliding window, thereby improving the data processing efficiency of the embedded system.

Drawings

In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a flow chart of one implementation of writing data provided by an embodiment of the present invention;

FIG. 2 is a flowchart of one implementation of reading data in a sliding window during each read clock cycle according to an embodiment of the present invention;

FIG. 3 is a diagram showing an exemplary structure of a RAM set according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of a data processing apparatus according to an embodiment of the present invention;

fig. 5 is a block diagram of a hardware structure of an electronic device according to an embodiment of the present invention.

The terms "first," "second," "third," "fourth" and the like in the description and in the claims and in the above drawings, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in other sequences than those illustrated herein.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without any inventive effort, are intended to be within the scope of the invention.

The data processing method provided by the embodiment of the invention is applied to an embedded system, and the embedded system can be an embedded system realized based on a Field programmable gate array (Field-Programmable Gate Array, FPGA).

For a clear understanding of the present invention, the inventive concept of the present invention will be described first, with the inventive concept being: by improving the writing mode and the reading mode of the data, the aim of reading all the data in the sliding window in one reading clock period is fulfilled, and the parallel reading of the sliding window data is realized, so that the data processing efficiency of the embedded system is improved.

In the embodiment of the present invention, for convenience of description, data to be processed is recorded as original data, where the original data may be image data, text data, or other data to be processed, such as video data, or audio data.

In an embodiment of the present invention, the original data is stored in at least two shares, each stored in one RAM (random access memory) group. Wherein, the liquid crystal display device comprises a liquid crystal display device,

each RAM group comprises M (M is an integer greater than 1) RAMs, and the numbers of the RAMs in different RAM groups are the same; each RAM comprises K address units, and the numbers of the address units in different RAM groups are the same; each address unit comprises N sub-address units, the sub-address units in each RAM are independently numbered in each RAM group, the numbers of the sub-address units in different RAM groups are the same, and the bit widths of the sub-address units are the same.

The write port data bit width of each RAM is the bit width of a sub-address unit, based on which, for each RAM, when writing data in the RAM, data can only be written in one sub-address unit of the RAM in each write clock cycle, the write port data bit widths of the respective RAMs being the same; the read port data bit width of each RAM is the bit width of an address unit, based on which, for each RAM, when reading data from the RAM bank, data can only be read from one address unit of the RAM in each read clock cycle, the read port data bit widths of the respective RAMs being the same.

In this embodiment of the present application, the number of RAM banks (denoted as R for convenience of description) may be determined according to the bit width of the sliding window (i.e., the bit width of the sliding window data, denoted as P for convenience of description), the number of RAMs M included in each RAM bank, and the write port data bit width (denoted as lenA for convenience of description) and the read port data bit width (denoted as lenB for convenience of description) of the RAMs. The number of RAM banks R may be determined based on the following relationship:

(P/lenA)≤[R×M×(lenB/lenA)-lenB/lenA+1] (1)

namely: r is not less than (P-lenA+lenB)/(M.times.lenB) (2)

In the embodiment of the present invention, the value of R may be the smallest integer value satisfying the above relationship. The present invention is directed to a scenario in which data processing is performed based on a sliding window, and therefore the bit width P of the sliding window is known.

In another alternative embodiment, the number of RAM banks may be determined first, and then RAM is selected to construct the RAM banks according to the number of RAM banks, the bit width of the sliding window data, and equation (1) or equation (2), that is, the number of RAM banks, the bit width of the write port data and the bit width of the read port data included in each RAM bank are determined based on equation (1) or equation (2) according to the number of RAM banks, the bit width of the sliding window data.

It should be noted that, in general, the manner in which data is presented to the user is different from the manner in which data is stored in the memory. Taking image data as an example, the image data is presented to a user in a pixel manner, the relative position relationship among the pixels is a first relative position relationship, when the image data is stored, the numerical value corresponding to each pixel is stored, and the relative position relationship among the pixels is no longer the first relative position relationship, that is, for the image data, the original data refers to the numerical value corresponding to the pixels which are required to be stored in the memory, not the pixels themselves. Therefore, in a scenario where data is extracted using a sliding window, it is necessary to convert the user-side sliding window (for determining the data extraction range in the data presented to the user) into a background-side sliding window (for determining the data extraction range in the memory), and to convert the movement step size of the user-side sliding window into the movement step size of the background-side sliding window. How to transform can be seen in particular with respect to existing transformation methods, which are not of interest for the present invention and will therefore not be described in detail here. Based on this, the sliding window in the embodiment of the present invention refers to a background sliding window unless otherwise specified. The serial number of the background side sliding window is the same as the serial number of the corresponding user side sliding window.

A specific implementation of writing the original data into the RAM bank is described below. Since the composition of the respective RAM banks is the same, the original data is written to the respective RAM banks in the same manner. Referring to fig. 1, fig. 1 is a flowchart of an implementation of writing data according to an embodiment of the present invention, which may include:

step S11: the original data is divided into input data with the same length and numbered in sequence.

As can be seen from the foregoing description, the bit width of the write port data of each RAM is the bit width of a sub-address unit, and when writing data in the RAM, data can be written in only one sub-address unit in each write clock cycle, based on which the length of the input data can be the bit width of the write port data of the RAM, that is, the bit width of one sub-address unit.

The length of the input data is generally different from the bit width of the sliding window, and in general, the bit width of the sliding window is greater than the length of the input data, but the present invention is not limited thereto, i.e., the bit width of the sliding window may be less than or equal to the length of the input data.

Step S12: determining a write address line according to the pre-configuration information and the input data sequence number in each write clock period; the pre-configuration information includes: the number of RAMs in each RAM set, M, the write address line width of the RAM (addr_A_width for ease of description), and the write port data bit width lenA and read port data bit width lenB of the RAM; the number R of the RAM groups is determined according to the bit width of the sliding window data, the number M of the RAMs included in each RAM group, and the write port data bit width lenA and the read port data bit width lenB of the RAMs; alternatively, the write port data bit width lenA and the read port data bit width lenB of the RAM number M, RAM included in each RAM group are determined according to the RAM group number R and the bit width of the sliding window data.

Each write address line corresponds to a write address, and different write address lines correspond to different write addresses. Wherein one write address line has one sub-address unit corresponding to it in each RAM.

In the embodiment of the invention, the write address lines of the input data with continuous serial numbers can be continuous or discontinuous, and the write address lines are determined according to actual scenes.

For example, in a certain RAM, a storage location corresponding to a first write address line of a 0 th address unit (i.e., a sub-address unit corresponding to the first write address line) may be written first, a storage location corresponding to a second write address line of the 0 th address unit (i.e., a sub-address unit corresponding to the second write address line) may be written, a storage location corresponding to a third write address line of the 0 th address unit (i.e., a sub-address unit corresponding to the third write address line) may be written, and so on until the 0 th address unit of the RAM is written. Then the 0 th address unit in the next RAM is written in the next RAM according to the same rule, and so on until the 0 th address unit of all the RAMs is written. Then writing in the 1 st address unit in the 0 st RAM according to the same rule until all input data are written into the RAM group.

Alternatively, in a certain RAM, the storage location corresponding to the first write address line of the 0 th address unit may be written first, the storage location corresponding to the third write address line of the 0 th address unit may be rewritten, the storage location corresponding to the fifth write address line of the 0 th address unit may be rewritten, and so on until the 0 th address unit of the RAM is written. Then the 0 th address unit of the RAM is written in the next RAM according to the same rule, and so on until the 0 th address unit of all the RAMs is written. Then, writing in the 1 st address unit in the 0 st RAM according to the same rule until all input data are written into the RAM group. In a specific application scenario, for example, it is desired to process image data of two images simultaneously (where the image data of each image is raw data of an image), image data of one image is stored in a sub-address unit corresponding to a single write address line, and image data of the other image is stored in a sub-address unit corresponding to a double write address line.

According to different practical application scenes, the writing address lines of the input data with continuous serial numbers can be continuous or discontinuous, and based on the fact, according to different practical application scenes, the specific implementation mode of determining the writing address lines according to the preset information and the input data serial numbers is different in each writing clock period.

Step S13: determining a write RAM according to the input data sequence number, the number of RAMs in each RAM group, the write port data bit width and the read port data bit width of the RAMs, and writing the input data corresponding to the input data sequence number into the write RAM according to the determined write address line and the write RAM.

The data bit width of the write port of the RAM is the data bit width of the write port of each RAM, and the data bit width of the read port of the RAM is the data bit width of the read port of each RAM.

According to different practical application scenes, the writing address lines of the input data with continuous serial numbers can be continuous or discontinuous, and based on the fact that the specific implementation mode of determining the writing RAM according to the input data serial numbers, the number of RAMs in each RAM group, the writing port data bit width and the reading port data bit width of the RAMs are different according to the different practical application scenes.

Regardless of the actual application scenario, after the write address line and the write RAM are determined, when the input data corresponding to the input data sequence number is written according to the determined write address line and the write RAM, the input data corresponding to the input data sequence number is written into the write RAM. In one embodiment, a write location of input data corresponding to the input data sequence number in the write RAM is determined based on the write address line. The sequence of each data in the input data corresponding to the input data sequence number is matched and written according to the position sequence of the RAM in each RAM group.

In the embodiment of the invention, no matter whether the writing address lines of the input data with continuous serial numbers are continuous or discontinuous, when the input data is written into the RAM group, the writing is sequentially carried out according to the position sequence of the RAMs in the RAM group, for example, the 0 th address unit of the 0 th RAM is written firstly, the 0 th address unit of the 1 st RAM is rewritten after the 0 th address unit of the 0 th RAM is written, the 0 th address unit of the 2 nd RAM is rewritten after the 0 th address unit of the 1 st RAM is written, and so on until the 0 th address unit of all RAMs in the RAM group is written, then the 1 st address unit of the 0 th RAM is rewritten, the 1 st address unit of the 1 st RAM is rewritten after the 1 st address unit of the 0 th RAM is written, the 1 st address unit of the 2 nd RAM is rewritten, and so on until all the input data is written into the RAM group.

Because the modes of writing data of the RAM groups are the same, when the input data corresponding to the input data serial numbers are written according to the determined writing address line and the writing RAM, the RAM groups can be written simultaneously.

After writing all the input data, when the data needs to be read, in each read clock cycle, an implementation flowchart of reading the data in the sliding window is shown in fig. 2, and may include:

Step S21: and determining the serial number of the sliding window.

In an actual application scene, the sliding window moves according to a certain step length, so that the number of the sliding window is increased by 1 every time the sliding window moves according to the step length, and the number of the sliding window can be recorded in the moving process of the sliding window. Wherein, in each reading clock period, the corresponding sliding window sequence number can be determined according to the requirement.

Step S22: and determining a read address line corresponding to the sliding window sequence number according to the input data sequence number corresponding to the sliding window sequence number, the read port data bit width and the write port data bit width of the RAM and the number of the RAMs in each RAM group.

The input data sequence number corresponding to the sliding window sequence number can be determined according to the sliding window sequence number, the bit width of the sliding window, the moving step length of the sliding window and the length of the input data. The detailed description will refer to the prior art, and since it is not the focus of the present invention, it will not be described in detail here.

Since one sliding window normally covers a plurality of input data, the input data number corresponding to the sliding window number refers to the number of each input data corresponding to the sliding window number. Determining the read address line corresponding to the sliding window sequence number refers to determining the address line corresponding to the address unit where the input data corresponding to the sliding window sequence number is located.

Step S23: reading storage data from a storage position corresponding to the determined read address line; and when the number of the determined read address lines is greater than one, reading the storage data in the storage positions corresponding to the different read address lines in different RAM groups.

Depending on the bit width of the sliding window, the bit width of the address unit of the RAM, and the position of the sliding window, the data to be read corresponding to the sliding window sequence number may be located in only one address unit or may be located in two or more address units during the sliding of the sliding window. When the data to be read corresponding to the sliding window sequence number is located in only one address unit, the determined read address lines are only one, and when the data to be read corresponding to the sliding window sequence number is located in L (L is an integer larger than 1) address units, the determined read address lines are L.

In the embodiment of the invention, when the number of the determined read address lines is greater than one, the stored data in the storage positions corresponding to the different read address lines are read in different RAM groups.

For example, if the number of the determined read address lines is 2 (the first read address line and the second read address line respectively), the stored data in the storage location corresponding to the first read address line may be read in the first RAM bank, and the stored data in the storage location corresponding to the second read address line may be read in the second RAM bank.

If the number of the read address lines is 3 (the first read address line, the second read address line and the third read address line respectively), the stored data in the storage position corresponding to the first read address line can be read in the first RAM bank, the stored data in the storage position corresponding to the second read address line can be read in the second RAM bank, and the stored data in the storage position corresponding to the third read address line can be read in the third RAM bank.

Step S24: extracting corresponding sliding window data from the read storage data according to the input data sequence number corresponding to the sliding window sequence number, the read port data bit width and the write port data bit width of the RAMs, the number of RAMs in each RAM group and the determined read address line; when the number of the determined read address lines is greater than one, all parts of the sliding window data extracted from the storage data read in different RAM groups are spliced to obtain corresponding sliding window data.

For each read address line determined, the data to be read corresponding to the sliding window serial number may occupy the address unit corresponding to the read address line, or may not occupy the address unit corresponding to the read address line, so that sliding window data (i.e. data covered by the sliding window) needs to be extracted from the read storage data, and when the number of the determined read address lines is greater than one, each part of the sliding window data extracted from the storage data read in different RAM groups needs to be spliced to obtain corresponding sliding window data.

According to the data processing method provided by the embodiment of the invention, at least two original data are stored, each original data are stored in a plurality of RAMs (namely RAM groups) in a distributed mode, so that when the data covered by the sliding window occupy a plurality of address units, different parts of the data covered by the sliding window can be read from the plurality of RAM groups at the same time, parallel reading of the data of the sliding window in one reading clock period is realized, and the data processing efficiency of the embedded system is improved.

The present inventors have studied and found that when the number of RAM banks is large, the logic to be considered in implementing the scheme of the present invention is complex, requiring a technician to pay more effort and consume a long development time, resulting in a high development cost. In order to simplify the logic to be considered in the design and reduce the development cost, the invention sets the number R of the RAM groups to 2, and based on the number R, the RAMs used for constructing the RAM groups can be selected according to the relation (3). The relation (3) is:

namely: 2. not less than (P-lenA+lenB)/(M.times.lenB) (3)

As shown in fig. 3, an exemplary diagram of a structure of a RAM bank according to an embodiment of the present invention is provided, where each RAM bank includes 4 RAMs, each RAM includes 8 address units (one address unit in each RAM), and each address unit includes 8 sub-address units. The RAM bank includes a total of 4×8×8=256 sub-address units.

In the example shown in fig. 3, when input data is written into the RAM group, the writing address lines of continuous input data are continuous, after the 0 th address unit of each RAM is written into the RAM in sequence from small to large, the 1 st address unit of each RAM is written into the RAM in sequence, after the 1 st address unit of each RAM is written into the RAM group, the 2 nd address unit of each RAM is written into the RAM group in sequence, and so on until all input data are written into the RAM group. According to this writing method, 8 consecutive input data are stored in each address unit, and the serial number difference of the input data located in the same column in two adjacent address units of each RAM is mxn=4×8=32. In fig. 3, each cell represents a sub-address unit, and the numbers in the cells represent the number of the input data, i.e. the number of the input data stored in each cell. For example, the square at 000 stores the 0 th input data, the square at 006 stores the 6 th input data, the square at 021 stores the 21 st input data, and the square at 153 stores the 153 th input data.

The following describes a specific implementation of the inventive solution based on the case of two RAM banks (i.e. r=2).

In an alternative embodiment, one implementation of determining the write address line according to the pre-configuration information and the input data sequence number may be that the write address line is determined according to the following formula (4):

The width of the write address line of the RAM may be determined according to the following relationship:

addr_A_width≥log2(NUM) (5)

NUM is the number of sub-address units in RAM.

Specifically, addr_a_width may be the smallest integer value satisfying the above relation (5).

Taking the input data stored in the RAM bank shown in fig. 3 as an example, in this example, the original data is divided into 256 input data of the same length, addr_a_width is equal to or greater than log2 (256) =8, and based on this, addr_a_width=8, assuming that lenb=64, lena=8, and m=4, then:

wr_addr＝{wr_data_num[8-1:log2(4)+log2(64/8)],wr_data_num[log2(64/8)-1:0]}

＝{wr_data_num[7:5],wr_data_num[2:0]}

For example, taking the 50 th input data (i.e., input data sequence number 50), the binary representation of 50 is: 00110010, bits 7 to 5 and bits 2 to 0 of the binary number are 001 and 010, then the write address line determined based on the input data sequence number 50 is wr_addr=001010=10, and it can be seen from fig. 3 that the 50 th input data is located in the 10 th sub-address unit of the 2 nd RAM (i.e., RAM 2) (note that the numbering of the sub-address units is in order from left to right, from top to bottom, and all the codes are from 0).

For another example, taking the 121 th input data (that is, the input data sequence number 121), the binary representation of 121 is: 01111001, bits 7 to 5 and bits 2 to 0 of the binary number are 011, and then the write address line determined based on the input data sequence number 121 is wr_addr=012001=25, as can be seen from fig. 3, the 121 th input is located in the 25 th sub-address unit of the 3 rd RAM (i.e., RAM 3) (note that the numbering of the sub-address units is in order from left to right, from top to bottom, and all codes are from 0).

Obviously, only the write address line is determined, and the specific writing position of the input data cannot be determined, and the specific writing RAM is also required to be determined to determine the specific writing position of the input data. In an alternative embodiment, an implementation of determining the write RAM according to the input data sequence number, the number of RAMs in each RAM bank, and the write port data bit width and the read port data bit width of each RAM may be:

Determining the write RAM according to the following formula (6):

wherein, RAM_num represents the sequence number of the write RAM;

we_v=1 indicates that the write port to be written to RAM is enabled;

Taking the input data stored in the RAM bank shown in fig. 3 as an example, assuming that lenb=64, lena=8, m=4, then:

for example, taking the 50 th input data as an example, the binary representation of 50 is: 00110010, bits 4 to 3 of the binary number are 10, i.e., ram_num=2, that is, the write RAM corresponding to the input data sequence number 50 determined based on the formula (6) is 2 nd RAM (i.e., RAM 2).

For another example, taking the 121 th input data as an example, the binary representation of 121 is: 01111001, bits 4 to 3 of the binary number are 11, i.e., ram_num=3, that is, the write RAM corresponding to the input data number 121 determined based on the formula (6) is 3 rd RAM (i.e., RAM 3).

In summary, for each RAM bank, in the embodiment of the present invention, the write ports of M RAMs in the RAM bank are enabled by polling, and each time the write port of one RAM is enabled, the RAM is used as a target RAM, N input data are continuously written in an address unit of the target RAM, and when the address unit is full, the target RAM is controlled to be disabled until all the input data are stored in the RAM bank. The plurality of RAM banks may write the input data at the same time, that is, after determining the write address line corresponding to the input data and the write RAM, the input data may be written into the sub-address unit corresponding to the write address line of the write RAM in each RAM bank.

After writing all input data, when the data needs to be read, in each read clock cycle, one implementation manner of determining the read address line corresponding to the sliding window sequence number according to the input data sequence number corresponding to the sliding window sequence number, the read port data bit width and the write port data bit width of the RAM, and the number of RAMs in each RAM group may be:

determining a read address line corresponding to the sliding window sequence number according to the following formula (7):

rd_B_addr＝floor(rd_data_num/(lenB/lenA×M)) (7)

For example, taking the 149 th input data (i.e. the input data sequence number is 149), based on the input data sequence number 149, the read address line corresponding to the sliding window sequence number is determined by the above formula (7):

rd_B_addr＝floor(149/(64/8×4))＝floor(4.7)＝4

i.e. the 149 th input data is located at the 4 th address unit. Specifically which address location 4 in RAM can be determined by the subsequent content.

Since there are a plurality of input data sequence numbers corresponding to the sliding window sequence numbers, a read address line corresponding to the sliding window sequence number can be determined based on each input data sequence number, and the read address lines corresponding to the sliding windows determined based on different input data sequence numbers may be the same or different. In the embodiment of the present invention, the same read address line is recorded as one address line, and the number of read address lines corresponding to the sliding window may be one or more than one.

In an optional embodiment, the extracting the corresponding sliding window data from the read stored data according to the input data sequence number corresponding to the sliding window sequence number, the read port data bit width and the write port data bit width of the RAM, the number of the RAMs in each RAM group, and the determined read address line includes:

and determining the read RAM according to the input data sequence number, the read port data bit width and the write port data bit width of the RAM, the number of the RAMs in each RAM group and the read address line determined based on the input data sequence number for any one of the input data sequence numbers corresponding to the sliding window sequence number.

In the embodiment of the invention, for any one of the input data sequence numbers corresponding to the sliding window sequence numbers, the write port data bit width and the read port data bit width of the RAMs, and the number of RAMs in each RAM group, the read address line corresponding to the sliding window sequence numbers is determined, and then the read RAM is determined according to the input data sequence numbers, the write port data bit width and the read port data bit width of the RAMs, the number of RAMs in each RAM group, and the read address line corresponding to the sliding window.

Alternatively, the read RAM is determined according to the following formula (8):

k＝floor((rd_data_num-rd_B_addr×M×lenB/lenA)/(lenB/lenA)) (8)

wherein k represents the serial number of the read RAM corresponding to the input data serial number; rd_b_addr represents a read address line corresponding to the sliding window determined based on the input data sequence number, and rd_data_num represents the input data sequence number; lenA is the write port data bit width of RAM; lenB is the read port data bit width of RAM; m is the number of RAMs in each RAM group; floor means rounded down.

Taking the 149 th input data as an example, the number of the address unit where the input data is located in the RAM is 4, that is, the read address line is 4, the number k of the RAM occupied by the input data is:

k＝floor((149-4×4×64/8)/(64/8))＝floor(21/8)＝floor(2.6)＝2

i.e. the 149 th input data is located at the 4 th address location in the 2 nd RAM (i.e. RAM 2).

And determining the specific position of the input data corresponding to the input data sequence number in the storage position corresponding to the read address line based on the read address line and the read RAM determined by the input data sequence number according to the input data sequence number, the read port data bit width and the write port data bit width of the RAM and the number of the RAMs in each RAM group.

Optionally, a specific location of the input data corresponding to the input data sequence number in the storage location corresponding to the read address line may be determined according to the following formula (9):

w＝rd_data_num-rd_B_addr×M×lenB/lenA-k×lenB/lenA (9)

wherein w represents a specific position of the input data in the address unit; k represents the serial number of the read RAM; rd_b_addr represents a read address line determined based on the input data sequence number, and rd_data_num represents the input data sequence number; lenA is the write port data bit width of RAM; lenB is the read port data bit width of RAM; m is the number of RAMs in each RAM group.

Taking the 149 th input data as an example, the number of the address unit where the input data is located in the RAM is 4, the number of the read RAM where the input data is located is 2, and the position w of the input data in the address unit No. 4 is:

w＝149-4×4×64/8-2×64/8＝149-128-16＝5

That is, the 149 th input data is located at the 5 th position (number from 0 from left to right) of the 4 th address unit in the 2 nd memory cell RAM2 of the RAM bank.

After determining the position w of the data corresponding to the input data sequence number and the sequence number k of the read RAM corresponding to the input data sequence number in the address unit corresponding to the read address line, the sliding window data can be extracted from the read storage data. In the case that the number of the determined read address lines is greater than one, since each portion of the sliding window data extracted from the storage data read in the different RAM banks needs to be spliced, the start position and the end position of the splicing need to be determined, in the embodiment of the present invention, the start position and the end position of the splicing may be determined by:

determining a start input data sequence number and an end input data sequence number of the input data sequence number corresponding to the window data sequence number;

determining a serial number k (k_1 for convenience of distinction), a read address line rd_B_addr (rd_B_addr_1 for convenience of distinction) of a read RAM corresponding to a starting input data serial number and a position w (w_1 for convenience of distinction) of data corresponding to the input data serial number in an address unit corresponding to the read address line;

Determining a sequence number k (denoted as k_2 for convenience of distinction) of a read RAM corresponding to the end input data sequence number, a read address line rd_B_addr (denoted as rd_B_addr_2 for convenience of distinction), and a position w (denoted as w_2 for convenience of distinction) of data corresponding to the input data sequence number in an address unit corresponding to the read address line;

if the read address line rd_b_addr_1 corresponding to the initial input data sequence number is the same as the read address line rd_b_addr_2 corresponding to the final input data sequence number, extracting all data corresponding to the window data sequence number from one RAM set: extracting data from the position w_1 of the address unit corresponding to the address line rd_B_addr_1 of the kth_1 RAM until the position w_2 of the address unit corresponding to the address line rd_B_addr_2 of the kth_2 RAM is finished, and splicing the extracted data according to the extraction sequence;

if the read address line rd_b_addr_1 corresponding to the initial input data sequence number is different from the read address line rd_b_addr_2 corresponding to the final input data sequence number, data needs to be extracted from two RAM banks, wherein one RAM bank (for describing as a first RAM bank) extracts data in an address unit corresponding to the read address line rd_b_addr_1, and the other RAM bank (for describing as a second RAM bank) extracts data in an address unit corresponding to the read address line rd_b_addr_2, specifically: in the first RAM bank, the extracted data includes: starting from the position w_1 of the address unit corresponding to the address line rd_b_addr_1 in the kth RAM to the last position data of the address unit corresponding to the address line rd_b_addr_1 of the mth RAM; in the second RAM bank, the extracted data includes: data from the 1 st position of the address unit corresponding to the read address line rd_b_addr_2 in the 0 th RAM up to the position w_2 of the address unit corresponding to the address line rd_b_addr_2 in the k_2 th RAM. And splicing the fetched data according to the sequence of the address lines from small to large and the RAM sequence numbers from small to large.

It should be noted that, the above-mentioned splicing scheme is only an optional implementation manner, and in a specific implementation, other implementation manners exist, so long as when the number of the determined read address lines is greater than one, the stored data in the storage positions corresponding to the different read address lines are read in different RAM groups; and splicing all parts of the sliding window data extracted from the storage data read in different RAM groups, so that the input data sequence numbers in the spliced data are the same as the input data sequence numbers corresponding to the sliding windows.

The following illustrates a specific implementation of the splicing scheme:

assuming that the input data sequence number corresponding to the sliding window sequence number is from 121 to 140, that is, the start input data sequence number is 121 and the end input data sequence number is 140, then:

based on the formula (7), the read address line rd_b_addr_1 corresponding to the initial input data sequence number 121 may be determined to be 3, based on the formula (8), the sequence number of the read RAM corresponding to the initial input data sequence number 121 may be determined to be 3, and based on the formula (9), the position w_1 of the input data corresponding to the input data sequence number 121 corresponding to the initial input data sequence number 121 in the address unit corresponding to the read address line rd_b_addr_1 may be determined to be 1.

Based on the formula (7), the read address line rd_b_addr_2 corresponding to the ending input data sequence number 140 may be determined to be 4, based on the formula (8), the sequence number k_2 of the read RAM corresponding to the ending input data sequence number 140 may be determined to be 1, and based on the formula (9), the position w_2 of the input data corresponding to the ending input data sequence number 140 in the address unit corresponding to the read address line rd_b_addr_2 may be determined to be 4.

In this example, if the read address line rd_b_addr_1 corresponding to the initial input data sequence number is different from the read address line rd_b_addr_2 corresponding to the final input data sequence number, the data needs to be extracted from the two RAM banks, which may be specifically: in the first RAM bank, the extracted data includes: starting from the position 1 of the address unit corresponding to the No. 3 read address line in the No. 3 RAM, and up to the data in the last position of the address unit corresponding to the No. 3 read address line of the No. 3 RAM; in the second RAM bank, the extracted data includes: starting from the 0 th position of the address unit corresponding to the 4 th read address line in the 0 th RAM, and up to the data in the position 4 of the address unit corresponding to the 4 th read address line in the 1 st RAM. And splicing the fetched data according to the sequence of the address lines from small to large and the RAM sequence numbers from small to large. Based on this, the spliced data is the input data corresponding to the input data sequence numbers 121-140.

For another example, if the input data sequence number corresponding to the sliding window sequence number is 169-188, i.e., the start input data sequence number is 169 and the end input data sequence number is 188, then:

based on the formula (7), the read address line rd_b_addr_1 corresponding to the initial input data sequence number 169 may be determined to be 5, based on the formula (8), the sequence number of the read RAM corresponding to the initial input data sequence number 169 may be determined to be 1, and based on the formula (9), the position w_1 of the input data corresponding to the input data sequence number 169 corresponding to the initial input data sequence number 169 in the address unit corresponding to the read address line rd_b_addr_1 may be determined to be 1.

Based on the formula (7), the read address line rd_b_addr_2 corresponding to the ending input data sequence number 188 can be determined to be 5, based on the formula (8), the sequence number k_2 of the read RAM corresponding to the ending input data sequence number 188 can be determined to be 3, and based on the formula (9), the position w_2 of the input data corresponding to the ending input data sequence number 188 in the address unit corresponding to the read address line rd_b_addr_2 can be determined to be 4.

In this example, the read address line rd_b_addr_1 corresponding to the start input data sequence number is the same as the read address line rd_b_addr_2 corresponding to the end input data sequence number, and all data can be extracted from one RAM bank: and (3) extracting data from the position 1 of the address unit corresponding to the No. 5 read address line of the No. 1 RAM in the first RAM group, and splicing the extracted data according to the extraction sequence until the position 4 of the address unit corresponding to the No. 5 read address line of the No. 3 RAM is finished, wherein the spliced data is input data with the input data sequence numbers corresponding to 169-188.

Corresponding to the method embodiment, the embodiment of the present invention further provides a data processing device, and a schematic structural diagram of the data processing device provided in the embodiment of the present invention is shown in fig. 4, which may include:

A write address determination module 41, a write data module 42, a sequence number determination module 43, a read address line determination module 44, a read data module 45 and a data extraction module 46; wherein, the liquid crystal display device comprises a liquid crystal display device,

the write address line determining module 41 is configured to divide the original data into input data with the same length, and sequentially number the input data, and determine a write address line according to the pre-configuration information and the serial number of the input data in each write clock cycle; the pre-configuration information includes: the number of RAMs in each RAM group, the width of the write address line of the RAMs, and the width of the write port data bit and the read port data bit of the RAMs; the number of the RAM groups is determined according to the bit width of the sliding window data, the number of the RAMs included in each RAM group, and the write port data bit width and the read port data bit width of the RAMs; or, the number of RAMs included in each RAM group, the write port data bit width and the read port data bit width of the RAMs are determined according to the number of the RAM groups and the bit width of the sliding window data;

the write data module 42 is configured to determine a write RAM according to the input data sequence number, the number of RAMs in each RAM group, and the write port data bit width and the read port data bit width of the RAM, and write the input data corresponding to the input data sequence number according to the determined write address line and the write RAM;

The sequence number determining module 43 is configured to determine a sliding window sequence number in each read clock cycle when the data needs to be read after writing all the input data;

the read address line determining module 44 is configured to determine a read address line corresponding to the sliding window sequence number according to the input data sequence number corresponding to the sliding window sequence number, the read port data bit width and the write port data bit width of the RAM, and the number of RAMs in each RAM group;

the read data module 45 is configured to read the stored data from the storage location corresponding to the determined read address line; when the number of the determined read address lines is greater than one, reading the storage data in the storage positions corresponding to the different read address lines in different RAM groups;

the data extraction module 46 is configured to extract corresponding sliding window data from the read storage data according to the input data sequence number corresponding to the sliding window sequence number, the read port data bit width and the write port data bit width of the RAM, the number of the RAMs in each RAM group, and the determined read address line; when the number of the determined read address lines is greater than one, each part of the sliding window data is extracted from the storage data read in different RAM groups to be spliced, so that corresponding sliding window data is obtained.

According to the data processing device provided by the embodiment of the invention, at least two original data are stored, each original data are stored in a plurality of RAMs (namely, RAM groups) in a distributed manner, so that when the data covered by the sliding window occupy a plurality of address units, different parts of the data covered by the sliding window can be read from the plurality of RAM groups at the same time, and the parallel reading of the data of the sliding window in one reading clock period is realized, thereby improving the data processing efficiency of an embedded system.

In an alternative embodiment, the write address line determining module 41 is specifically configured to, when determining the write address line according to the pre-configuration information and the input data sequence number:

the write address line is determined according to the following formula:

In an alternative embodiment, the number of RAM banks, the bit width of the sliding window data, the number of RAMs included in each RAM bank, and the write port data bit width and the read port data bit width of the RAM satisfy the following relationship:

R≥(P-lenA+lenB)/(M×lenB)

In an alternative embodiment, the write data module 42, when determining to write to RAM, is specifically configured to:

determining the write RAM according to the following formula:

wherein, RAM_num represents the sequence number of the write RAM;

we_v=1 indicates that the write port to be written to RAM is enabled;

wrdatanum [ log2 (M) +log2 (lenB/lenA) -1:log2 (lenB/lenA) ] represents data taking log2 (M) +log2 (lenB/lenA) -1 bit to log2 (lenB/lenA) bit of wrdatanum; wrdatanum represents an input data sequence number; lenA is the write port data bit width of RAM; lenB is the read port data bit width of RAM; m is the number of RAMs in each RAM group.

In an alternative embodiment, the write data module 42 is specifically configured to, when writing the input data corresponding to the input data sequence number according to the determined write address line and the write RAM:

In an alternative embodiment, the read address line determination module 44 is specifically configured to:

rd_B_addr＝floor(rd_data_num/(lenB/lenA×M))

In an alternative embodiment, the data extraction module 46 is specifically configured to, when extracting corresponding sliding window data from the read stored data according to the input data sequence number corresponding to the sliding window sequence number, the read port data bit width and the write port data bit width of the RAM, the number of RAMs in each RAM group, and the determined read address line:

In an alternative embodiment, the data extraction module 46 is specifically configured to, when determining the read RAM:

the read RAM is determined according to the following formula:

k＝floor((rd_data_num-rd_B_addr×M×lenB/lenA)/(lenB/lenA))

In an alternative embodiment, the data extraction module 46 is specifically configured to, when determining a specific location of the input data corresponding to the input data sequence number in the storage location corresponding to the read address line:

determining a specific position of the input data corresponding to the input data sequence number in a storage position corresponding to the read address line according to the following formula:

w＝rd_data_num-rd_B_addr×M×lenB/lenA-k×lenB/lenA

The data processing device provided by the embodiment of the invention can be applied to electronic equipment. Optionally, fig. 5 shows a block diagram of a hardware structure of the electronic device, and referring to fig. 5, the hardware structure of the electronic device may include: at least one processor 1, at least one communication interface 2, at least one memory 3 and at least one communication bus 4;

in the embodiment of the invention, the number of the processor 1, the communication interface 2, the memory 3 and the communication bus 4 is at least one, and the processor 1, the communication interface 2 and the memory 3 complete the communication with each other through the communication bus 4;

processor 1 may be a central processing unit CPU, or a specific integrated circuit ASIC (Application Specific Integrated Circuit), or one or more integrated circuits configured to implement embodiments of the present invention, etc.;

The memory 3 may comprise a high-speed RAM memory, and may further comprise a non-volatile memory (non-volatile memory) or the like, such as at least one magnetic disk memory;

wherein the memory stores a program, the processor is operable to invoke the program stored in the memory, the program operable to:

dividing the original data into input data with the same length, numbering according to the sequence, and determining a write address line according to the pre-configuration information and the sequence number of the input data in each write clock period; the pre-configuration information includes: the number of RAMs in each RAM group, the width of the write address line of the RAMs, and the width of the write port data bit and the read port data bit of the RAMs; the number of the RAM groups is determined according to the bit width of the sliding window, the number of the RAMs included in each RAM group, and the write port data bit width and the read port data bit width of the RAMs; or, the number of RAMs included in each RAM group, the write port data bit width and the read port data bit width of the RAMs are determined according to the number of the RAM groups and the bit width of the sliding window data;

Alternatively, the refinement function and the extension function of the program may be described with reference to the above.

The embodiment of the present invention also provides a storage medium storing a program adapted to be executed by a processor, the program being configured to:

Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.

In the several embodiments provided herein, it should be understood that the disclosed system (if any), apparatus, and method may be implemented in other ways. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.

The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in the embodiments of the present invention may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.

It should be understood that in the embodiments of the present invention, the claims, the various embodiments, and the features may be combined with each other, so as to solve the foregoing technical problems.

The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution, in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, a server, a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-only memory (ROM), a random access memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method of data processing, comprising:

2. The method of claim 1, wherein determining the write address line based on the pre-configuration information and the input data sequence number comprises:

the write address line is determined according to the following formula:

3. The method of claim 1, wherein the number of RAM banks, the bit width of the sliding window data, the number of RAMs included in each RAM bank, and the write port data bit width and the read port data bit width of the RAM satisfy the following relationship:

R≥(P-lenA+lenB)/(M×lenB)

4. The method of claim 1, wherein determining the write RAM based on the input data sequence number, the number of RAMs in each RAM bank, and the write port data bit width and the read port data bit width of each RAM, comprises:

determining the write RAM according to the following formula:

Wherein, RAM_num represents the sequence number of the write RAM;

we_v=1 indicates that the write port to be written to RAM is enabled;

5. The method according to claim 4, wherein writing the input data corresponding to the input data sequence number according to the determined write address line and the write RAM comprises:

6. The method of claim 1, wherein determining the read address line corresponding to the sliding window sequence number according to the input data sequence number corresponding to the sliding window sequence number, the read port data bit width and the write port data bit width of the RAM, and the number of RAMs in each RAM bank comprises:

rd_B_addr＝floor(rd_data_num/(lenB/lenA×M))

7. The method of claim 6, wherein extracting the corresponding sliding window data from the read stored data according to the input data sequence number corresponding to the sliding window sequence number, the read port data bit width and the write port data bit width of the RAM, the number of RAMs in each RAM bank, and the determined read address line, comprises:

8. The method of claim 7, wherein determining the read RAM comprises: the read RAM is determined according to the following formula:

k＝floor((rd_data_num-rd_B_addr×M×lenB/lenA)/(lenB/lenA))

9. The method of claim 7, wherein determining the specific location of the input data corresponding to the input data sequence number in the memory location corresponding to the read address line comprises: determining a specific position of the input data corresponding to the input data sequence number in a storage position corresponding to the read address line according to the following formula:

w＝rd_data_num-rd_B_addr×M×lenB/lenA-k×lenB/lenA

10. A data processing apparatus, comprising: