CN112328522A

CN112328522A - Data processing method and device

Info

Publication number: CN112328522A
Application number: CN202011355821.9A
Authority: CN
Inventors: 李为良
Original assignee: Beijing Runke General Technology Co Ltd
Current assignee: Beijing Runke General Technology Co Ltd
Priority date: 2020-11-26
Filing date: 2020-11-26
Publication date: 2021-02-05
Anticipated expiration: 2040-11-26
Also published as: CN112328522B

Abstract

The embodiment of the invention discloses a data processing method and a data processing device, wherein at least two parts of original data are stored, and each part of the original data is distributed and stored in a plurality of RAMs (namely RAM groups), so that when the data covered by a sliding window occupies a plurality of address units, different parts of the data covered by the sliding window can be simultaneously read from the plurality of RAM groups, and the parallel reading of the data of the sliding window in one reading clock cycle is realized, thereby improving the data processing efficiency of an embedded system.

Description

Data processing method and device

Technical Field

The present invention relates to the field of data processing technologies, and in particular, to a data processing method and apparatus.

Background

When the embedded system processes data, the general process is to read data from the memory, then send the read data to the computing unit to complete specific operation, and finally output the computing result. The existing embedded system reads data in sequence in a pipeline mode when reading the data, namely, the data in one address can only be read in each clock cycle, the data reading speed is low due to the processing mode, particularly, a data processing algorithm with a sliding window extraction processing requirement possibly causes that the data in one sliding window needs to be read in a plurality of clock cycles and the data in the sliding window cannot be efficiently obtained, so that the real-time property of data processing cannot meet the requirement of high-speed processing.

Therefore, how to improve the data processing efficiency of the embedded system becomes an urgent technical problem to be solved.

Disclosure of Invention

The invention aims to provide a data processing method and a data processing device so as to improve the data processing efficiency of an embedded system. The technical scheme is as follows:

a method of data processing, comprising:

dividing original data into input data with the same length, numbering the input data in sequence, and determining a write address line according to pre-configuration information and an input data sequence number in each write clock cycle; the pre-configuration information includes: the number of RAMs in each RAM group, the width of a write address line of the RAM, and the bit width of write port data and the bit width of read port data of the RAM; the number of the RAM groups is determined according to the bit width of the sliding window data, the number of the RAMs in each RAM group, the bit width of the write port data of the RAM and the bit width of the read port data of the RAM; or, the number of RAMs in each RAM group, the bit width of the write port data of the RAM and the bit width of the read port data are determined according to the number of the RAM groups and the bit width of the sliding window data;

determining a write RAM according to the input data serial number, the number of RAMs in each RAM group, the write port data bit width and the read port data bit width of the RAMs, and writing input data corresponding to the input data serial number into the write RAM according to the determined write address line and the write RAM;

after all input data are written, when data need to be read, determining a serial number of a sliding window in each reading clock period;

determining a read address line corresponding to the sliding window serial number according to the input data serial number corresponding to the sliding window serial number, the read port data bit width and the write port data bit width of the RAM, and the number of the RAMs in each RAM group;

reading storage data from the storage position corresponding to the determined reading address line; when the number of the determined read address lines is more than one, reading storage data in storage positions corresponding to different read address lines in different RAM groups;

extracting corresponding sliding window data from the read storage data according to the input data serial number corresponding to the sliding window serial number, the read port data bit width and the write port data bit width of the RAM, the number of the RAMs in each RAM group and the determined read address line; when the number of the determined read address lines is more than one, extracting all parts of the sliding window data from the storage data read from different RAM groups for splicing to obtain corresponding sliding window data.

Optionally, the determining, according to the pre-configuration information and the input data sequence number, the address-writing line includes:

the write address line is determined according to the following equation:

wr_addr＝{wr_data_num[addr_A_width-1:log2(M)+log2(lenB/lenA)],wr_data_num[log2(lenB/lenA)-1:0]}

wherein wr _ addr represents a write address line; wr _ data _ num is an input data sequence number; lenA is the data bit width of a write port of the RAM; lenB is the read port data bit width of the RAM; m is the number of RAMs in each RAM group;

wr _ data _ num [ addr _ A _ width-1: log2(M) + log2(lenB/lenA) ] represents the high order bits of the write address line, and the data from the addr _ A _ width-1 bit of the wr _ data _ num to the log2(M) + log2(lenB/lenA) bits are taken; wr _ data _ num [ log2(lenB/lenA) -1:0] represents the low order of the write address line, and takes the data from log2(lenB/lenA) -1 bit to 0 bit of the wr _ data _ num; addr _ A _ width is the write address line width of the RAM.

Optionally, in the method, the determining, by the number of the RAM groups according to the bit width of the sliding window data, the number of RAMs included in each RAM group, and the bit width of the write port data and the bit width of the read port data of the RAM includes:

determining the number of the RAM groups according to the following formula:

R≥(P-lenA+lenB)/(M×lenB)

wherein R represents the number of the RAM groups; lenA is the data bit width of a write port of the RAM; lenB is the read port data bit width of the RAM; m is the number of RAMs in each RAM group, and P represents the bit width of the sliding window data.

Optionally, the determining the write RAM according to the input data sequence number, the number of RAMs in each RAM group, and the write port data bit width and the read port data bit width of each RAM includes:

the write RAM is determined according to the following equation:

wherein, RAM _ num represents the serial number of the write RAM;

when we _ v is 1, the write port of the write RAM is enabled;

wr _ data _ num [ log2(M) + log2(lenB/lenA) -1: log2(lenB/lenA) ] represents data of log2(M) + log2(lenB/lenA) -1 bit to log2(lenB/lenA) bit of wr _ data _ num; wr _ data _ num represents an input data sequence number; lenA is the data bit width of a RAM write port; lenB is the read port data bit width of the RAM; m is the number of RAMs in each RAM group.

Optionally, the writing the input data corresponding to the input data sequence number according to the determined write address line and the write RAM includes:

determining the writing position of the input data corresponding to the input data serial number in the writing RAM according to the writing address line; and writing the data in the input data corresponding to the input data sequence number in a matching manner according to the position sequence of the RAM in each RAM group.

Optionally, the determining, according to the input data sequence number corresponding to the sliding window sequence number, the read port data bit width and the write port data bit width of the RAM, and the number of RAMs in each RAM group, a read address line corresponding to the sliding window sequence number includes:

determining a read address line corresponding to the sliding window serial number according to the following formula:

rd_B_addr＝floor(rd_data_num/(lenB/lenA×M))

the rd _ B _ addr represents a read address line corresponding to the sliding window serial number, and the rd _ data _ num represents any input data serial number in the input data serial numbers corresponding to the sliding window serial number; lenA is the data bit width of a write port of the RAM; lenB is the read port data bit width of the RAM; m is the number of RAMs in each RAM group; floor denotes rounding down.

Optionally, the method, where the extracting, according to the input data sequence number corresponding to the sliding window sequence number, the read port data bit width and the write port data bit width of the RAM, the number of RAMs in each RAM group, and the determined read address line, corresponding sliding window data from the read storage data includes:

for any input data serial number in the input data serial numbers corresponding to the sliding window serial numbers, determining a read RAM according to the input data serial number, the read port data bit width and the write port data bit width of the RAM, the number of RAMs in each RAM group and a read address line determined based on the input data serial number;

according to the input data serial number, the read port data bit width and the write port data bit width of the RAM, and the number of the RAMs in each RAM group, determining a read address line and a read RAM based on the input data serial number, and determining the specific position of the input data corresponding to the input data serial number in a storage position corresponding to the read address line;

and extracting corresponding sliding window data from the read storage data according to the determined read RAM and the determined specific position.

The method, optionally, determining to read the RAM includes: the read RAM is determined according to the following equation:

k＝floor((rd_data_num-rd_B_addr×M×lenB/lenA)/(lenB/lenA))

wherein k represents the serial number of the read RAM corresponding to the serial number of the input data; rd _ B _ addr represents a read address line determined based on the input data sequence number, and rd _ data _ num represents the input data sequence number; lenA is the data bit width of a write port of the RAM; lenB is the read port data bit width of the RAM; m is the number of RAMs in each RAM group; floor denotes rounding down.

Optionally, in the method, the step of determining a specific location of the input data corresponding to the input data sequence number in the storage location corresponding to the read address line includes: determining the specific position of the input data corresponding to the input data sequence number in the storage position corresponding to the read address line according to the following formula:

w＝rd_data_num-rd_B_addr×M×lenB/lenA-k×lenB/lenA

wherein, w represents the specific position of the input data corresponding to the input data serial number in the storage position corresponding to the read address line; k represents the serial number of the read RAM corresponding to the serial number of the input data; rd _ B _ addr represents a read address line determined based on the input data sequence number, and rd _ data _ num represents the input data sequence number; lenA is the data bit width of a write port of the RAM; lenB is the read port data bit width of the RAM; m is the number of RAMs in each RAM group.

A data processing apparatus comprising:

the write address line determining module is used for dividing the original data into input data with the same length, numbering the input data in sequence, and determining the write address line according to the pre-configuration information and the input data sequence number in each write clock cycle; the pre-configuration information includes: the number of RAMs in each RAM group, the width of a write address line of the RAM, and the bit width of write port data and the bit width of read port data of the RAM; the number of the RAM groups is determined according to the bit width of the sliding window data, the number of the RAMs in each RAM group, the bit width of the write port data of the RAM and the bit width of the read port data of the RAM; or, the number of RAMs in each RAM group, the bit width of the write port data of the RAM and the bit width of the read port data are determined according to the number of the RAM groups and the bit width of the sliding window data;

the data writing module is used for determining a write RAM according to the input data serial number, the number of RAMs in each RAM group, the write port data bit width and the read port data bit width of each RAM, and writing input data corresponding to the input data serial number into the write RAM according to the determined write address line and the write RAM;

the sequence number determining module is used for determining the sequence number of the sliding window in each reading clock cycle when data needs to be read after all input data are written;

the read address line determining module is used for determining a read address line corresponding to the sliding window serial number according to the input data serial number corresponding to the sliding window serial number, the read port data bit width and the write port data bit width of the RAM, and the number of the RAMs in each RAM group;

the read data module is used for reading the storage data from the storage position corresponding to the determined read address line; when the number of the determined read address lines is more than one, reading storage data in storage positions corresponding to different read address lines in different RAM groups;

the data extraction module is used for extracting corresponding sliding window data from the read storage data according to the input data serial number corresponding to the sliding window serial number, the read port data bit width and the write port data bit width of the RAM, the number of the RAMs in each RAM group and the determined read address line; when the number of the determined read address lines is more than one, extracting all parts of the sliding window data from the storage data read from different RAM groups for splicing to obtain corresponding sliding window data.

According to the scheme, when data are stored, the original data are divided into input data with the same length, the input data are numbered in sequence, and in each write clock cycle, a write address line is determined according to preset information (including the number of RAMs in each RAM group, the write address line width of the RAMs, the write port data bit width and the read port data bit width of the RAMs, the number of the RAM groups is determined according to the bit width of sliding window data, the number of RAMs in each RAM group, the write port data bit width and the read port data bit width of the RAMs, or the number of RAMs in each RAM group, the write port data bit width and the read port data bit width of the RAMs are determined according to the number of the RAM groups and the bit width of the sliding window data) and an input data serial number; determining a write RAM according to the input data serial number, the number of RAMs in each RAM group, the write port data bit width and the read port data bit width of each RAM, and writing input data corresponding to the input data serial number into the write RAM according to the determined write address line and the write RAM; after all input data are written, when data need to be read, determining a serial number of a sliding window in each reading clock period; determining a read address line corresponding to the sliding window serial number according to the input data serial number corresponding to the sliding window serial number, the read port data bit width and the write port data bit width of the RAM, and the number of the RAMs in each RAM group; reading storage data from the storage position corresponding to the determined reading address line; when the number of the determined read address lines is more than one, reading storage data in storage positions corresponding to different read address lines in different RAM groups; extracting corresponding sliding window data from the read storage data according to the input data serial number corresponding to the sliding window serial number, the read port data bit width and the write port data bit width of the RAM, the number of the RAMs in each RAM group and the determined read address line; when the number of the determined read address lines is more than one, all parts of the sliding window data extracted from the storage data read from different RAM groups are spliced to obtain corresponding sliding window data. According to the invention, by improving the writing mode and the reading mode of the data, all data in the sliding window can be read in one reading clock cycle, and the parallel reading of the data in the sliding window is realized, so that the data processing efficiency of the embedded system is improved.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a flow chart of an implementation of writing data according to an embodiment of the present invention;

fig. 2 is a flowchart of an implementation of reading data in a sliding window in each read clock cycle according to an embodiment of the present invention;

FIG. 3 is a diagram illustrating an exemplary structure of a RAM bank according to an embodiment of the present invention;

FIG. 4 is a schematic structural diagram of a data processing apparatus according to an embodiment of the present invention;

fig. 5 is a block diagram of a hardware structure of an electronic device according to an embodiment of the present invention.

The terms "first," "second," "third," "fourth," and the like in the description and in the claims, as well as in the drawings described above, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated herein.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without inventive effort based on the embodiments of the present invention, are within the scope of the present invention.

The data processing method provided by the embodiment of the invention is applied to an embedded system, and the embedded system can be an embedded system realized based on a Field-Programmable Gate Array (FPGA).

For a clear understanding of the present invention, the inventive concept of the present invention will be described first, and the inventive concept of the present invention is: by improving the writing mode and the reading mode of the data, the aim of reading all data in the sliding window in one reading clock cycle is fulfilled, the parallel reading of the sliding window data is realized, and the data processing efficiency of the embedded system is improved.

In the embodiment of the present invention, for convenience of description, data to be processed is referred to as raw data, and the raw data may be image data, text data, or other data to be processed, such as video data or audio data.

In the embodiment of the invention, the original data is stored in at least two parts, and each part is stored in a RAM (random access memory) group. Wherein the content of the first and second substances,

each RAM group comprises M (M is an integer larger than 1) RAMs, and the RAMs in different RAM groups have the same number; each RAM comprises K address units, and the serial numbers of the address units in different RAM groups are the same; each address unit comprises N sub-address units, in each RAM group, the sub-address units in each RAM are independently numbered, the numbers of the sub-address units in different RAM groups are the same, and the bit widths of the sub-address units are the same.

The data bit width of the write port of each RAM is the bit width of the sub-address unit, so that for each RAM, when data are written in the RAM, the data can be written in only one sub-address unit of the RAM in each write clock cycle, and the data bit width of the write port of each RAM is the same; and on the basis that the read port data bit width of each RAM is the bit width of the address unit, when data is read from the RAM group, the data can be read from only one address unit of the RAM in each read clock cycle, and the read port data bit widths of the RAMs are the same.

In the embodiment of the present application, the number of RAM groups (for convenience of description, denoted as R) may be determined according to a bit width of a sliding window (that is, a bit width of sliding window data, denoted as P for convenience of description), a number M of RAMs included in each RAM group, a write port data bit width (for convenience of description, denoted as lenA) and a read port data bit width (for convenience of description, denoted as lenB) of the RAMs. The number R of RAM banks can be determined based on the following relationship:

(P/lenA)≤[R×M×(lenB/lenA)-lenB/lenA+1] (1)

namely: r is more than or equal to (P-lenA + lenB)/(M x lenB) (2)

In the embodiment of the present invention, the value of R may be the minimum integer value satisfying the above relationship. The present invention is directed to a scenario for data processing based on a sliding window, and therefore, the bit width P of the sliding window is known.

In another alternative embodiment, the number of RAM groups may be determined first, and then the RAM groups are selected according to the number of RAM groups, the bit width of the sliding window data, and formula (1) or formula (2) to construct the RAM groups, that is, the number of RAMs included in each RAM group, the bit width of the write port data of the RAM, and the bit width of the read port data of the RAM are determined based on formula (1) or formula (2) according to the number of RAM groups and the bit width of the sliding window data.

It should be noted that, in general, the way data is presented to the user is different from the way data is stored in the memory. Taking image data as an example, the image data is presented to a user in a pixel point manner, the relative position relationship between the pixel points is a first relative position relationship, when the image data is stored, the corresponding numerical values of each pixel point are stored, and the relative position relationship between the pixel points is not the first relative position relationship any more, that is, for the image data, the original data refers to the corresponding numerical values of the pixel points which need to be stored in the memory, but not the pixel points themselves. Therefore, in a scenario in which data is extracted using a sliding window, it is necessary to convert a user-side sliding window (for determining a data extraction range in data presented to a user) into a background-side sliding window (for determining a data extraction range in a memory), and convert a moving step size of the user-side sliding window into a moving step size of the background-side sliding window. How to convert can be referred to an existing conversion method, and the conversion method is not focused on the invention, so the detailed description is omitted here. Based on this, unless otherwise specified, the sliding window in the embodiment of the present invention refers to a background-side sliding window. The serial number of the background side sliding window is the same as that of the corresponding user side sliding window.

The following describes a specific implementation of writing raw data into a RAM bank. Since the composition of each RAM group is the same, the manner in which the original data is written to each RAM group is the same. Referring to fig. 1, fig. 1 is a flowchart illustrating an implementation of writing data according to an embodiment of the present invention, which may include:

step S11: the original data is divided into input data of the same length and numbered in sequence.

As can be seen from the above description, the write port data bit width of each RAM is the bit width of a sub address unit, and when data is written into the RAM, data can be written into only one sub address unit in each write clock cycle.

The length of the input data is generally different from the bit width of the sliding window, and usually, the bit width of the sliding window is greater than the length of the input data.

Step S12: in each write clock cycle, determining a write address line according to the pre-configuration information and the input data sequence number; the pre-configuration information includes: the number M of RAMs in each RAM group, the write address line width of the RAM (for convenience of description, denoted as addr _ a _ width), and the write port data bit width lenA and read port data bit width lenB of the RAM; the number R of the RAM groups is determined according to the bit width of the sliding window data, the number M of the RAMs in each RAM group, the write port data bit width lenA and the read port data bit width lenB of the RAMs; alternatively, the write port data bit width lenA and the read port data bit width lenB of the RAM number M, RAM included in each RAM group are determined according to the number R of RAM groups and the bit width of the sliding window data.

Each write address line corresponds to a write address, and different write address lines correspond to different write addresses. Wherein a write address line has a sub-address location in each RAM corresponding thereto.

In the embodiment of the present invention, the write address lines of the input data with consecutive sequence numbers may be consecutive or discontinuous, which is determined according to an actual scenario.

For example, in a certain RAM, a storage location corresponding to a first write address line of a 0 th address unit (i.e., a sub-address unit corresponding to the first write address line) may be written first, then a storage location corresponding to a second write address line of the 0 th address unit (i.e., a sub-address unit corresponding to the second write address line) may be written, then a storage location corresponding to a third write address line of the 0 th address unit (i.e., a sub-address unit corresponding to the third write address line) may be written, and so on until the 0 th address unit of the RAM is written. And then writing the 0 th address unit in the next RAM according to the same rule, and so on until writing the 0 th address units of all the RAMs. And then writing in the 1 st address unit in the 0 th RAM according to the same rule until all input data are written into the RAM group.

Or, in a certain RAM, the storage location corresponding to the first write address line of the 0 th address unit may be written first, then the storage location corresponding to the third write address line of the 0 th address unit may be written again, then the storage location corresponding to the fifth write address line of the 0 th address unit may be written again, and so on until the 0 th address unit of the RAM is written. And then writing the 0 th address unit of one RAM in the next RAM according to the same rule, and so on until all the 0 th address units of the RAMs are written. Then, writing is carried out according to the same rule in the 1 st address unit in the 0 th RAM until all input data are written into the RAM group. In a specific application scenario, for example, image data of two images (at this time, the image data of each image is original data of the image) are to be processed simultaneously, the image data of one image is stored in a sub-address unit corresponding to a single number of write address lines, and the image data of the other image is stored in a sub-address unit corresponding to a double number of write address lines.

According to different practical application scenarios, the write address lines of the input data with continuous sequence numbers can be continuous or discontinuous, and based on the fact, according to different practical application scenarios, in each write clock cycle, the specific implementation mode of the write address lines is determined to be different according to the preset configuration information and the input data sequence numbers.

Step S13: and determining a write RAM according to the input data serial number, the number of RAMs in each RAM group, the write port data bit width and the read port data bit width of the RAMs, and writing the input data corresponding to the input data serial number into the write RAM according to the determined write address line and the write RAM.

The data bit width of the write port of the RAM is the data bit width of the write port of each RAM, and the data bit width of the read port of the RAM is the data bit width of the read port of each RAM.

According to different practical application scenarios, the write address lines of the input data with continuous serial numbers can be continuous or discontinuous, and based on the fact, according to different practical application scenarios, the specific implementation modes of the write RAM are determined to be different according to the input data serial numbers, the number of RAMs in each RAM group, and the write port data bit width and the read port data bit width of the RAM.

Regardless of the actual application scenario, after the write address line and the write RAM are determined, when the input data corresponding to the input data sequence number is written according to the determined write address line and the write RAM, the input data corresponding to the input data sequence number is written into the write RAM. In a specific implementation mode, the writing position of the input data in the writing RAM corresponding to the input data sequence number is determined according to the writing address line. And writing the data in the input data corresponding to the input data sequence number in a matching manner according to the position sequence of the RAM in each RAM group.

In the embodiment of the present invention, regardless of whether the write address lines of the input data with consecutive sequence numbers are consecutive or discontinuous, when the input data are written into the RAM group, the input data are sequentially written according to the position order of the RAMs in the RAM group, for example, first writing the 0 th address unit of the 0 th RAM, after the 0 th address unit of the 0 th RAM is written, writing the 0 th address unit of the 1 st RAM, after the 0 th address unit of the 1 st RAM is written, writing the 0 th address unit of the 2 nd RAM, and so on, until the 0 th address units of all RAMs in the RAM group are written, then writing the 1 st address unit of the 0 th RAM, after the 1 st address unit of the 0 th RAM is written, writing the 1 st address unit of the 1 st RAM, writing the 1 st address unit of the 2 nd RAM, and so on, until all the input data is written into the RAM bank.

Because the data writing mode of each RAM group is the same, when the input data corresponding to the input data serial number is written according to the determined writing address line and the writing RAM, each RAM group can be written simultaneously.

After all input data are written, when data needs to be read, in each read clock cycle, an implementation flowchart of reading data in a sliding window is shown in fig. 2, and may include:

step S21: a sliding window sequence number is determined.

In an actual application scenario, the sliding window is moved according to a certain step length, and therefore, the serial number of the sliding window is increased by 1 each time the sliding window is moved according to the step length, and therefore, the serial number of the sliding window can be recorded in the moving process of the sliding window. In each read clock cycle, the corresponding sliding window sequence number may be determined as required.

Step S22: and determining a read address line corresponding to the sliding window serial number according to the input data serial number corresponding to the sliding window serial number, the read port data bit width and the write port data bit width of the RAM, and the number of the RAMs in each RAM group.

The input data serial number corresponding to the sliding window serial number can be determined according to the sliding window serial number, the sliding window bit width, the sliding window moving step length and the input data length. Reference is made to the prior art for a specific implementation which is not described in detail herein as it is not the focus of the invention.

Since one sliding window usually covers a plurality of input data, the input data number corresponding to the sliding window number refers to the number of each input data corresponding to the sliding window number. Determining the read address line corresponding to the sliding window serial number refers to determining the address line corresponding to the address unit where the input data corresponding to the sliding window serial number is located.

Step S23: reading storage data from the storage position corresponding to the determined reading address line; when the number of the determined read address lines is more than one, reading the storage data in the storage positions corresponding to different read address lines in different RAM groups.

According to the bit width of the sliding window, the bit width of the address unit of the RAM and the position of the sliding window, in the sliding process of the sliding window, the data to be read corresponding to the serial number of the sliding window may be located in only one address unit or may be located in two or more address units. When the data to be read corresponding to the sliding window serial number is only located in one address unit, only one determined read address line is provided, and when the data to be read corresponding to the sliding window serial number is located in L (L is an integer greater than 1) address units, L determined read address lines are provided.

In the embodiment of the invention, when the number of the determined read address lines is more than one, the storage data in the storage positions corresponding to different read address lines are read in different RAM groups.

For example, if the determined number of the read address lines is 2 (i.e., the first read address line and the second read address line, respectively), the storage data in the storage location corresponding to the first read address line may be read in the first RAM bank, and the storage data in the storage location corresponding to the second read address line may be read in the second RAM bank.

If the determined number of the read address lines is 3 (respectively, the first read address line, the second read address line and the third read address line), the storage data in the storage position corresponding to the first read address line can be read in the first RAM group, the storage data in the storage position corresponding to the second read address line can be read in the second RAM group, and the storage data in the storage position corresponding to the third read address line can be read in the third RAM group.

Step S24: extracting corresponding sliding window data from the read storage data according to the input data serial number corresponding to the sliding window serial number, the read port data bit width and the write port data bit width of the RAM, the number of the RAMs in each RAM group and the determined read address line; when the number of the determined read address lines is more than one, all parts of the sliding window data extracted from the storage data read from different RAM groups are spliced to obtain corresponding sliding window data.

For each determined read address line, the data to be read corresponding to the sliding window serial number may occupy the address unit corresponding to the read address line, or may not occupy the address unit corresponding to the read address line, so that the sliding window data (i.e., the data covered by the sliding window) needs to be extracted from the read storage data, and when the number of the determined read address lines is more than one, the parts of the sliding window data extracted from the storage data read from different RAM banks need to be spliced to obtain the corresponding sliding window data.

In the data processing method provided by the embodiment of the invention, at least two parts of original data are stored, and each part of the original data is distributed and stored in a plurality of RAMs (namely RAM groups), so that when the data covered by the sliding window occupies a plurality of address units, different parts of the data covered by the sliding window can be simultaneously read from the plurality of RAM groups, and the parallel reading of the data of the sliding window in one reading clock cycle is realized, thereby improving the data processing efficiency of the embedded system.

The inventor of the present invention has found that, when the number of RAM banks is large, the logic to be considered in implementing the scheme of the present invention is complex, and the development cost is high due to the fact that the skilled person needs to pay more effort and spend longer development time. In order to simplify the logic to be considered when designing the scheme and reduce the development cost, the number R of the RAM groups is set to be 2, and based on the 2, the RAM for constructing the RAM groups can be selected according to the relation (3). The relation (3) is:

namely: 2 is not less than (P-lenA + lenB)/(M x lenB) (3)

As shown in fig. 3, a diagram of a structure example of one RAM bank is provided for the embodiment of the present invention, in this example, each RAM bank includes 4 RAMs, each RAM includes 8 address units (one address unit is a row in each RAM), and each address unit includes 8 sub-address units. The RAM bank includes a total of 256 sub-address units, 4 × 8 × 8.

In the example shown in fig. 3, when input data is written into the RAM group, the write address lines of consecutive input data are consecutive, and according to the sequence from small to large of the write address lines, after the 0 th address unit of each RAM is fully written, the 1 st address unit of each RAM is sequentially written, after the 1 st address unit of each RAM is fully written, the 2 nd address unit of each RAM is sequentially written, and so on until all input data are written into the RAM group. According to this writing method, each address unit stores 8 consecutive input data, and in two adjacent address units of each RAM, the difference between the serial numbers of the input data in the same column is M × N — 4 × 8 — 32. In fig. 3, each small square indicates a sub-address unit, and the numbers in the small squares represent the serial numbers of the input data, i.e. one input data is stored in each small square. For example, the cell 000 stores the 0 th input data, the cell 006 stores the 6 th input data, the cell 021 stores the 21 st input data, and the cell 153 stores the 153 th input data.

A specific implementation of the scheme of the present invention is described below based on the case of two RAM banks (i.e., R ═ 2).

In an optional embodiment, one implementation of the foregoing determining the write address line according to the pre-configuration information and the input data sequence number may be that the write address line is determined according to the following formula (4):

The width of the write address line of the RAM may be determined according to the following relationship:

addr_A_width≥log2(NUM) (5)

NUM is the number of subaddress units in the RAM.

Specifically, addr _ a _ width may be a minimum integer value that satisfies the above relationship (5).

Taking the input data stored in the RAM bank shown in fig. 3 as an example, in this example, the original data is divided into 256 pieces of input data with the same length, addr _ a _ width ≧ log2(256) is 8, based on which addr _ a _ width is 8, and assuming that lenB is 64, lenA is 8, and M is 4:

wr_addr＝{wr_data_num[8-1:log2(4)+log2(64/8)],wr_data_num[log2(64/8)-1:0]}

＝{wr_data_num[7:5],wr_data_num[2:0]}

for example, taking the 50 th input data (i.e. the input data sequence number is 50) as an example, the binary representation of 50 is: 00110010, the 7 th bit to the 5 th bit of the binary number are 001, the 2 nd bit to the 0 th bit are 010, the write address line determined based on the input data sequence number 50 is wr _ addr 001010 is 10, and as can be seen from fig. 3, the 50 th input data is located in the 10 th sub-address unit of the 2 nd RAM (i.e., RAM2) (note that the numbering of the sub-address units is in the order of encoding from left to right and from top to bottom, and all encoding is from 0).

For another example, taking the 121 th input data (i.e. the input data sequence number is 121) as an example, the binary expression of 121 is: 01111001, where the 7 th bit to the 5 th bit of the binary number are 011, and the 2 nd bit to the 0 th bit are 001, the write address line determined based on the input data sequence number 121 is wr _ addr 011001 ═ 25, and as can be seen from fig. 3, the 121 th input is located in the 25 th sub-address unit of the 3 rd RAM (i.e., RAM3) (note that the numbering of the sub-address units is from left to right, and from top to bottom, and all the encodings start from 0).

Obviously, only the write address line is determined, the specific write position of the input data cannot be determined, and the specific write RAM needs to be determined to determine the specific write position of the input data. In an optional embodiment, one implementation manner of determining the write RAM according to the input data sequence number, the number of RAMs in each RAM group, and the write port data bit width and the read port data bit width of each RAM may be:

the write RAM is determined according to the following equation (6):

wherein, RAM _ num represents the serial number of the write RAM;

when we _ v is 1, the write port of the write RAM is enabled;

Taking the input data stored in the RAM bank shown in fig. 3 as an example, assuming that lenB is 64, lenA is 8, and M is 4, then:

for example, taking the 50 th input data as an example, the binary representation of 50 is: 00110010, the 4 th bit to the 3 rd bit of the binary number are 10, that is, RAM _ num is 2, that is, the write RAM corresponding to the input data sequence number 50 determined based on the formula (6) is the 2 nd RAM (i.e., RAM 2).

For another example, taking the 121 th input data as an example, the binary expression of 121 is: 01111001, the 4 th bit to the 3 rd bit of the binary number are 11, that is, RAM _ num is 3, that is, the write RAM corresponding to the input data sequence number 121 determined based on the formula (6) is the 3 rd RAM (i.e., RAM 3).

In summary, for each RAM group, polling enables the write ports of M RAMs in the RAM group, and each time the write port of one RAM is enabled, the RAM is taken as the target RAM, N input data are continuously written in one address unit of the target RAM, and when the address unit is full, the target RAM is controlled to be disabled until all the input data are stored in the RAM group. The input data can be written into the plurality of RAM groups simultaneously, namely after the write address line corresponding to the input data and the write RAM are determined, the input data can be written into the sub-address unit corresponding to the write address line of the write RAM in each RAM group.

After all the input data are written in, when data need to be read, in each read clock cycle, one implementation manner of determining the read address line corresponding to the sliding window sequence number according to the input data sequence number corresponding to the sliding window sequence number, the read port data bit width and the write port data bit width of the RAM, and the number of RAMs in each RAM group may be as follows:

determining a read address line corresponding to the sliding window sequence number according to the following formula (7):

rd_B_addr＝floor(rd_data_num/(lenB/lenA×M)) (7)

For example, taking the 149 th input data (i.e. the input data number 149) as an example, based on the input data number 149, the read address line corresponding to the sliding window number is determined by the above equation (7) as:

rd_B_addr＝floor(149/(64/8×4))＝floor(4.7)＝4

i.e. the 149 th input data is located at the 4 th address location. Specifically, which address unit 4 in the RAM is determined by the following content.

Because there are multiple input data serial numbers corresponding to the sliding window serial number, the read address line corresponding to the sliding window serial number can be determined based on each input data serial number, and the read address lines corresponding to the sliding window determined based on different input data serial numbers may be the same or different. In the embodiment of the present invention, the same read address line is recorded as one address line, and the number of the read address lines corresponding to the sliding window may be one or more than one.

In an optional embodiment, the extracting, according to the input data sequence number corresponding to the sliding window sequence number, the read port data bit width and the write port data bit width of the RAM, the number of RAMs in each RAM group, and the determined read address line, corresponding sliding window data from the read storage data includes:

and for any input data serial number in the input data serial numbers corresponding to the sliding window serial numbers, determining a read RAM according to the input data serial number, the read port data bit width and the write port data bit width of the RAM, the number of RAMs in each RAM group and a read address line determined based on the input data serial number.

In the embodiment of the invention, for any input data serial number in the input data serial numbers corresponding to the sliding window serial number, the write port data bit width and the read port data bit width of the RAM, and the number of RAMs in each RAM group, the read address line corresponding to the sliding window serial number is determined, and then the read RAM is determined according to the input data serial number, the write port data bit width and the read port data bit width of the RAM, the number of RAMs in each RAM group and the read address line corresponding to the sliding window.

Alternatively, the read RAM is determined according to the following equation (8):

k＝floor((rd_data_num-rd_B_addr×M×lenB/lenA)/(lenB/lenA)) (8)

wherein k represents the serial number of the read RAM corresponding to the serial number of the input data; rd _ B _ addr represents a read address line corresponding to the sliding window determined based on the input data sequence number, and rd _ data _ num represents the input data sequence number; lenA is the data bit width of a write port of the RAM; lenB is the read port data bit width of the RAM; m is the number of RAMs in each RAM group; floor denotes rounding down.

Taking the 149 th input data as an example, if the serial number of the address unit in the RAM where the input data is located is 4, that is, the read address line is 4, then the serial number k of the RAM occupied by the input data is:

k＝floor((149-4×4×64/8)/(64/8))＝floor(21/8)＝floor(2.6)＝2

i.e., the 149 th input data is located at the 4 th address location in the 2 nd RAM (i.e., RAM 2).

And determining the specific position of the input data corresponding to the input data serial number in the storage position corresponding to the read address line based on the read address line and the read RAM determined by the input data serial number according to the input data serial number, the read port data bit width and the write port data bit width of the RAM and the number of RAMs in each RAM group.

Optionally, the specific position of the input data corresponding to the input data sequence number in the storage location corresponding to the read address line may be determined according to the following formula (9):

w＝rd_data_num-rd_B_addr×M×lenB/lenA-k×lenB/lenA (9)

wherein w represents the specific location of the input data in the address unit; k represents the serial number of the read RAM; rd _ B _ addr represents a read address line determined based on the input data sequence number, and rd _ data _ num represents the input data sequence number; lenA is the data bit width of a write port of the RAM; lenB is the read port data bit width of the RAM; m is the number of RAMs in each RAM group.

Taking the 149 th input data as an example, if the serial number of the address unit in which the input data is located in the RAM is 4, then the serial number of the read RAM in which the input data is located is 2, and the position w of the input data in the address unit No. 4 is:

w＝149-4×4×64/8-2×64/8＝149-128-16＝5

that is, the 149 th input data is located at the 5 th position (counted from left to right, numbering starting from 0) of the 4 th address location in the 2 nd memory location RAM2 of the RAM bank.

After the serial number k of the read RAM corresponding to the input data serial number and the position w of the data corresponding to the input data serial number in the address unit corresponding to the read address line are determined, the sliding window data can be extracted from the read storage data. In the embodiment of the present invention, when the number of the determined read address lines is greater than one, since each part of the sliding window data extracted from the storage data read from different RAM banks needs to be spliced, the start position and the end position of the splicing need to be determined, in the following manner:

determining a starting input data serial number and an ending input data serial number of an input data serial number corresponding to the window data serial number;

determining a sequence number k (for convenience of distinguishing and marked as k _1) of a read RAM corresponding to the initial input data sequence number, a read address line rd _ B _ addr (for convenience of distinguishing and marked as rd _ B _ addr _1) and a position w (for convenience of distinguishing and marked as w _1) of data corresponding to the input data sequence number in an address unit corresponding to the read address line;

determining a sequence number k (for convenience of distinguishing and recorded as k _2) of a read RAM corresponding to an input data sequence number, a read address line rd _ B _ addr (for convenience of distinguishing and recorded as rd _ B _ addr _2) and a position w (for convenience of distinguishing and recorded as w _2) of data corresponding to the input data sequence number in an address unit corresponding to the read address line;

if the read address line rd _ B _ addr _1 corresponding to the initial input data sequence number is the same as the read address line rd _ B _ addr _2 corresponding to the ending input data sequence number, all the data corresponding to the window data sequence number are extracted from one RAM group: extracting data from the position w _1 of an address unit corresponding to the address line rd _ B _ addr _1 of the kth RAM until the end of the position w _2 of the address unit corresponding to the address line rd _ B _ addr _2 of the kth RAM, and splicing the extracted data according to the extraction sequence;

if the read address line rd _ B _ addr _1 corresponding to the initial input data sequence number is different from the read address line rd _ B _ addr _2 corresponding to the ending input data sequence number, data needs to be extracted from two RAM banks, data in an address unit corresponding to the read address line rd _ B _ addr _1 is extracted from one RAM bank (for convenience of description, denoted as a first RAM bank), and data in an address unit corresponding to the read address line rd _ B _ addr _2 is extracted from the other RAM bank (for convenience of description, denoted as a second RAM bank), which specifically includes: in the first RAM group, the extracted data includes: starting from the position w _1 of the address unit corresponding to the address line rd _ B _ addr _1 in the kth RAM to the last position of the address unit corresponding to the address line rd _ B _ addr _1 in the Mth RAM; in the second RAM group, the extracted data includes: starting from the 1 st position of the address unit corresponding to the read address line rd _ B _ addr _2 in the 0 th RAM, the data of the position w _2 of the address unit corresponding to the read address line rd _ B _ addr _2 in the k _2 th RAM. And splicing the acquired data according to the sequence that the address lines are from small to large and the RAM serial numbers are from small to large.

It should be noted that the above splicing scheme is only an optional implementation manner, and in particular, there are other implementation manners, as long as the number of the determined read address lines is greater than one, the storage data in the storage locations corresponding to different read address lines are read in different RAM banks; and splicing all parts of the sliding window data extracted from the storage data read from different RAM groups to ensure that the input data serial number in the spliced data is the same as the input data serial number corresponding to the sliding window.

The following illustrates a specific implementation of the splicing scheme:

assuming that the input data sequence number corresponding to the sliding window sequence number is from 121- "140", i.e. the initial input data sequence number is 121, and the ending input data sequence number is 140, then:

based on formula (7), it can be determined that the read address line rd _ B _ addr _1 corresponding to the initial input data sequence number 121 is 3, based on formula (8), it can be determined that the sequence number of the read RAM corresponding to the initial input data sequence number 121 is 3, and based on formula (9), it can be determined that the position w _1 of the input data corresponding to the input data sequence number 121 corresponding to the initial input data sequence number 121 in the address unit corresponding to the read address line rd _ B _ addr _1 is 1.

It may be determined that the read address line rd _ B _ addr _2 corresponding to the ending input data sequence number 140 is 4 based on equation (7), the sequence number k _2 of the read RAM corresponding to the ending input data sequence number 140 is 1 based on equation (8), and the position w _2 of the input data corresponding to the input data sequence number 140 corresponding to the ending input data sequence number 140 in the address cell corresponding to the read address line rd _ B _ addr _2 is 4 based on equation (9).

In this example, if the read address line rd _ B _ addr _1 corresponding to the initial input data sequence number is different from the read address line rd _ B _ addr _2 corresponding to the final input data sequence number, data needs to be extracted from two RAM groups, which may specifically be: in the first RAM group, the extracted data includes: starting from position 1 of an address unit corresponding to the No. 3 reading address line in the No. 3 RAM, and reading data in the last position of the address unit corresponding to the No. 3 reading address line in the No. 3 RAM; in the second RAM group, the extracted data includes: starting from the 0 th position of the address unit corresponding to the read address line No. 4 in the 0 th RAM, and continuing to the data in the 4 th position of the address unit corresponding to the read address line No. 4 in the 1 st RAM. And splicing the acquired data according to the sequence that the address lines are from small to large and the RAM serial numbers are from small to large. Based on this, the spliced data is the input data corresponding to the input data sequence number 121-140.

For another example, if the input data sequence number corresponding to the sliding window sequence number is from 169-188, that is, the initial input data sequence number is 169, and the ending input data sequence number is 188, then:

based on equation (7), it can be determined that the read address line rd _ B _ addr _1 corresponding to the start input data sequence number 169 is 5, based on equation (8), it can be determined that the sequence number of the read RAM corresponding to the start input data sequence number 169 is 1, and based on equation (9), it can be determined that the position w _1 of the input data corresponding to the input data sequence number 169 corresponding to the start input data sequence number 169 in the address cell corresponding to the read address line rd _ B _ addr _1 is 1.

Based on equation (7), it may be determined that the read address line rd _ B _ addr _2 corresponding to the end input data sequence number 188 is 5, based on equation (8), it may be determined that the sequence number k _2 of the read RAM corresponding to the end input data sequence number 188 is 3, and based on equation (9), it may be determined that the position w _2 of the input data corresponding to the input data sequence number 188 corresponding to the end input data sequence number 188 in the address unit corresponding to the read address line rd _ B _ addr _2 is 4.

In this example, the read address line rd _ B _ addr _1 corresponding to the initial input data sequence number is the same as the read address line rd _ B _ addr _2 corresponding to the final input data sequence number, and all data can be extracted from one RAM group: and (3) extracting data from the position 1 of the address unit corresponding to the No. 5 reading address line of the No. 1 RAM in the first RAM group until the position 4 of the address unit corresponding to the No. 5 reading address line of the No. 3 RAM is finished, and splicing the extracted data according to the extraction sequence, wherein the spliced data is the input data with the input data sequence number corresponding to 169-188.

Corresponding to the method embodiment, an embodiment of the present invention further provides a data processing apparatus, and a schematic structural diagram of the data processing apparatus according to the embodiment of the present invention is shown in fig. 4, and the data processing apparatus may include:

a write address determining module 41, a write data module 42, a serial number determining module 43, a read address line determining module 44, a read data module 45 and a data extracting module 46; wherein the content of the first and second substances,

the write address line determining module 41 is configured to divide the original data into input data with the same length, number the input data in sequence, and determine a write address line according to pre-configuration information and an input data sequence number in each write clock cycle; the pre-configuration information includes: the number of RAMs in each RAM group, the width of a write address line of the RAM, and the bit width of write port data and the bit width of read port data of the RAM; the number of the RAM groups is determined according to the bit width of the sliding window data, the number of the RAMs in each RAM group, the bit width of the write port data of the RAM and the bit width of the read port data of the RAM; or, the number of RAMs in each RAM group, the bit width of the write port data of the RAM and the bit width of the read port data are determined according to the number of the RAM groups and the bit width of the sliding window data;

the data writing module 42 is configured to determine a write RAM according to the input data serial number, the number of RAMs in each RAM group, and a write port data bit width and a read port data bit width of the RAM, and write input data corresponding to the input data serial number in accordance with the determined write address line and the write RAM;

the sequence number determining module 43 is configured to determine a sequence number of the sliding window in each read clock cycle when data needs to be read after all input data are written;

the read address line determining module 44 is configured to determine a read address line corresponding to the sliding window sequence number according to the input data sequence number corresponding to the sliding window sequence number, the read port data bit width and the write port data bit width of the RAM, and the number of RAMs in each RAM group;

the read data module 45 is configured to read storage data from a storage location corresponding to the determined read address line; when the number of the determined read address lines is more than one, reading storage data in storage positions corresponding to different read address lines in different RAM groups;

the data extraction module 46 is configured to extract corresponding sliding window data from the read storage data according to the input data serial number corresponding to the sliding window serial number, the read port data bit width and the write port data bit width of the RAM, the number of RAMs in each RAM group, and the determined read address line; when the number of the determined read address lines is more than one, extracting all parts of the sliding window data from the storage data read from different RAM groups for splicing to obtain corresponding sliding window data.

The data processing device provided by the embodiment of the invention stores at least two parts of original data, wherein each part of original data is distributed and stored in a plurality of RAMs (namely RAM groups), so that when the data covered by the sliding window occupies a plurality of address units, different parts of the data covered by the sliding window can be simultaneously read from the plurality of RAM groups, and the parallel reading of the data of the sliding window in one reading clock cycle is realized, thereby improving the data processing efficiency of the embedded system.

In an optional embodiment, the write address line determining module 41 is specifically configured to, when determining the write address line according to the pre-configuration information and the input data sequence number:

the write address line is determined according to the following equation:

In an optional embodiment, the number of the RAM groups, the bit width of the sliding window data, the number of RAMs included in each RAM group, and the write port data bit width and the read port data bit width of the RAM satisfy the following relationship:

R≥(P-lenA+lenB)/(M×lenB)

In an optional embodiment, the data writing module 42 is specifically configured to, when determining to write to the RAM:

the write RAM is determined according to the following equation:

wherein, RAM _ num represents the serial number of the write RAM;

when we _ v is 1, the write port of the write RAM is enabled;

wr _ data _ num [ log2(M) + log2(lenB/lenA) -1: log2(lenB/lenA) ] represents data of log2(M) + log2(lenB/lenA) -1 bit to log2(lenB/lenA) bit of wr _ data _ num; wr _ data _ num represents an input data sequence number; lenA is the data bit width of a write port of the RAM; lenB is the read port data bit width of the RAM; m is the number of RAMs in each RAM group.

In an optional embodiment, when the write data module 42 writes the input data corresponding to the input data sequence number according to the determined write address line and the write RAM, it is specifically configured to:

In an alternative embodiment, the read address line determination module 44 is specifically configured to:

rd_B_addr＝floor(rd_data_num/(lenB/lenA×M))

In an optional embodiment, when the data extraction module 46 extracts corresponding sliding window data from the read storage data according to the input data serial number corresponding to the sliding window serial number, the read port data bit width and the write port data bit width of the RAM, the number of RAMs in each RAM group, and the determined read address line, the data extraction module is specifically configured to:

In an alternative embodiment, when determining to read the RAM, the data extraction module 46 is specifically configured to:

the read RAM is determined according to the following equation:

k＝floor((rd_data_num-rd_B_addr×M×lenB/lenA)/(lenB/lenA))

In an optional embodiment, when determining that the input data corresponding to the input data sequence number is at a specific position in the storage location corresponding to the read address line, the data extracting module 46 is specifically configured to:

determining the specific position of the input data corresponding to the input data sequence number in the storage position corresponding to the read address line according to the following formula:

w＝rd_data_num-rd_B_addr×M×lenB/lenA-k×lenB/lenA

The data processing device provided by the embodiment of the invention can be applied to electronic equipment. Alternatively, fig. 5 shows a block diagram of a hardware structure of the electronic device, and referring to fig. 5, the hardware structure of the electronic device may include: at least one processor 1, at least one communication interface 2, at least one memory 3 and at least one communication bus 4;

in the embodiment of the present invention, the number of the processor 1, the communication interface 2, the memory 3, and the communication bus 4 is at least one, and the processor 1, the communication interface 2, and the memory 3 complete mutual communication through the communication bus 4;

the processor 1 may be a central processing unit CPU, or an application Specific Integrated circuit asic, or one or more Integrated circuits configured to implement embodiments of the present invention, etc.;

the memory 3 may include a high-speed RAM memory, and may further include a non-volatile memory (non-volatile memory) or the like, such as at least one disk memory;

wherein the memory stores a program and the processor can call the program stored in the memory, the program for:

dividing original data into input data with the same length, numbering the input data in sequence, and determining a write address line according to pre-configuration information and an input data sequence number in each write clock cycle; the pre-configuration information includes: the number of RAMs in each RAM group, the width of a write address line of the RAM, and the bit width of write port data and the bit width of read port data of the RAM; the number of the RAM groups is determined according to the bit width of the sliding window, the number of the RAMs in each RAM group, the bit width of write port data and the bit width of read port data of the RAMs; or, the number of RAMs in each RAM group, the bit width of the write port data of the RAM and the bit width of the read port data are determined according to the number of the RAM groups and the bit width of the sliding window data;

Alternatively, the detailed function and the extended function of the program may be as described above.

An embodiment of the present invention further provides a storage medium, where the storage medium may store a program suitable for being executed by a processor, where the program is configured to:

Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.

In the embodiments provided by the present invention, it should be understood that the disclosed system (if any), apparatus and method may be implemented in other ways. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.

It should be understood that the embodiments of the present invention can be combined with each other from the drawings, the embodiments and the features to solve the above technical problems.

The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A data processing method, comprising:

2. The method of claim 1, wherein determining the write address line based on the pre-configuration information and the input data sequence number comprises:

the write address line is determined according to the following equation:

3. The method according to claim 1, wherein the number of RAM groups, the bit width of the sliding window data, the number of RAMs included in each RAM group, and the write port data bit width and the read port data bit width of the RAM satisfy the following relationship:

R≥(P-lenA+lenB)/(M×lenB)

4. The method of claim 1, wherein determining a write RAM based on an input data sequence number, a number of RAMs in each RAM bank, and a write port data bit width and a read port data bit width of each RAM comprises:

the write RAM is determined according to the following equation:

wherein, RAM _ num represents the serial number of the write RAM;

when we _ v is 1, the write port of the write RAM is enabled;

5. The method of claim 4, wherein writing the input data corresponding to the input data sequence number according to the determined write address line and write RAM comprises:

6. The method of claim 1, wherein determining the read address line corresponding to the sliding window number according to the input data number corresponding to the sliding window number, the read port data bit width and the write port data bit width of the RAM, and the number of RAMs in each RAM bank comprises:

rd_B_addr＝floor(rd_data_num/(lenB/lenA×M))

7. The method as claimed in claim 6, wherein said extracting corresponding sliding window data from the read storage data according to the input data sequence number corresponding to the sliding window sequence number, the read port data bit width and the write port data bit width of the RAM, the number of RAMs in each RAM bank and the determined read address line comprises:

8. The method of claim 7, wherein determining to read the RAM comprises: the read RAM is determined according to the following equation:

k＝floor((rd_data_num-rd_B_addr×M×lenB/lenA)/(lenB/lenA))

9. The method of claim 7, wherein determining the specific location of the input data corresponding to the input data sequence number in the memory location corresponding to the read address line comprises: determining the specific position of the input data corresponding to the input data sequence number in the storage position corresponding to the read address line according to the following formula:

w＝rd_data_num-rd_B_addr×M×lenB/lenA-k×lenB/lenA

10. A data processing apparatus, comprising: