CN117807361A - Fast fourier transform method, apparatus and digital hearing aid - Google Patents
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Abstract
The application relates to a fast Fourier transform method, a fast Fourier transform device and a digital hearing aid, wherein the fast Fourier transform device comprises a first memory for storing original FFT data, a second memory for storing intermediate results of butterfly operation and a third memory; the method comprises the steps of performing a 1 st level butterfly operation based on a result obtained after original FFT data shift, and outputting an intermediate result of the 1 st level butterfly operation; performing shift processing when reading the intermediate result; performing an ith butterfly operation based on the result obtained after the intermediate result of the last butterfly operation is shifted, and outputting an intermediate result of the ith butterfly operation; wherein I is more than or equal to 2 and less than or equal to I, I represents the total number of stages of butterfly operation, and I is a positive integer; the intermediate results are sequentially rotated into the second memory and the third memory. By performing shift processing in advance before butterfly operation, two memories are used for storing intermediate results of the butterfly operation, so that the storage area and power consumption of the intermediate results are reduced, and the problem that the storage area and power consumption of the intermediate results are large is solved.
Description
Technical Field
The present application relates to the field of digital signal processing technologies, and in particular, to a fast fourier transform method, apparatus, and digital hearing aid.
Background
The fast fourier transform (Fast Fourier Transform, FFT) is a fast implementation algorithm for converting data from a time domain to a frequency domain for processing, and is widely applied to the fields of digital images, wireless communication, voice recognition, radar signal processing and the like at present, and generally needs to meet the requirements of high precision, low delay, low power consumption data and the like.
In the calculation process of the fast fourier transform, the storage mode of the intermediate quantity result can influence the overall calculation speed and the power consumption. In the traditional scheme, the intermediate result is generally stored in a register set or a static memory (SRAM), and along with the increase of the number of memories (RAMs) and the increase of the capacity, the more resources can be used correspondingly, but larger power consumption and area occupation are brought at the same time, so that the method is difficult to be applied to the fields with high requirements on power consumption and area.
Aiming at the problem of larger area and power consumption for storing intermediate results in the related art, no effective solution is proposed at present.
Disclosure of Invention
In view of the foregoing, it is desirable to provide a fast fourier transform method, apparatus and digital hearing aid that can reduce the power consumption and area for storing intermediate results.
In a first aspect, in this embodiment, there is provided a fast fourier transform method, which is applicable to a fast fourier transform apparatus, and the apparatus includes: a first memory storing original FFT data, a second memory storing intermediate results of butterfly operations, and a third memory; the method comprises the following steps:
performing a level 1 butterfly operation based on the shifted result of the original FFT data, and outputting an intermediate result of the level 1 butterfly operation;
performing shift processing when reading the intermediate result;
performing an ith butterfly operation based on the result obtained after the intermediate result of the last butterfly operation is shifted, and outputting an intermediate result of the ith butterfly operation; wherein I is more than or equal to 2 and less than or equal to I, I represents the total number of stages of butterfly operation, and I is a positive integer;
and sequentially and cyclically storing the intermediate result into the second memory and the third memory.
In a second aspect, in this embodiment, there is provided a fast fourier transform method, which is applicable to a fast fourier transform apparatus, the apparatus including: a first memory for storing original FFT data, a second memory for storing the result after the shift of the butterfly operation intermediate result, and a third memory; the method comprises the following steps:
Performing a 1 st level butterfly operation based on the original FFT data, and outputting an intermediate result of the 1 st level butterfly operation;
performing an ith butterfly operation based on the result obtained after the intermediate result of the last butterfly operation is shifted, and outputting an intermediate result of the ith butterfly operation; wherein I is more than or equal to 2 and less than or equal to I, I represents the total number of stages of butterfly operation, and I is a positive integer;
performing shift processing on the intermediate result;
and sequentially and cyclically storing the results after the intermediate result shift into the second memory and the third memory.
In some of these embodiments, further comprising:
and after each stage of butterfly operation is finished, performing high-order detection on the output intermediate result to update the shift value of the shift processing.
In some of these embodiments, said high-level detecting of said intermediate result of said outputting to update a shift value of said shifting process comprises:
calculating a preset high-order value in the intermediate result and a preset register, and updating a current calculation result in the preset register;
and after each stage of butterfly operation is finished, determining the shift value according to the current operation result.
In some of these embodiments, further comprising:
Dividing each level of butterfly operation in the fast Fourier transform, and generating a ping-pong selection signal corresponding to each level of butterfly operation.
In some of these embodiments, further comprising:
and based on the ping-pong selection signal and the read-write address of each memory, sequentially and cyclically writing the intermediate result or the result after the intermediate result is shifted into the second memory and the third memory.
In a third aspect, in this embodiment, there is provided a fast fourier transform apparatus, including: the device comprises a shift detection module, a first memory, a second memory, a third memory, an address generation module and a butterfly operation module, wherein the first memory, the second memory, the third memory, the address generation module and the butterfly operation module are respectively connected with the shift detection module;
the first memory is used for storing original FFT data;
the shift detection module is used for carrying out shift processing when the butterfly operation module reads data to be calculated;
the address generation module is used for generating read-write addresses of the first memory, the second memory and the third memory;
the butterfly operation module is used for carrying out the level 1 butterfly operation based on the result after the FFT data shift and outputting the intermediate result of the level 1 butterfly operation; and performing the ith butterfly operation based on the result of the shift of the intermediate result of the previous butterfly operation, and outputting the intermediate result of the ith butterfly operation; wherein I is more than or equal to 2 and less than or equal to I, I represents the total number of stages of butterfly operation, and I is a positive integer;
The second memory and the third memory are used for sequentially and cyclically storing intermediate results output by the butterfly operation module.
In a fourth aspect, in this embodiment, there is provided a fast fourier transform apparatus, including: the device comprises a shift detection module, a first memory, a second memory, a third memory, an address generation module and a butterfly operation module, wherein the first memory, the second memory, the third memory, the address generation module and the butterfly operation module are respectively connected with the shift detection module;
the first memory is used for storing original FFT data;
the address generation module is used for generating read-write addresses of the first memory, the second memory and the third memory;
the butterfly operation module is used for carrying out the 1 st level butterfly operation based on the original FFT data and outputting the intermediate result of the 1 st level butterfly operation; and performing the ith butterfly operation based on the result of the shift of the intermediate result of the previous butterfly operation, and outputting the intermediate result of the ith butterfly operation; wherein I is more than or equal to 2 and less than or equal to I, I represents the total number of stages of butterfly operation, and I is a positive integer;
the shift detection module is used for carrying out shift processing on the intermediate result output by the butterfly operation module;
The second memory and the third memory are used for sequentially and cyclically storing the results after the intermediate result shift.
In some embodiments, the butterfly operation module is a base 2 operation module, and the second memory and the third memory are single-port RAM; or,
the butterfly operation module is a base 4 operation module, and the second memory and the third memory are dual-port RAMs.
In a fifth aspect, in this embodiment there is provided a digital hearing aid comprising a fast fourier transform device as described in the third or fourth aspect above.
Compared with the related art, the fast Fourier transform method, the fast Fourier transform device and the digital hearing aid provided in the embodiment, wherein the fast Fourier transform device comprises a first memory for storing original FFT data, a second memory for storing intermediate results of butterfly operation and a third memory; the method is suitable for the device and comprises the following steps: performing a level 1 butterfly operation based on the shifted result of the original FFT data, and outputting an intermediate result of the level 1 butterfly operation; performing shift processing when reading the intermediate result; performing an ith butterfly operation based on the result obtained after the intermediate result of the last butterfly operation is shifted, and outputting an intermediate result of the ith butterfly operation; wherein I is more than or equal to 2 and less than or equal to I, I represents the total number of stages of butterfly operation, and I is a positive integer; and sequentially and cyclically storing the intermediate result into the second memory and the third memory. According to the method and the device, the shift processing is performed in advance when the data are read to perform butterfly operation, the two memories are adopted to sequentially store the intermediate result of each level of butterfly operation in a rotating mode, the storage area and the power consumption of the intermediate result can be reduced, and the problem that the current storage area and the power consumption of the intermediate result are large is solved.
The details of one or more embodiments of the application are set forth in the accompanying drawings and the description below to provide a more thorough understanding of the other features, objects, and advantages of the application.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute an undue limitation to the application. In the drawings:
FIG. 1 is a block diagram of the hardware architecture of a terminal of a fast Fourier transform method in one embodiment;
FIG. 2 is a flow diagram of a fast Fourier transform method in one embodiment;
FIG. 3 is a flow chart of a fast Fourier transform method in another embodiment;
FIG. 4 is a flow chart of a fast Fourier transform method in yet another embodiment;
FIG. 5 is a flow chart of a fast Fourier transform method in yet another embodiment;
FIG. 6 is a schematic diagram of a fast Fourier transform device in one embodiment;
FIG. 7 is a schematic diagram of an address generation module output signal in one embodiment;
FIG. 8 is a schematic diagram of data processing in a shift detection module in one embodiment;
fig. 9 is a schematic diagram of the structure of radix-4 butterfly in a fast fourier transform apparatus in one embodiment.
In the figure: 102. a processor; 104. a memory; 106. a transmission device; 108. and an input/output device.
Detailed Description
For a clearer understanding of the objects, technical solutions and advantages of the present application, the present application is described and illustrated below with reference to the accompanying drawings and examples.
Unless defined otherwise, technical or scientific terms used herein shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terms "a," "an," "the," "these," and the like in this application are not intended to be limiting in number, but rather are singular or plural. The terms "comprising," "including," "having," and any variations thereof, as used in the present application, are intended to cover a non-exclusive inclusion; for example, a process, method, and system, article, or apparatus that comprises a list of steps or modules (units) is not limited to the list of steps or modules (units), but may include other steps or modules (units) not listed or inherent to such process, method, article, or apparatus. The terms "connected," "coupled," and the like in this application are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. Reference to "a plurality" in this application means two or more. "and/or" describes an association relationship of an association object, meaning that there may be three relationships, e.g., "a and/or B" may mean: a exists alone, A and B exist together, and B exists alone. Typically, the character "/" indicates that the associated object is an "or" relationship. The terms "first," "second," "third," and the like, as referred to in this application, merely distinguish similar objects and do not represent a particular ordering of objects.
The method embodiments provided in the present embodiment may be executed in a terminal, a computer, or similar computing device. For example, the present invention is operated on a terminal such as a digital hearing aid, and fig. 1 is a block diagram of the hardware configuration of the terminal of the fast fourier transform method of the present embodiment. As shown in fig. 1, the terminal may include one or more (only one is shown in fig. 1) processors 102 and a memory 104 for storing data, wherein the processors 102 may include, but are not limited to, processing devices such as MCUs (Microcontroller Unit, microprocessors) or FPGAs (Field Programmable Gate Array, programmable logic devices). The terminal may also include a transmission device 106 for communication functions and an input-output device 108. It will be appreciated by those skilled in the art that the structure shown in fig. 1 is merely illustrative and is not intended to limit the structure of the terminal. For example, the terminal may also include more or fewer components than shown in fig. 1, or have a different configuration than shown in fig. 1.
The memory 104 may be used to store a computer program, for example, a software program of application software and a module, such as a computer program corresponding to the fast fourier transform method in the present embodiment, and the processor 102 executes the computer program stored in the memory 104, thereby performing various functional applications and data processing, that is, implementing the above-described method. Memory 104 may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include memory remotely located relative to the processor 102, which may be connected to the terminal via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
The transmission device 106 is used to receive or transmit data via a network. The network includes a wireless network provided by a communication provider of the terminal. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, simply referred to as NIC) that can connect to other network devices through a base station to communicate with the internet. In one example, the transmission device 106 may be a Radio Frequency (RF) module, which is configured to communicate with the internet wirelessly.
The fast fourier transform (Fast Fourier Transform, FFT) is a fast implementation algorithm for converting data from a time domain to a frequency domain for processing, and is widely applied to the fields of digital images, wireless communication, voice recognition, radar signal processing and the like at present, and generally needs to meet the requirements of high precision, low delay, low power consumption data and the like.
In the calculation process of the fast fourier transform, the storage mode of the intermediate quantity result can influence the overall calculation speed and the power consumption. In the traditional scheme, the intermediate result is generally stored in a register set or a static memory (SRAM), and along with the increase of the number of memories (RAMs) and the increase of the capacity, the more resources can be used correspondingly, but larger power consumption and area occupation are brought at the same time, so that the method is difficult to be applied to the fields with high requirements on power consumption and area.
In this embodiment, a fast fourier transform method is provided, which is applicable to a fast fourier transform device, and the device includes: a first memory storing original FFT data, and a second memory and a third memory storing intermediate results of butterfly operations. Fig. 2 is a flowchart of the fast fourier transform method in this embodiment, and as shown in fig. 2, the method includes the following steps:
step S210, performing a level 1 butterfly operation based on the shifted result of the original FFT data, and outputting an intermediate result of the level 1 butterfly operation.
Specifically, when original FFT data is read from the first memory based on the address of the first memory, shift processing is performed on the original FFT data. And performing the 1 st level butterfly operation based on the shifted result of the original FFT data, and outputting an intermediate result of the 1 st level butterfly operation. In the level 1 butterfly operation, a shift value for performing shift processing on original FFT data is determined by the amplitude of the original FFT data and the level 1 butterfly operation, the level 1 butterfly operation is performed after the original FFT data is shifted, so that no overflow of subsequent operations is ensured, and the shift value is set to 2 bits, that is, shift processing of shifting to the right by 2 bits is performed when the original FFT data is read.
The method in this embodiment is applicable to radix-2 butterfly and radix-4 butterfly. The difference between the radix-2 butterfly operation and the radix-4 butterfly operation is that for a sequence of N points, the sequence is divided into two parts each time in the radix-2 butterfly operation, and the sequence of N points is expressed as a linear combination of two sequences of N/2 points; the sequence is divided into four at a time in the radix-4 butterfly operation, and the sequence of N points is expressed as a linear combination of four N/4 point sequences.
Step S220, performing shift processing when reading the intermediate result; performing an ith butterfly operation based on the result obtained after the intermediate result of the last butterfly operation is shifted, and outputting an intermediate result of the ith butterfly operation; wherein I is greater than or equal to 2 and less than or equal to I, I represents the total number of stages of butterfly operation, and I is a positive integer.
Specifically, when the intermediate result of the butterfly operation of the previous stage is read from the second memory or the third memory based on the addresses of the second memory and the third memory, the intermediate result is subjected to shift processing. And performing the ith butterfly operation based on the result after the intermediate result is shifted, and outputting the intermediate result of the ith butterfly operation. Wherein, I represents the total number of stages of butterfly operation, and the relation with the FFT point number N is as follows:
in the ith butterfly operation, a shift value for shifting the intermediate result of the previous stage is determined by the butterfly operation of the previous stage, and is updated after each stage of butterfly operation, so that no overflow of subsequent operations is ensured.
Step S230, the intermediate result is sequentially rotated and stored in the second memory and the third memory.
Specifically, a second memory and a third memory are arranged for storing intermediate results of each level of butterfly operation, and for each level of butterfly operation, read-write operations in the operation process are distributed to different memories through ping-pong operations, so that data read-write collision is avoided when butterfly operation is performed.
For the 1 st level butterfly operation, original FFT data is read from a first memory and shifted, and an intermediate result output by the butterfly operation is input into a second memory or a third memory. Taking the example of inputting the intermediate result into the second memory, for the 2 nd-stage butterfly operation, reading the intermediate result of the 1 st-stage butterfly operation from the second memory, performing shift processing, storing the intermediate result output by the butterfly operation into the third memory, sequentially executing each stage of butterfly operation, and performing each time of reading and writing on the two memories respectively, so as to realize that the intermediate result is sequentially stored into the second memory and the third memory in a rotating manner until the Fourier transform calculation is completed.
Through the steps, when the butterfly operation is performed on the read data, the shift processing is performed in advance, the subsequent operation can be guaranteed not to overflow, meanwhile, the two memories are adopted to sequentially store the intermediate result of each level of butterfly operation in a rotating mode, the conflict of data reading and writing in each level of butterfly operation is reduced, meanwhile, the storage area and the power consumption of the intermediate result can be reduced, and the problem that the storage area and the power consumption of the intermediate result are larger at present is solved.
In this embodiment, a fast fourier transform method is provided, which is applicable to a fast fourier transform device, and the device includes: a first memory storing original FFT data, and a second memory and a third memory storing shifted results of butterfly intermediate results. Fig. 3 is a flowchart of the fast fourier transform method in this embodiment, and as shown in fig. 3, the method includes the steps of:
step S310, performing a level 1 butterfly operation based on the original FFT data, and outputting an intermediate result of the level 1 butterfly operation.
Specifically, based on the address of the first memory, the original FFT data is read from the first memory to perform the 1 st stage butterfly operation, and the intermediate result of the 1 st stage butterfly operation is output.
The method in this embodiment is applicable to radix-2 butterfly and radix-4 butterfly. The difference between the radix-2 butterfly operation and the radix-4 butterfly operation is that for a sequence of N points, the sequence is divided into two parts each time in the radix-2 butterfly operation, and the sequence of N points is expressed as a linear combination of two sequences of N/2 points; the sequence is divided into four at a time in the radix-4 butterfly operation, and the sequence of N points is expressed as a linear combination of four N/4 point sequences.
Step S320, performing the ith butterfly operation based on the result of the shift of the intermediate result of the previous butterfly operation, and outputting the intermediate result of the ith butterfly operation; wherein I is greater than or equal to 2 and less than or equal to I, I represents the total number of stages of butterfly operation, and I is a positive integer.
Specifically, based on the addresses of the second memory and the third memory, the intermediate result of the butterfly operation of the previous stage is read from the second memory or the third memory to perform the butterfly operation of the ith stage, and the intermediate result of the butterfly operation of the ith stage is output. Wherein, I represents the total number of stages of butterfly operation, and the relation with the FFT point number N is as follows:
step S330, performing shift processing on the intermediate result; and sequentially and cyclically storing the results after the intermediate result shift into a second memory and a third memory.
Specifically, after the intermediate result of each level of butterfly operation is shifted, the intermediate result is stored in a corresponding memory. In the level 1 butterfly operation, a shift value for shifting the intermediate result is determined by the amplitude of the FFT data and the level 1 butterfly operation, so that the subsequent operation is guaranteed not to overflow, and the shift value is set to be 2 bits, that is, shift processing for shifting the intermediate result by 2 bits to the right is performed before the intermediate result is stored in the memory. In the ith butterfly operation, the shift value for shifting the intermediate result is determined by the last butterfly operation and updated after each butterfly operation, so that the subsequent operations are ensured not to overflow.
The second memory and the third memory are used for storing the result after the intermediate result of each level butterfly operation is shifted, and for each level butterfly operation, the read-write operation in the operation process is distributed to different memories through the ping-pong operation, so that the read-write of data can not conflict when the butterfly operation is performed.
For the 1 st level butterfly operation, original FFT data is read from a first memory, and the output intermediate result after shifting is input into a second memory or a third memory. Taking the example of inputting the result after the intermediate result is shifted into the second memory, for the 2 nd-stage butterfly operation, reading the intermediate result of the 1 st-stage butterfly operation from the second memory, shifting the output intermediate result, storing the intermediate result into the third memory, sequentially executing each-stage butterfly operation, and respectively performing each time of reading and writing on the two memories, so as to realize that the intermediate result is sequentially and cyclically stored into the second memory and the third memory until the Fourier transform calculation is completed.
Through the steps, the shift processing is carried out before the intermediate result of each level butterfly operation is written into the memory, so that the subsequent operation can be ensured not to overflow, and meanwhile, the two memories are adopted to sequentially store the result after the intermediate result shift of each level butterfly operation in a rotating way, so that the conflict of data reading and writing in each level butterfly operation is reduced, the storage area and the power consumption of the intermediate result can be reduced, and the problem of larger storage area and power consumption of the intermediate result at present is solved.
In some embodiments thereof, the above method further comprises the steps of:
And after each stage of butterfly operation is finished, performing high-order detection on the output intermediate result to update the shift value of the shift processing.
The method comprises the steps of performing operation on a value of a preset high bit in an intermediate result and a preset register, and updating a current operation result in the preset register; and after each level of butterfly operation is finished, determining a shift value according to the current operation result.
Specifically, the intermediate result of each butterfly operation is stored in the second memory or the third memory, and the intermediate high-order detection is performed to detect whether the high-order occupation exists, if the high-order occupation exists, the bit number of the preset high-order occupied by the maximum value is recorded as a shift value, so that enough valid bits are ensured, and the subsequent operation cannot overflow.
Illustratively, the following is a specific procedure for high-order detection, where dout0, dout1, dout2 … dout127, etc. represent the number of bits of the intermediate result:
(1) Marking a preset register as A [1:0], and enabling an initial value to be 0, wherein A [1:0] =2' b0;
(2) Taking out the highest two bits except the sign bit in dout0[ N:0] (wherein dout0[ N ] is the sign bit), and carrying out the following OR operation with the current preset register A [1:0 ]:
A[1]＝dout0[N-1]|A[1]；
A[0]＝dout0[N-2]|A[0]；
(3) Taking out the highest two bits except sign bits of dout1[ N:0] (wherein dout1[ N ] is sign bit), and carrying out the following OR operation with the current preset register A [1:0 ]:
A[1]＝dout1[N-1]|A[1]；
A[0]＝dout1[N-2]|A[0]；
(4) Repeating the steps (2) and (3), and updating the current operation result in a preset register until dout0, dout1, dout2 … dout127 are all written into the corresponding memories;
(5) When a dividing signal (stage_done) of each stage of butterfly operation in the FFT is received, the preset register A [1:0] is cleared after the shift value is updated.
And after each stage of butterfly operation is finished, determining a shift value according to the current operation result in the preset register.
Wherein:
if the current a [1:0] =2 'b11 or a [1:0] =2' b10 indicates that the high order bit is occupied, updating the shift value to 2bit;
if the current A [1:0] =2' b01 indicates that the high order bit is occupied, updating the shift value to be 1bit;
if the current a [1:0] =2' b00, indicating that the high order bits are not occupied, the shift value is updated to 0bit.
In this embodiment, the intermediate result of each stage of butterfly operation is subjected to high-order detection to update the shift value, and when the intermediate result is subjected to shift processing in each stage of butterfly operation, the shift processing is performed based on the updated shift value, so that sufficient valid bits are ensured, and no overflow occurs in subsequent operations.
In some embodiments, the method further comprises:
dividing each level of butterfly operation in the fast Fourier transform, and generating a ping-pong selection signal corresponding to each level of butterfly operation.
Specifically, a dividing signal (stage_done) for dividing each stage of butterfly operation in the FFT is generated by an address generating module, and a ping-pong selection signal (addr_base) for each stage of butterfly operation is generated. Illustratively, the generation rule of the ping pong selection signal is as follows:
level 1 butterfly operation: selecting a first memory as a read and a second memory as a write;
level 2 butterfly operation: selecting a second memory as a read and a third memory as a write;
level 3 butterfly operation: selecting a third memory as a read and a second memory as a write; sequentially and regularly generating ping-pong selection signals of the common I-level butterfly operation.
In some of these embodiments, the method further comprises the steps of:
based on ping-pong selection signals and read-write addresses of each memory, intermediate results or results after shifting the intermediate results are sequentially written into the second memory and the third memory in a rotating manner.
Specifically, in each butterfly operation, by generating read/write addresses (for example, the read/write addresses are 0-127) in each butterfly operation from the memory, the read/write operations are performed on the two memories based on the ping-pong selection signal, respectively. When the intermediate result is read, shifting is carried out, and the intermediate result output by butterfly operation is sequentially and circularly written into a second memory and a third memory; and when the shift processing is performed during the output of the intermediate result, sequentially and cyclically writing the result obtained after the shift of the butterfly operation output intermediate result into the second memory and the third memory. Illustratively, shift processing is performed when the intermediate result of the previous butterfly operation is read from the second memory, and after butterfly operation is performed, the output intermediate result is input into the third memory; or, after the intermediate result of the last stage of butterfly operation is read from the third memory and subjected to butterfly operation, the intermediate result is output and the intermediate result is shifted to the second memory.
In this embodiment, by performing ping-pong operation, read-write operations are performed on two memories in each butterfly operation, so as to reduce data read-write conflicts, and intermediate results or results after shifting the intermediate results of each butterfly operation are sequentially written into the second memory and the third memory in a rotating manner, so as to reduce power consumption and area occupation of intermediate result storage.
The present embodiment is described and illustrated below by way of preferred embodiments.
Fig. 4 is a flowchart of the fast fourier transform method of the present embodiment, as shown in fig. 4, including the steps of:
in step S410, the original FFT data is read from the first memory and a shift process is performed.
Step S420, based on the shifted result of the original FFT data, performing the level 1 butterfly operation, outputting the intermediate result of the level 1 butterfly operation, and storing the intermediate result in the second memory.
In step S430, the intermediate result of the previous butterfly operation is read from the second memory, and a shift process is performed based on the shift value. Wherein, the shift value is updated by high-order detection after each stage of butterfly operation.
Step S440, performing the 2 nd level butterfly operation based on the shifted result of the intermediate result, outputting the intermediate result of the 2 nd level butterfly operation, and storing the intermediate result in the third memory.
In step S450, in each butterfly operation, the intermediate result is sequentially rotated and stored in the second memory and the third memory.
According to the method and the device, the shift processing is performed in advance when the butterfly operation is performed on the read data, the subsequent operation can be guaranteed not to overflow, meanwhile, the two memories are adopted to sequentially store the intermediate result of each level of butterfly operation in a rotating mode, the conflict of data reading and writing in each level of butterfly operation is reduced, meanwhile, the storage area and the power consumption of the intermediate result can be reduced, the low-power-consumption fast Fourier transform is realized, and the problem that the area and the power consumption of the existing intermediate result are large is solved.
Fig. 5 is a flowchart of the fast fourier transform method of the present embodiment, as shown in fig. 5, including the steps of:
step S510, original FFT data is read from a first memory; and carrying out the 1 st level butterfly operation based on the original FFT data, and outputting an intermediate result of the 1 st level butterfly operation.
Step S520, after shifting the intermediate result of the level 1 butterfly operation, storing the intermediate result in the second memory.
In step S530, the result of the intermediate result shift of the previous butterfly operation is read from the second memory, the 2 nd butterfly operation is performed, and the intermediate result of the 2 nd butterfly operation is output.
Step S540, after the intermediate result of the level 2 butterfly operation is shifted, the intermediate result is stored in the third memory. Wherein, the shift value is updated by high-order detection after each stage of butterfly operation.
In step S550, in each butterfly operation, the result after the intermediate result shift is sequentially rotated and stored in the second memory and the third memory.
Through the steps, the shift processing is carried out before the intermediate result of each level butterfly operation is written into the memory, so that the subsequent operation can be ensured not to overflow, and meanwhile, the two memories are adopted to sequentially store the result after the intermediate result of each level butterfly operation is shifted in a rotating way, so that the conflict of data reading and writing in each level butterfly operation is reduced, the storage area and the power consumption of the intermediate result can be reduced, and the problem of larger storage area and power consumption of the intermediate result at present is solved.
It should be noted that the steps illustrated in the above-described flow or flow diagrams of the figures may be performed in a computer system, such as a set of computer-executable instructions, and that, although a logical order is illustrated in the flow diagrams, in some cases, the steps illustrated or described may be performed in an order other than that illustrated herein.
In this embodiment, a fast fourier transform device is further provided, and the fast fourier transform device is used to implement the foregoing embodiments and preferred embodiments, and will not be described in detail. The terms "module," "unit," "sub-unit," and the like as used below may refer to a combination of software and/or hardware that performs a predetermined function. While the means described in the following embodiments are preferably implemented in software, implementations in hardware, or a combination of software and hardware, are also possible and contemplated.
In this embodiment, a fast fourier transform device is provided, and fig. 6 is a schematic structural diagram of the fast fourier transform device in this embodiment, as shown in fig. 6, where the device includes: the device comprises a displacement detection module, a first memory, a second memory, a third memory, an address generation module and a butterfly operation module, wherein the first memory, the second memory, the third memory, the address generation module and the butterfly operation module are respectively connected with the displacement detection module.
A first memory for storing raw FFT data;
the shift detection module is used for carrying out shift processing when the butterfly operation module reads data to be calculated;
the address generation module is used for generating read-write addresses of the first memory, the second memory and the third memory;
the butterfly operation module is used for carrying out the level 1 butterfly operation based on the result of the original FFT data shift and outputting the intermediate result of the level 1 butterfly operation; and performing the ith butterfly operation based on the result of the shift of the intermediate result of the previous butterfly operation, and outputting the intermediate result of the ith butterfly operation; wherein I is more than or equal to 2 and less than or equal to I, I represents the total number of stages of butterfly operation, and I is a positive integer;
the second memory and the third memory are used for sequentially and cyclically storing intermediate results output by the butterfly operation module.
The address generating module generates the read-write addresses (for example, 0-127) of each memory, converts the read-write addresses into binary marks, and then converts the lowest bit and the highest bit of the binary marks. The data to be calculated comprises the original FFT data required by the butterfly operation or the intermediate result of the last level butterfly operation.
And the butterfly operation module is used for performing shift processing when the original FFT data is read by the shift detection module in the 1 st stage butterfly operation according to the read-write address generated by the address generation module, reading the original FFT data from the first memory, performing shift processing, performing the 1 st stage butterfly operation based on the shifted result (din) of the original FFT data, and outputting the intermediate result (dout) of the 1 st stage butterfly operation. In the level 1 butterfly operation, a shift value for performing shift processing on original FFT data is determined by the amplitude of the FFT data and the level 1 butterfly operation, the level 1 butterfly operation is performed after the original FFT data is shifted, so that no overflow of subsequent operations is ensured, and the shift value is set to 2 bits, that is, shift processing of shifting to the right by 2 bits is performed when the original FFT data is read.
For the ith butterfly operation, a shift detection module performs shift processing on the intermediate result of the last butterfly operation, reads the intermediate result of the last butterfly operation from the second memory or the third memory, performs shift processing, performs the ith butterfly operation based on the result (din) obtained by shifting the intermediate result, and outputs the intermediate result (dout) of the ith butterfly operation.
The second memory and the third memory are arranged in the device and are used for storing the intermediate result of each level of butterfly operation, and for each level of butterfly operation, the read-write operation in the operation process is distributed to different memories through ping-pong operation, so that the read-write of data can not conflict when the butterfly operation is performed. Taking the example that the intermediate result is input into the second memory after the level 1 butterfly operation, for the level 2 butterfly operation, reading the intermediate result of the level 1 butterfly operation from the second memory, performing shift processing, storing the intermediate result output after the butterfly operation into the third memory, sequentially executing each level of butterfly operation, and performing each time of reading and writing on the two memories respectively, so as to realize that the intermediate result is sequentially stored in the second memory and the third memory in a rotating way until the Fourier transform calculation is completed.
Through the device provided by the embodiment, the shift processing is performed in advance when the data is read to perform the butterfly operation, so that the subsequent operation can be ensured not to overflow, meanwhile, the two memories are adopted to sequentially store the intermediate result of each level of butterfly operation in a rotating way, the conflict of data reading and writing in each level of butterfly operation is reduced, meanwhile, the storage area and the power consumption of the intermediate result can be reduced, and the problem that the current storage area and the power consumption of the intermediate result are larger is solved.
In this embodiment, there is provided a fast fourier transform apparatus including: the device comprises a displacement detection module, a first memory, a second memory, a third memory, an address generation module and a butterfly operation module, wherein the first memory, the second memory, the third memory, the address generation module and the butterfly operation module are respectively connected with the displacement detection module.
A first memory for storing raw FFT data;
the address generation module is used for generating read-write addresses of the first memory, the second memory and the third memory;
the butterfly operation module is used for carrying out the 1 st level butterfly operation based on the original FFT data and outputting the intermediate result of the 1 st level butterfly operation; and performing the ith butterfly operation based on the result of the shift of the intermediate result of the previous butterfly operation, and outputting the intermediate result of the ith butterfly operation; wherein I is more than or equal to 2 and less than or equal to I, I represents the total number of stages of butterfly operation, and I is a positive integer;
the shift detection module is used for carrying out shift processing on the intermediate result output by the butterfly operation module;
and the second memory and the third memory are used for sequentially and cyclically storing the results after the intermediate result shift.
The fast fourier transform device in this embodiment is identical to the one shown in fig. 6, but differs from the one shown in fig. 6 in terms of module function.
After generating the read-write address of each memory, the address generating module converts the read-write address into a binary mark, and then converts the lowest bit and the highest bit of the binary.
And the butterfly operation module is used for reading the original FFT data (din) from the first memory in the 1 st-stage butterfly operation according to the read-write address generated by the address generation module, performing the butterfly operation on the 1 st stage, outputting the intermediate result (dout) of the 1 st-stage butterfly operation, and performing shift processing on the intermediate result through the shift detection module. In the level 1 butterfly operation, a shift value for shifting an intermediate result is determined by the amplitude of original FFT data and the level 1 butterfly operation, so that subsequent operations are guaranteed not to overflow, and the shift value is set to be 2 bits, that is, shift processing for shifting the intermediate result by 2 bits to the right is performed before the intermediate result is stored in the memory.
And for the ith butterfly operation, reading a result (din) obtained after the intermediate result of the last butterfly operation is shifted from the second memory or the third memory, performing the ith butterfly operation, outputting an intermediate result (dout) of the ith butterfly operation, and performing shift processing on the output intermediate result through a shift detection module, wherein a shift value of the intermediate result subjected to shift processing is determined by the last butterfly operation, and updating is performed after each butterfly operation, so that the subsequent operation is ensured not to overflow.
The second memory and the third memory are arranged in the device and are used for storing the result after the intermediate result of each level butterfly operation is shifted, and for each level butterfly operation, the read-write operation in the operation process is distributed to different memories through the ping-pong operation, so that the read-write collision of data in the butterfly operation is avoided. Taking the example that the intermediate result is input into the second memory after the 1 st stage butterfly operation, for the 2 nd stage butterfly operation, reading the intermediate result of the 1 st stage butterfly operation from the second memory, shifting the output intermediate result, storing the shifted intermediate result into the third memory, sequentially executing each stage of butterfly operation, and respectively performing each time of reading and writing on the two memories, so as to realize that the intermediate result is sequentially and cyclically stored into the second memory and the third memory until the Fourier transform calculation is completed.
Through the device provided by the embodiment, the shift processing is performed before the intermediate result of each level butterfly operation is written into the memory, so that the subsequent operation can be ensured not to overflow, and meanwhile, the two memories are adopted to sequentially and cyclically store the result after the intermediate result of each level butterfly operation is shifted, so that the conflict of data reading and writing in each level butterfly operation is reduced, the storage area and the power consumption of the intermediate result can be reduced, and the problem of larger storage area and power consumption of the intermediate result at present is solved.
In some embodiments, the address generation module is further configured to: dividing each level of butterfly operation in the fast Fourier transform; and generating a ping-pong selection signal in each stage of butterfly operation.
Specifically, fig. 7 is a schematic diagram of an output signal of the address generation module in this embodiment, and as shown in fig. 7, the address generation module includes a stage number counter and an address counter, generates a dividing signal (stage_done) for dividing each stage of butterfly operation in the fft, generates a ping-pong selection signal (addr_base) for each stage of butterfly operation, and generates a read-write address (addr_offset) of a memory required for each stage of butterfly operation.
In the embodiment, the address generation module provides the read-write address and the ping-pong selection signal for the butterfly operation module, so that the butterfly operation module can be driven to respectively perform read-write operation on the two memories, and the conflict of data read-write is reduced.
In some embodiments, the shift detection module is further configured to perform high-level detection on the output intermediate result after each stage of butterfly operation ends, so as to update the shift value of the shift process.
The method comprises the steps of performing operation on a value of a preset high bit in an intermediate result and a preset register, and updating a current operation result in the preset register; and after each level of butterfly operation is finished, determining a shift value according to the current operation result.
Fig. 8 is a schematic diagram of data processing in the shift detection module in this embodiment, where the butterfly operation module reads data based on the ping-pong selection signal and the read-write address, and in one case, as shown in fig. 8, when the shift detection module reads data to be calculated from the memory, the shift detection module performs shift processing based on the shift value, uses the result after the shift of the data to be calculated as the input (din) of the butterfly operation module, and directly writes the intermediate result (dout) output by the butterfly operation module into the memory. In another case, the butterfly operation reads an intermediate result of the previous butterfly operation from the memory as an input (din), and when the butterfly operation module outputs the intermediate result, the shift detection module performs shift processing based on the shift value, and writes a result (dout) obtained by shifting the intermediate result into the memory. In addition, when the shift value is updated by high-order detection, when the division signal is received, the preset register is cleared after the shift value is updated.
In this embodiment, the shift detection module performs shift processing when the butterfly operation module reads data to be calculated or outputs an intermediate result, and updates a shift value of shift processing after each stage of butterfly operation through high-order detection, so as to ensure that subsequent operations do not overflow.
In some embodiments, the butterfly operation module is further configured to sequentially write the intermediate result or the result after the intermediate result is shifted into the second memory and the third memory in rotation based on the ping-pong selection signal and the read-write address of each memory.
Specifically, in each butterfly operation, read-write operations are performed on the two memories based on the ping-pong selection signal respectively through the read-write address generated in the address generation module. When the intermediate result is read, shifting is carried out, and the intermediate result output by butterfly operation is sequentially and circularly written into a second memory and a third memory; and when the shift processing is performed during the output of the intermediate result, sequentially and cyclically writing the result obtained after the shift of the butterfly operation output intermediate result into the second memory and the third memory. Illustratively, shift processing is performed when the intermediate result of the previous butterfly operation is read from the second memory, and after butterfly operation is performed, the output intermediate result is input into the third memory; or, after the intermediate result of the last stage of butterfly operation is read from the third memory and subjected to butterfly operation, the intermediate result is output and the intermediate result is shifted to the second memory.
In the embodiment, by ping-pong operation, read-write operation is performed on two memories in each butterfly operation, so that data read-write conflict is reduced, intermediate results of each butterfly operation are sequentially and cyclically written into a second memory and a third memory, and power consumption and area occupation of intermediate result storage are reduced.
In some embodiments, the butterfly operation module is a base 2 operation module, and the second memory and the third memory are single-port RAM; or in the radix-4 butterfly operation, the butterfly operation module is a radix-4 operation module, and the second memory and the third memory are dual-port RAMs.
Specifically, in the radix-2 butterfly operation, as shown in fig. 6, the second memory and the third memory are single-port RAM (Random Access Memory ), which means that the second memory and the third memory have only one read/write port, and only can perform the read or write operation at the same time.
Fig. 9 is a schematic structural diagram of radix-4 butterfly operation in the fast fourier transform apparatus in this embodiment, as shown in fig. 9, in the radix-4 butterfly operation, the second memory and the third memory are dual-port RAMs, two independent read/write ports are provided, data can be accessed simultaneously, and higher access efficiency is provided in the radix-4 butterfly operation with larger operation amount.
In this embodiment a digital hearing aid is provided comprising the fast fourier arrangement of the above embodiments.
In the digital hearing aid system, the fast fourier transform for time-frequency conversion is a critical loop, and by applying the fast fourier transform device to the digital hearing aid, the area for storing intermediate results in fast fourier transform and larger power consumption are reduced, so that the fast fourier transform device can be suitable for application scenes of the digital hearing aid, such as high precision, low delay and low power consumption.
There is also provided in this embodiment a computer device comprising a memory in which a computer program is stored and a processor arranged to run the computer program to perform the steps of any of the method embodiments described above.
Optionally, the computer device may further include a transmission device and an input/output device, where the transmission device is connected to the processor, and the input/output device is connected to the processor.
It should be noted that, specific examples in this embodiment may refer to examples described in the foregoing embodiments and alternative implementations, and are not described in detail in this embodiment.
In addition, in combination with the fast fourier transform method provided in the above embodiment, a storage medium may be provided in this embodiment. The storage medium has a computer program stored thereon; the computer program, when executed by a processor, implements any of the fast fourier transform methods of the above embodiments.
It should be noted that, user information (including but not limited to user equipment information, user personal information, etc.) and data (including but not limited to data for analysis, stored data, presented data, etc.) referred to in the present application are information and data authorized by the user or sufficiently authorized by each party.
It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to be limiting. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present application, are within the scope of the present application in light of the embodiments provided herein.
It is evident that the drawings are only examples or embodiments of the present application, from which the present application can also be adapted to other similar situations by a person skilled in the art without the inventive effort. In addition, it should be appreciated that while the development effort might be complex and lengthy, it would nevertheless be a routine undertaking of design, fabrication, or manufacture for those of ordinary skill having the benefit of this disclosure, and thus should not be construed as an admission of insufficient detail.
The term "embodiment" in this application means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive. It will be clear or implicitly understood by those of ordinary skill in the art that the embodiments described in this application can be combined with other embodiments without conflict.
The above examples only represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the patent. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application shall be subject to the appended claims.
Claims (10)
1. A fast fourier transform method, adapted for use in a fast fourier transform apparatus, the apparatus comprising: a first memory storing original FFT data, a second memory storing intermediate results of butterfly operations, and a third memory; the method comprises the following steps:
Performing a level 1 butterfly operation based on the shifted result of the original FFT data, and outputting an intermediate result of the level 1 butterfly operation;
performing shift processing when reading the intermediate result;
performing an ith butterfly operation based on the result obtained after the intermediate result of the last butterfly operation is shifted, and outputting an intermediate result of the ith butterfly operation; wherein I is more than or equal to 2 and less than or equal to I, I represents the total number of stages of butterfly operation, and I is a positive integer;
and sequentially and cyclically storing the intermediate result into the second memory and the third memory.
2. A fast fourier transform method, adapted for use in a fast fourier transform apparatus, the apparatus comprising: a first memory for storing original FFT data, a second memory for storing the result after the shift of the butterfly operation intermediate result, and a third memory; the method comprises the following steps:
performing a 1 st level butterfly operation based on the original FFT data, and outputting an intermediate result of the 1 st level butterfly operation;
performing an ith butterfly operation based on the result obtained after the intermediate result of the last butterfly operation is shifted, and outputting an intermediate result of the ith butterfly operation; wherein I is more than or equal to 2 and less than or equal to I, I represents the total number of stages of butterfly operation, and I is a positive integer;
Performing shift processing on the intermediate result;
and sequentially and cyclically storing the results after the intermediate result shift into the second memory and the third memory.
3. The fast fourier transform method according to any one of claims 1-2, further comprising:
and after each stage of butterfly operation is finished, performing high-order detection on the output intermediate result to update the shift value of the shift processing.
4. A fast fourier transform method according to claim 3, wherein said high-order detecting of said intermediate result of said output to update a shift value of said shift process comprises:
calculating a preset high-order value in the intermediate result and a preset register, and updating a current calculation result in the preset register;
and after each stage of butterfly operation is finished, determining the shift value according to the current operation result.
5. The fast fourier transform method according to any one of claims 1-2, further comprising:
dividing each level of butterfly operation in the fast Fourier transform, and generating a ping-pong selection signal corresponding to each level of butterfly operation.
6. The fast fourier transform method of claim 5, further comprising:
And based on the ping-pong selection signal and the read-write address of each memory, sequentially and cyclically writing the intermediate result or the result after the intermediate result is shifted into the second memory and the third memory.
7. A fast fourier transform device, comprising: the device comprises a shift detection module, a first memory, a second memory, a third memory, an address generation module and a butterfly operation module, wherein the first memory, the second memory, the third memory, the address generation module and the butterfly operation module are respectively connected with the shift detection module;
the first memory is used for storing original FFT data;
the shift detection module is used for carrying out shift processing when the butterfly operation module reads data to be calculated;
the address generation module is used for generating read-write addresses of the first memory, the second memory and the third memory;
the butterfly operation module is used for carrying out the level 1 butterfly operation based on the result after the FFT data shift and outputting the intermediate result of the level 1 butterfly operation; and performing the ith butterfly operation based on the result of the shift of the intermediate result of the previous butterfly operation, and outputting the intermediate result of the ith butterfly operation; wherein I is more than or equal to 2 and less than or equal to I, I represents the total number of stages of butterfly operation, and I is a positive integer;
The second memory and the third memory are used for sequentially and cyclically storing intermediate results output by the butterfly operation module.
8. A fast fourier transform device, comprising: the device comprises a shift detection module, a first memory, a second memory, a third memory, an address generation module and a butterfly operation module, wherein the first memory, the second memory, the third memory, the address generation module and the butterfly operation module are respectively connected with the shift detection module;
the first memory is used for storing original FFT data;
the address generation module is used for generating read-write addresses of the first memory, the second memory and the third memory;
the butterfly operation module is used for carrying out the 1 st level butterfly operation based on the original FFT data and outputting the intermediate result of the 1 st level butterfly operation; and performing the ith butterfly operation based on the result of the shift of the intermediate result of the previous butterfly operation, and outputting the intermediate result of the ith butterfly operation; wherein I is more than or equal to 2 and less than or equal to I, I represents the total number of stages of butterfly operation, and I is a positive integer;
the shift detection module is used for carrying out shift processing on the intermediate result output by the butterfly operation module;
the second memory and the third memory are used for sequentially and cyclically storing the results after the intermediate result shift.
9. The fast fourier transform device of any of claims 7-8, wherein the butterfly operation module is a radix-2 operation module, and the second and third memories are single-port RAMs; or,
the butterfly operation module is a base 4 operation module, and the second memory and the third memory are dual-port RAMs.
10. A digital hearing aid comprising: the fast fourier transform device of any of claims 7 to 9.
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