CN101345604A - Parallel implementing method for determinant block interleaving device - Google Patents
Parallel implementing method for determinant block interleaving device Download PDFInfo
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Abstract
The invention relates to a parallel accomplishing method for row type grouped interweaver, belonging to communication field. Interweaving depth is d, breadth is n for row type grouped interweaver; random factor of n is selected as parallelism degree p, n=w*p, w is positive integer. First sequence exchanger exchanges inputted p bit data in order, then executes ROR, then writes p bit data gotten from sequential exchange and ROR in p double port RAMs (random access memory) according to p address created by writing address creator; after writing a frame of data, then parallel reading p bit data from p double port RAMs according to read address created by read address creator, then executes ROL to get interweaved data. The invention can agilely selects parallelism degree p to accomplish parallel row type grouped interweaver, so promotes data processing rate p times to satisfy needs of high speed data transmission.
Description
Technical field
The present invention relates to communication technical field, relate in particular to a kind of Parallel Implementation method of determinant block interleaved device.
Background technology
The determinant block interleaved is the most directly perceived also the simplest a kind of interleaving mode in the interleaver, and its basic principle is that the Bit data that will import is packed in d * n the matrix unit, as shown in fig. 1 line by line; After having filled all matrix units, then by the content in the row sensor matrix unit, as shown in Figure 2.Wherein, d and n are two parameters of determinant block interleaved device, are called interleave depth and weaving width.From interleave function, the function of determinant block interleaved device is output again again after the Bit data of input is upset in proper order, and determinant block interleaved device is to be that the Bit data of d * n is the unit that interweaves with the frame length, and every frame data are carried out identical interlace operation.
The serial implementation method of determinant block interleaved device is comparatively simple.Use a capacity for (d * n) * 1 storage is write, read to the dual port random access memory (RAM) of bit to Bit data, the write address of dual port RAM is that 1 counter that adds of d * n produces by mould, after in dual port RAM, writing full d * n data, then begin sense data from dual port RAM, the generation of reading the address of dual port RAM is by Cnt
RAnd Cnt
CTwo parts addition constitutes, Cnt
RBe a mould be d * n add the n counter, work as Cnt
RCalculated value be 0 o'clock by (d-1) * n redirect, Cnt
CThen carrying out mould is 1 counting that adds of n, and the initial value of two counters all is 0.
Obviously, the data processing speed bottleneck of the determinant block interleaved device realized of serial approach is subject to the writing of dual port RAM, reading rate.In order to improve the data processing speed of determinant block interleaved device, can take the Parallel Implementation method.Denomination of invention is for having provided a kind of Parallel Implementation method of determinant block interleaved device among the US6476738 of granted patent of " Block interleave circuit ", it mainly proposes for the purpose of avoiding the comparatively loaded down with trivial details read-write control logic of dual port RAM.With shift register d * n Bit data carried out the serial conversion earlier during realization, then deposit parallel data after the conversion, afterwards the dateout of this d * n register is upset to walk abreast in proper order depositing the data Output Shift Register in and walk abreast/serial conversion according to the desired data of function of determinant block interleaved device with d * n register.Though in patent of invention US6476738, the data of determinant block interleaved device output are serial modes, if remove the data Output Shift Register, this invention can regard that the degree of parallelism of determinant block interleaved device is the Parallel Implementation method of d * n as.
The shortcoming of foregoing invention is a d and the less situation of n value of only being suitable for, when d and n are big, this invent need be a large amount of register resources, thereby impracticable; The degree of parallelism of this invention is fixed in addition, can not change flexibly according to the actual requirements.
Summary of the invention
The present invention is directed to the Parallel Implementation of determinant block interleaved device,, proposed a kind of Parallel Implementation method of determinant block interleaved device for improving the data processing speed of determinant block interleaved device.
The present invention is achieved through the following technical solutions:
The interleave depth that makes determinant block interleaved device is d, weaving width is n, the number of one frame Bit data is d * n, any factor of choosing n is as degree of parallelism p, n=w * p, wherein w is a positive integer, determinant block interleaved device be input as that data width is the p bit parallel data after serial conversion, its output is also for data width is the p bit parallel data, and the data that a frame interweaves are that d * w data width is the p bit parallel data.Its step is as follows:
(1) with the order interchanger p Bit data of importing is carried out the order exchange.The order interchanger is a data passage that the p Bit data is carried out the bit-order exchange according to exchange sequence, the exchange sequence of each p Bit data is all identical, given d, n, p value, exchange sequence just determine that also its computational methods are: get i and be the integer on 0 to p-1, at first calculate index Indx value, wherein the relation between Indx and the i is as follows:
Indx＝mod(i，n)×d+floor(i/n)
Wherein mod (i, n) expression i is divided exactly the remainder that n obtains, floor (i/n) expression i is divided exactly the merchant that n obtains, then, the Indx value according to calculating calculates the Shuf value, the Shuf value is the integer that is positioned on 0 to p-1, wherein the relation between Shuf and the Indx is as follows:
Shuf＝mod(Indx+mod(floor(Indx/lcm(d，p))，gcd(d，p))，p)
Lcm (d wherein, p) least common multiple of d and p is asked in expression, and gcd (d, p) then the greatest common divisor of d and p is asked in expression, floor (Indx/lcm (d, p)) expression Indx is divided exactly lcm (d, the merchant who p) obtains, mod (floor (Indx/lcm (d, p)), (Indx/lcm (d, p)) is divided exactly gcd (d to gcd (d, p)) expression floor, p) remainder that obtains, mod (Indx+mod (floor (Indx/lcm (d, p)), gcd (d, p)), p) then represent Indx and mod (floor (Indx/lcm (d, p)), gcd (d, p)) divide exactly the remainder that p obtains with value, get the i value and be followed successively by from 0 to p-1 integer, calculate successively and can get p Shuf value, the corresponding relation integer of the p from 0 to p-1 and p the Shuf value calculating is exchange sequence;
(2) will behind step (1) exchange sequence, obtain the data inputs cyclic shifter cyclic shift that moves to right that moves to right, the cyclic shifter that moves to right each p Bit data after to exchange sequence carries out to the right cyclic shift, and (a data high position is on a left side, low level is on the right side), the computational methods of the number of times SR of displacement are as follows:
SR＝floor(k/w)
Wherein k represents the sequence number of p Bit data in frame p bit parallel data, and value is the integer on 0 to d * w-1, and floor (k/w) expression asks k to divide exactly the merchant that w obtains;
(3) p the write address that produces according to the write address generator, each bit of the p Bit data that will obtain after step (2) move to right cyclic shift writes respectively in p the dual port RAM.The write address generator is used to produce distinguishes p corresponding write address when each p Bit data writes toward p dual port RAM, its production method is: for the 1st p Bit data (sequence number k is 0), the content of reading from 0 address storaging unit of read-only memory (ROM) is p write address of the 1st p Bit data, the production method of the write address of (w-1) individual p Bit data that it is follow-up is that p write address of a back p Bit data added up by p write address of previous p Bit data and 1 obtain, for (w+1) individual p Bit data (sequence number k is w), the content of reading from 1 address storaging unit of ROM is p the write address of (w+1) individual p Bit data, the production method of the write address of (w-1) individual p Bit data that it is follow-up is that p write address of a back p Bit data added up by p write address of previous p Bit data and 1 obtain, the rest may be inferred, and (d * w) the pairing write address of individual p Bit data produces in this way and obtains.
The production method of the content of storing among the ROM is: for the 1st p Bit data (sequence number k is 0), get i for from 0 to p-1 integer, at first, calculate p Indx value, then, calculate the individual initially write address Addr of p according to the Indx value
WR, Addr wherein
WRAnd the relation between the Indx is as follows:
Addr
WR＝mod(floor(Indx/p)，d)×w+floor(Indx/(d×p))
Wherein floor (Indx/p) expression Indx is divided exactly the merchant that p obtains, mod (floor (Indx/p), d) expression asks floor (Indx/p) to divide exactly the remainder that d obtains, floor (Indx/ (d * p)) represents that then Indx divides exactly the merchant that d * p obtains, exchange sequence according to the p Bit data, earlier p initial write address carried out the order exchange, carry out the identical circulative shift operation that moves to right according to the operation of the cyclic shift that moves to right of the 1st p Bit data p initial write address after to the order exchange again, it is (high-order in order on a left side that the p that an obtains write address carries out the link of binary bits data, low level is on the right side) deposit in the memory cell of 0 address indication of ROM, for (w+1) individual p Bit data (sequence number k is w), get i for from (w * p) is to the integer of (w+1) * p-1, calculate p Indx value earlier, then, calculate p initial write address Addr according to the Indx value
WRExchange sequence according to the p Bit data, earlier p initial write address carried out the order exchange, carry out the identical circulative shift operation that moves to right according to the operation of the cyclic shift that moves to right of w p Bit data p initial write address after to the order exchange again, the p that obtains write address binary bits data link in the memory cell of the 1 address indication that deposits ROM in, the rest may be inferred, and the content of d memory cell according to said method produces and obtains among the ROM, and the capacity of ROM is d * (p * m
1) bit, wherein,
Wherein
Represent to round up computing, promptly need m
1Individual bit is represented (d-1) * w value;
(4) step (3) finish frame data are all write p dual port RAM after, according to reading the address of reading that address generator produces, parallel read-out p Bit data from p dual port RAM, p dual port RAM to read the address all identical, it produces by Cnt
RAnd Cnt
CTwo parts addition constitutes, Cnt
RBe a mould be d * w add the w counter, work as Cnt
RCalculated value is 0 o'clock by (d-1) * w redirect, Cnt
CThen carrying out mould is 1 counting that adds of w, and the initial value of two counters all is 0;
(5) cyclic shifter that moves to left is carried out left cyclic shift to each p Bit data of being read by step (4) (a data high position is on a left side, low level is on the right side), the p Bit data that obtains after the cyclic shift that moves to left is the output of determinant block interleaved device, and the computational methods of the number of times SL of cyclic shift are as follows left:
SL＝mod(floor(j/(d/gcd(d，p)))，gcd(d，p))
Wherein j represents the sequence number of the p Bit data read from p dual port RAM, and value is the integer on 0 to d * w-1, gcd (d, p) then the greatest common divisor of d and p is asked in expression, (j/ (d/gcd (d, p))) expression j is divided exactly the (merchant that d/gcd (d, p)) obtains to floor, mod (floor (j/ (d/gcd (d, p))), gcd (d, p)) expression floor (j/ (d/gcd (d, p))) divide exactly gcd (d, the remainder that p) obtains.
Beneficial effect of the present invention
The present invention is by choosing the mode of degree of parallelism p neatly, and the data processing rate of determinant block interleaved device is improved p doubly, satisfied the application of high speed data transfer.
Description of drawings
Fig. 1 is the schematic diagram of writing of determinant block interleaved device;
Fig. 2 is the schematic diagram of reading of determinant block interleaved device;
Fig. 3 is the Parallel Implementation structure chart of determinant block interleaved device;
Fig. 4 is the structure chart of the write address generator among Fig. 3;
Fig. 5 is the structure chart of reading address generator among Fig. 3;
Fig. 6 for dual port RAM write fashionable, the sequential chart of the control signal that controller among Fig. 3 produces;
When Fig. 7 reads for dual port RAM, the sequential chart of the control signal that the controller among Fig. 3 produces;
Fig. 8 is the order exchange of one group of data according to an embodiment of the invention and the cyclic shift figure that moves to right;
Fig. 9 is the order exchange of another group of data according to an embodiment of the invention and the cyclic shift figure that moves to right;
Figure 10 is that a frame interleaving data according to an embodiment of the invention has been write the memory contents schematic diagram in the dual port RAM of back.
Embodiment
The present invention proposes a kind of Parallel Implementation method of determinant block interleaved device.The interleave depth of determinant block interleaved device is d, and weaving width is n, and the number of a frame Bit data is d * n, and any factor of choosing n is as degree of parallelism p, and n=w * p, w are positive integer.
Converting every p the Bit data serial continuously of d * n Bit data to a data width is the p bit parallel data.Interleaving process need be (dual port RAM (the RAM of bit of d * w) * 1 with p capacity
0, RAM
1..., RAM
P-1) storage is write, read to data.Each p Bit data is not to write RAM respectively according to the bit-order in the parallel data
0, RAM
1..., RAM
P-1In, and after this p Bit data need being carried out the order exchange earlier,, according to write address each bit is write RAM respectively then again through cyclic shift
0, RAM
1..., RAM
P-1In this p dual port RAM.
The Parallel Implementation structured flowchart of determinant block interleaved device as shown in Figure 3.
The function of order interchanger 3001 is that the p Bit data that determinant block interleaved device is imported is carried out the order exchange.For given d, n, the p value, exchange sequence determines that its computational methods are: get i and be the integer on 0 to p-1, at first calculate index Indx value according to formula (1).
Indx＝mod(i，n)×d+floor(i/n) (1)
Wherein mod (i, n) expression i is divided exactly the remainder that n obtains, floor (i/n) expression i is divided exactly the merchant that n obtains.
According to the Indx value that calculates, calculate the Shuf value according to formula (2), the Shuf value is for being positioned at the integer on 0 to p-1.
Shuf＝mod(Indx+mod(floor(Indx/lcm(d，p))，gcd(d，p))，p) (2)
Wherein, lcm (d, p) least common multiple of d and p is asked in expression, gcd (d, p) then the greatest common divisor of d and p is asked in expression, floor (Indx/lcm (d, p)) expression ask Indx divide exactly lcm (d, the merchant who p) obtains,
Mod (floor (Indx/lcm (d, p)), gcd (d, p)) (Indx/lcm (d, p)) is divided exactly gcd (d, the remainder that p) obtains to expression floor, mod (Indx+mod (floor (Indx/lcm (d, p)), gcd (d, p)), p) then represent Indx and mod (floor (Indx/lcm (d, p)), gcd's (d, p)) divides exactly the remainder that p obtains with value.
Get the i value and be followed successively by from 0 to p-1 integer, calculate successively and can get p Shuf value, the corresponding relation integer of the p from 0 to p-1 and p the Shuf value calculating is exchange sequence.
Order interchanger among the present invention only is the cross over transition of data path, does not consume any circuit resource.
The function of the cyclic shifter that moves to right among Fig. 3 3002 is to finish the operation of cyclic shift to the right of each p Bit data.A data high position is on a left side, and low level is on the right side, by the CE of controller 3008 generations
2Signal indication be each p Bit data number of times SR of cyclic shift to the right, it can calculate according to formula (3).
SR＝floor(k/w) (3)
Wherein k represents the sequence number of p Bit data in frame p bit parallel data, and value is the integer on 0 to d * w-1, and floor (k/w) expression asks k to divide exactly the merchant that w obtains.
Among Fig. 3, read-only memory (ROM) 3003 is d memory cell altogether, its memory contents production method is as follows: for the 1st p Bit data (sequence number k is 0), get i for from 0 to p-1 integer, at first, calculate p Indx value according to formula (1), then, calculate p initial write address Addr by formula (4) according to the Indx value
WR,
Addr
WR＝mod(floor(Indx/p)，d)×w+floor(Indx/(d×p)) (4)
Wherein floor (Indx/p) expression Indx is divided exactly the merchant that p obtains, mod (floor (Indx/p), d) expression asks floor (Indx/p) to divide exactly the remainder that d obtains, floor (Indx/ (d * p)) represents that then Indx divides exactly the merchant that d * p obtains, exchange sequence according to the p Bit data, earlier p initial write address carried out the order exchange, carry out the identical circulative shift operation that moves to right according to the operation of the cyclic shift that moves to right of the 1st p Bit data p initial write address after to the order exchange again, it is (high-order in order on a left side that the p that an obtains write address carries out the link of binary bits data, low level is on the right side) deposit in the memory cell of 0 address indication of ROM, for (w+1) individual p Bit data (sequence number k is w), get i for from (w * p) is to the integer of (w+1) * p-1, calculate p Indx value earlier, then, calculate p initial write address Addr according to the Indx value
WRExchange sequence according to the p Bit data, earlier p initial write address carried out the order exchange, carry out the identical circulative shift operation that moves to right according to the operation of the cyclic shift that moves to right of w p Bit data p initial write address after to the order exchange again, the p that an obtains write address carries out the binary bits data and links in the memory cell of the 1 address indication that deposits ROM in, by parity of reasoning, and the d that stores among a ROM write address produces in this way and obtains, and the amount of capacity of ROM is d * (p * m
1) bit, wherein,
Wherein
Represent to round up computing, promptly need m
1Individual bit is represented (d-1) * w value;
Among Fig. 3, ROM reads the every w of an address CA clock cycle from adding 1 (initial value is 0), and the p of a read-only memory bit wide is m
1The output of bit corresponds to respectively on p the write address generator 3004.
The detailed structure of write address generator 3004 as shown in Figure 4.Order
Promptly need m
2Individual bit is represented the (value of d * w-1).CE
1When signal was effective, the data width of the content that will read from read-only memory 3003 was from m
1Expand to m
2(high-order benefit 0).CE
1During invalidating signal, write address adds up 1.
P write address of p write address generator 3004 outputs corresponds to respectively on p the write address port of p dual port RAM 3005, with each bit of p Bit data write p dual port RAM by in the indicated memory cell of p write address.
Read the address of reading that address generator 3006 is used to produce dual port RAM, p dual port RAM to read the address all identical, it produces by Cnt
RAnd Cnt
CTwo parts addition constitutes, Cnt
RBe a mould be d * w add the w counter, work as Cnt
RCalculated value is 0 o'clock by (d-1) * w redirect, Cnt
CThen carrying out mould is 1 counting that adds of w, and the initial value of two counters all is 0.The detailed structure of reading address generator 3006 as shown in Figure 5.CE
3When signal is effective, Cnt
RPut 0, Cnt
CAdd 1 counting; Otherwise, Cnt
RAdd the w counting, Cnt
CIt is constant then to keep initial value.
Read individual the reading on the address port of p that the address has corresponded to p dual port RAM 3005 of reading of address generator 3006 generations, be used for parallel read-out p Bit data.
Each p Bit data that 3007 pairs of the cyclic shifter that moves to left are read cyclic shift that moves to left, a data high position is on a left side, and low level is on the right side, and the p Bit data that obtains after the cyclic shift left is the output of determinant block interleaved device, the CE that is produced by controller 3008
4Signal indication be each p Bit data number of times SL of cyclic shift left, it can calculate according to formula (5).
SL＝mod(floor(j/(d/gcd(d，p)))，gcd(d，p)) (5)
When in dual port RAM, writing data, need to produce control signal CA, CE
1And CE
2, its sequential chart as shown in Figure 6.After frame data all write p dual port RAM, just begin reading of data from p dual port RAM, during read data, need to produce control signal CE
3And CE
4, its sequential chart as shown in Figure 7.Only provided the sequential relationship in the preceding d clock cycle among Fig. 7, follow-up sequential relationship then is (w-1) the inferior repetition among Fig. 7.
Be illustrated with instantiation below.
Example:
If: interleave depth d=6, weaving width n=12, degree of parallelism p=4 is according to formula n=w * p, then w=3.
If 72 Bit datas of a frame are x
0, x
1..., x
71
Get i respectively and equal 0,1,2,3, calculate the Indx value by formula (1) and be respectively (0,6,12,18), calculate the Shuf value by formula (2) and be respectively (0,2,1,3).
For 4 Bit data (x
0, x
1, x
2, x
3), sequence number k equals 0, calculating the SR value by formula (3) is 0, therefore, through order exchange and to the right 4 Bit datas after the cyclic shift 0 time be (x
0, x
2, x
1, x
3), the order of this 4 Bit data exchanges and moves to right cyclic shift figure as shown in Figure 8.
For another example for 4 Bit data (x
36, x
37, x
38, x
39), sequence number k equals 9, calculating the SR value by formula (3) is 3, therefore, through order exchange and to the right 4 Bit datas after the cyclic shift 3 times be (x
38, x
37, x
39, x
36), the order of this 4 Bit data exchanges and moves to right cyclic shift figure as shown in Figure 9.
6 groups of initial write address Addr that calculate by formula (4)
WRBe (0,3,9,12); (0,3,9,12); (0,6,9,15); (0,6,9,15); (3,6,12,15); (3,6,12,15).Through the order exchange and the cyclic shift that moves to right after, 6 groups of write addresses be (0,9,3,12); (12,0,9,3); (6,15,0,9); (9,6,15,0); (3,12,6,15); (15,3,12,6).
Every group of write address link deposited among the ROM that capacity is 6 * 16 bits, and since 0 address, the content of storage is followed successively by 0000100100111100; 1100000010010011; 0110111100001001; 1001011011110000; 0011110001101111; 1111001111000110.
In this example, after a frame interleaving data has been write, 4 dual port RAM (RAM
0, RAM
1, RAM
2, RAM
3) middle content of storing as shown in Figure 10.
After one frame interleaving data has been write, need from 4 dual port RAMs, data to be read, and will read the 4 Bit datas cyclic shift that moves to left at every turn according to reading the address.
As read the 1st 4 Bit datas read the address for (0,0,0,0), the 1st 4 Bit datas of reading from 4 dual port RAMs are (x
0, x
12, x
24, x
36), j=0, calculating the SL value by formula (5) is 0.This 4 Bit data needs through cyclic shift left 0 time, also is that the 1st 4 Bit datas of determinant block interleaved device output are (x
0, x
12, x
24, x
36).
The address of reading of reading the 5th 4 Bit datas for another example is (12,12,12,12), and the 5th 4 Bit datas of reading from 4 dual port RAMs are (x
15, x
50, x
62, x
3), j=4, calculating the SL value by formula (6) is 1.This 4 Bit data after cyclic shift left 1 time determinant block interleaved device be output as (x
50, x
62, x
3, x
15).
Claims (1)
1. the Parallel Implementation method of a determinant block interleaved device is characterized in that, any factor of choosing n is as degree of parallelism p, n=w * p, wherein, the interleave depth of determinant block interleaved device is d, and weaving width is n, the number of one frame Bit data is d * n, and w is a positive integer, and concrete steps comprise:
(1) with the order interchanger p Bit data of importing is carried out the order exchange, the order interchanger is a data passage that the p Bit data is carried out the bit-order exchange according to exchange sequence, the exchange sequence of each p Bit data is all identical, given d, n, p value, exchange sequence is also just determined, its computational methods are: get i and be the integer on 0 to p-1, at first calculate index Indx value, wherein the relation between Indx and the i is as follows:
Indx＝mod(i，n)×d+floor(i/n)
Wherein mod (i, n) expression i is divided exactly the remainder that n obtains, floor (i/n) expression i is divided exactly the merchant that n obtains, then, the Indx value according to calculating calculates the Shuf value, the Shuf value is the integer that is positioned on 0 to p-1, wherein the relation between Shuf and the Indx is as follows:
Shuf＝mod(Indx+mod(floor(Indx/1cm(d，p))，gcd(d，p))，p)
1cm (d wherein, p) least common multiple of d and p is asked in expression, and gcd (d, p) then the greatest common divisor of d and p is asked in expression, floor (Indx/1cm (d, p)) expression Indx is divided exactly 1cm (d, the merchant who p) obtains, mod (floor (Indx/1cm (d, p)), (Indx/1cm (d, p)) is divided exactly gcd (d to gcd (d, p)) expression floor, p) remainder that obtains, mod (Indx+mod (floor (Indx/1cm (d, p)), gcd (d, p)), p) then represent Indx and mod (floor (Indx/1cm (d, p)), gcd (d, p)) divide exactly the remainder that p obtains with value, get the i value and be followed successively by from 0 to p-1 integer, calculate successively and can get p Shuf value, the corresponding relation integer of the p from 0 to p-1 and p the Shuf value calculating is exchange sequence;
(2) will behind step (1) exchange sequence, obtain the data inputs cyclic shifter cyclic shift that moves to right that moves to right, the cyclic shifter that moves to right each p Bit data after to exchange sequence according to a data high position on a left side, low level carries out cyclic shift to the right on the right side, the computational methods of the number of times SR of displacement are as follows:
SR＝floor(k/w)
Wherein k represents the sequence number of p Bit data in frame p bit parallel data, and value is the integer on 0 to d * w-1, and floor (k/w) expression asks k to divide exactly the merchant that w obtains;
(3) p the write address that produces according to the write address generator, to write respectively in p the dual port RAM through step (2) move to right each bit of the p Bit data that cyclic shift obtains, the write address generator is used to produce distinguishes p corresponding write address when each p Bit data writes toward p dual port RAM, its production method is: for the 1st p Bit data, its sequence number k is 0, the content of reading from 0 address storaging unit of read-only memory (ROM) is p write address of the 1st p Bit data, the production method of the write address of (w-1) individual p Bit data that it is follow-up is that p write address of a back p Bit data added up by p write address of previous p Bit data and 1 obtain, for (w+1) individual p Bit data, its sequence number k is w, the content of reading from 1 address storaging unit of ROM is p the write address of (w+1) individual p Bit data, the production method of the write address of (w-1) individual p Bit data that it is follow-up is that p write address of a back p Bit data added up by p write address of previous p Bit data and 1 obtain, the rest may be inferred, and (d * w) the pairing write address of individual p Bit data produces in this way and obtains;
The production method of the content of storing among the ROM is: for the 1st p Bit data, its sequence number k is 0, gets i for from 0 to p-1 integer, at first, calculates p Indx value, then, calculates the individual initially write address Addr of p according to the Indx value
WR, Addr wherein
WRAnd the relation between the Indx is as follows:
Addr
WR＝mod(floor(Indx/p)，d)×w+floor(Indx/(d×p))
Wherein floor (Indx/p) expression Indx is divided exactly the merchant that p obtains, mod (floor (Indx/p), d) expression asks floor (Indx/p) to divide exactly the remainder that d obtains, floor (Indx/ (d * p)) represents that then Indx divides exactly the merchant that d * p obtains, exchange sequence according to the p Bit data, earlier p initial write address carried out the order exchange, carry out the identical circulative shift operation that moves to right according to the operation of the cyclic shift that moves to right of the 1st p Bit data p initial write address after to the order exchange again, the p that an obtains write address is high-order in order on a left side, low level carries out the binary bits data and links in the memory cell of the 0 address indication that deposits ROM on the right side, for (w+1) individual p Bit data (sequence number k is w), get i for from (w * p) is to the integer of (w+1) * p-1, calculate p Indx value earlier, then, calculate p initial write address Addr according to the Indx value
WRExchange sequence according to the p Bit data, earlier p initial write address carried out the order exchange, carry out the identical circulative shift operation that moves to right according to the operation of the cyclic shift that moves to right of w p Bit data p initial write address after to the order exchange again, the p that obtains write address binary bits data link in the memory cell of the 1 address indication that deposits ROM in, the rest may be inferred, and the content of d memory cell according to said method produces and obtains among the ROM, and the capacity of ROM is d * (p * m
1) bit, wherein,
Wherein
Represent to round up computing, promptly need m
1Individual bit is represented (d-1) * w value;
(4) step (3) finish frame data are all write p dual port RAM after, according to reading the address of reading that address generator produces, parallel read-out p Bit data from p dual port RAM, p dual port RAM to read the address all identical, it produces by Cnt
RAnd Cnt
CTwo parts addition constitutes, Cnt
RBe a mould be d * w add the w counter, work as Cnt
RCalculated value is 0 o'clock by (d-1) * w redirect, Cnt
CThen carrying out mould is 1 counting that adds of w, and the initial value of two counters all is 0;
(5) move to left cyclic shifter to each p Bit data of reading by step (4) according to a data high position on a left side, low level carries out cyclic shift left on the right side, the p Bit data that obtains after the cyclic shift that moves to left is the output of determinant block interleaved device, and the computational methods of the number of times SL of cyclic shift are as follows left:
SL＝mod(floor(j/(d/gcd(d，p)))，gcd(d，p))
Wherein j represents the sequence number of the p Bit data read from p dual port RAM, and value is the integer on 0 to d * w-1, gcd (d, p) then the greatest common divisor of d and p is asked in expression, (j/ (d/gcd (d, p))) expression j is divided exactly the (merchant that d/gcd (d, p)) obtains to floor, mod (floor (j/ (d/gcd (d, p))), gcd (d, p)) expression floor (j/ (d/gcd (d, p))) divide exactly gcd (d, the remainder that p) obtains.
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| CN104158654A (en) * | 2014-08-25 | 2014-11-19 | 中国石油大学(华东) | Interweaving technology-based key stream generation method and device |
| CN109891756A (en) * | 2019-01-31 | 2019-06-14 | 香港应用科技研究院有限公司 | The scalable shift unit of segmentation can be reset |
| CN111030780A (en) * | 2019-12-16 | 2020-04-17 | 中国科学院国家空间科学中心 | Configurable parallel bit grouping interleaver and interleaving method |
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| CN1171392C (en) * | 2000-12-29 | 2004-10-13 | 中兴通讯股份有限公司 | Method and device for interleaving and deinterleaving of parallel cascade convolution code |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104158654A (en) * | 2014-08-25 | 2014-11-19 | 中国石油大学(华东) | Interweaving technology-based key stream generation method and device |
| CN104158654B (en) * | 2014-08-25 | 2018-01-16 | 中国石油大学(华东) | A kind of key stream generating method and device based on interleaving technology |
| CN109891756A (en) * | 2019-01-31 | 2019-06-14 | 香港应用科技研究院有限公司 | The scalable shift unit of segmentation can be reset |
| CN109891756B (en) * | 2019-01-31 | 2023-03-28 | 香港应用科技研究院有限公司 | Resettable segmented scalable shifter |
| CN111030780A (en) * | 2019-12-16 | 2020-04-17 | 中国科学院国家空间科学中心 | Configurable parallel bit grouping interleaver and interleaving method |
| CN111030780B (en) * | 2019-12-16 | 2022-07-12 | 中国科学院国家空间科学中心 | Configurable parallel bit grouping interleaver and interleaving method |
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| CN111478750B (en) * | 2020-03-12 | 2022-10-14 | 普联技术有限公司 | Data parallel interleaving method, terminal equipment and computer storage medium |
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