CN109872161A - A kind of chip and system accelerating IOTA subchain transaction verification process - Google Patents
A kind of chip and system accelerating IOTA subchain transaction verification process Download PDFInfo
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Abstract
Present disclose provides a kind of chips and system for accelerating IOTA subchain transaction verification process.Wherein, the chip for accelerating IOTA subchain transaction verification process includes ReRAM comprising memory modules, memory modules are connected with subchain transaction verification module, and memory modules are configured as storing the cryptographic Hash of the transaction of unauthenticated mistake；The subchain transaction verification module includes multiplying logic array, XOR logic array and logic array and cyclic shift logic array；Controller is configured as: being transferred the data in memory modules and is input in subchain transaction verification module；The control signal of respective array in the subchain transaction verification module is exported according to keccak Encryption Algorithm, whether the cryptographic Hash to verify the currently transaction of unauthenticated mistake is correct and accelerates IOTA subchain transaction verification process.It deposits interior calculating structure using ReRAM, avoids data movement of the data between CPU and memory, substantially reduces the mobile expense of data, accelerate the processing speed of subchain transaction verification process.
Description
Technical field
The disclosure belongs to block chain field more particularly to a kind of chip for accelerating IOTA subchain transaction verification process and is
System.
Background technique
Only there is provided background technical informations relevant to the disclosure for the statement of this part, it is not necessary to so constitute first skill
Art.
Block chain technology is to be verified using block linked data structure and storing data, is aided with common recognition mechanism, Encryption Algorithm
Equal strategies reach a kind of distributed account book technology of access and transmission safety, are widely used in financial transaction, credit system, clothes
Business field etc..With the rapid development of the smart fields such as smart city, car networking, the strategy based on Internet of Things net system security mechanism
Research is concerned, tradition with chain structure storage information block chain technology be not able to satisfy big data under Internet of Things background,
The demands such as high-throughput, penny ante, therefore met the tendency of with the block chain technology of DAG (directed acyclic graph) data structure storage information
And give birth to, it is the most significant with IOTA.IOTA is the novel settlement of transactions of a revolutionary character and data transfer layer designed for Internet of Things.
It is based on new distribution type account book Tangle (entanglement) and transaction data is connected to DAG (directed acyclic graph) net in the form of block structure
In network, the transaction inefficiencies of traditional block chain are overcome, form novel decentralization P2P system common recognition, there is zero transaction fee, height
The features such as TPS (transaction throughput).
When inventor's hair carries out the calculating of subchain transaction verification process now with conventional processors (such as CPU, GPU),
A large amount of results of intermediate calculations, which will lead between memory and CPU, there is the mobile consumption of huge data, increases computing relay, drags slow meter
Energy consumption is also increased while calculation process.
Summary of the invention
An aspect of this disclosure is provided a kind of chip for accelerating IOTA subchain transaction verification process, is deposited using ReRAM
Interior calculating structure can be avoided data movement of the data between CPU and memory, reduce the mobile expense of data, accelerate subchain
The processing speed of transaction verification process.
A kind of technical solution of the chip of acceleration IOTA subchain transaction verification process of the disclosure are as follows:
A kind of chip accelerating IOTA subchain transaction verification process, comprising:
ReRAM, the ReRAM include memory modules, and the memory modules are connected with subchain transaction verification module, described interior
Storing module is configured as storing the cryptographic Hash of the transaction of unauthenticated mistake；The subchain transaction verification module includes multiplying logic array
Column, XOR logic array and logic array and cyclic shift logic array；
Controller is configured as:
It transfers the data in memory modules and is input in subchain transaction verification module；
The control signal of respective array in the subchain transaction verification module is exported, according to keccak Encryption Algorithm with verifying
Whether the cryptographic Hash of the transaction of current unauthenticated mistake is correct and accelerates IOTA subchain transaction verification process.
Further, the subchain transaction verification module is that sponge calculates structure.
The advantages of above-mentioned technical proposal, is that sponge calculates and uses sponge function in structure, that is, utilizes limited shape
State receives the input bit element flow of any length, then can satisfy the output of any length, improves the calculating of subchain transaction verification
Speed.
Further, the controller, is also configured to
The cryptographic Hash of the transaction of the unauthenticated mistake stored in the memory modules transferred is calculated structure to sponge to fill out
It fills；
By absorption process and extrusion process, final output hashed value.
The advantages of above-mentioned technical proposal is, keccak Encryption Algorithm integrally uses sponge to calculate structure, be divided into absorption and
Squeeze two stages.The core displacement f of keccak Encryption Algorithm is acted on 5 × 5 × 64 three-dimensional matrice.Entire f shares 24
Wheel, every wheel include 5 links θ, ρ, π, χ, τ.5 links of algorithm are respectively acting on the different dimensions of three-dimensional matrice.θ ring
Section is the linear operation acted on column；ρ link be act on per together on linear operation, by per together on 64 bits into
Row circulative shift operation；π link is the linear operation integrally moved on to the element on per pass on another road；χ link is to act on
Nonlinear operation in every a line is equivalent to 5 bits in every a line replacing with another 5 bit；τ link is additive constant ring
Section.The stereo enciphered thought and sponge structure of keccak Encryption Algorithm, sponge function can be established to be input to arbitrarily from random length
The mapping of length output.
Further, the controller, is also configured to
Whether the current transaction of verifying is by other transaction verifications, if so, the cryptographic Hash of the transaction of unauthenticated mistake is deposited
Storage is into memory modules.
Further, the controller, is also configured to
In the case where verifying the correct situation of cryptographic Hash of transaction of current unauthenticated mistake, it is current unauthenticated to continue verifying
Exchange transaction basic unit in All Activity transaction amount numerical value and whether be zero, if not zero, then base of trading
The error in data of this unit.
Further, the controller, is also configured to
The current unauthenticated exchange of verifying transaction basic unit in All Activity transaction amount numerical value with
After being zero, continue the validity of judgement transaction basic unit.
Further, the controller, is also configured to
When basic unit of trading meets following either condition, determine that transaction basic unit is invalid；
(1) transaction of current unauthenticated mistake is No. 0 transaction in transaction basic unit；
(2) transaction of current unauthenticated mistake is not first transaction in transaction basic unit transaction List Table.
Further, the chip further includes data cache module, and be used to store in cache module is not tested
The cryptographic Hash for the transaction demonstrate,proved and the intermediate result of subchain transaction verification module.
Further, interconnection circuit is also serially connected between the data cache module and subchain transaction verification module.
The advantages of above-mentioned technical proposal, is that interconnection circuit is for realizing data cache module and subchain transaction verification module
It communicates between the two.
Another aspect of the disclosure provides a kind of transaction verification system, deposits interior calculating structure using ReRAM, can
It avoids data of the data between CPU and memory mobile, reduces the mobile expense of data, accelerate the place of subchain transaction verification process
Manage speed.
A kind of technical solution of transaction verification system of the disclosure are as follows:
A kind of transaction verification system, the chip including acceleration IOTA subchain transaction verification process described above.
The beneficial effect of the disclosure is:
(1) chip of the acceleration IOTA subchain transaction verification process of the disclosure includes ReRAM and controller, wherein ReRAM
Including memory modules and subchain transaction verification module, controller is by transferring the transaction of the unauthenticated mistake stored in memory modules
Cryptographic Hash be input in subchain transaction verification module, then the subchain transaction verification module is exported using keccak Encryption Algorithm
The control signal of middle respective array, it is whether correct to verify the cryptographic Hash of transaction of current unauthenticated mistake, reduce CPU with it is interior
The mobile expense of data between depositing, greatly reduces the calculation delay of subchain transaction verification process, accelerates the transaction of IOTA subchain
Verification process.
(2) chip of the acceleration IOTA subchain transaction verification process of the disclosure, using the multiple array structure of ReRAM, so that
For the parallel computation of keccak Encryption Algorithm during subchain transaction verification, substantially increase subchain transaction verification process and
Row degree, improves overall performance.
(3) ReRAM in the chip of the acceleration IOTA subchain transaction verification process of the disclosure includes multiplying logic array, exclusive or
Logic array, with logic array and cyclic shift logic array, the characteristics of taking full advantage of ReRAM internal calculation structure attribute,
The utilization rate of ReRAM is improved, IOTA subchain transaction verification process is finally accelerated.
Detailed description of the invention
The Figure of description for constituting a part of this disclosure is used to provide further understanding of the disclosure, and the disclosure is shown
Meaning property embodiment and its explanation do not constitute the improper restriction to the disclosure for explaining the disclosure.
Fig. 1 is that the tips that respectively trades is directed toward schematic diagram in Bundle that the embodiment of the present disclosure provides.
Fig. 2 is the chip carrier composition for the acceleration IOTA subchain transaction verification process that the embodiment of the present disclosure provides.
Fig. 3 (a) be the embodiment of the present disclosure provide multiply logical operation schematic diagram.
Fig. 3 (b) is the XOR logic operation schematic diagram that the embodiment of the present disclosure provides.
Fig. 3 (c) be the embodiment of the present disclosure provide with logical operation schematic diagram.
Fig. 3 (d) is the cyclic shift logical operation schematic diagram that the embodiment of the present disclosure provides.
Fig. 4 is the complementation process schematic that the embodiment of the present disclosure provides.
Fig. 5 is each parallel computation module design schematic diagram of Hash verification process that the embodiment of the present disclosure provides.
Specific embodiment
It is noted that following detailed description is all illustrative, it is intended to provide further instruction to the disclosure.Unless another
It indicates, all technical and scientific terms used herein has usual with disclosure person of an ordinary skill in the technical field
The identical meanings of understanding.
It should be noted that term used herein above is merely to describe specific embodiment, and be not intended to restricted root
According to the illustrative embodiments of the disclosure.As used herein, unless the context clearly indicates otherwise, otherwise singular
Also it is intended to include plural form, additionally, it should be understood that, when in the present specification using term "comprising" and/or " packet
Include " when, indicate existing characteristics, step, operation, device, component and/or their combination.
Term is explained:
IOTA is a kind of novel digital encryption currency, is absorbed in the transaction issues solved between machine and machine (M2M).
The blueprint of the following machine economy (machine economy) is constructed by realizing the payment of machine and machinery compartment no deal expense.
IOTA is provided efficiently, and safety is light, real-time micro- transaction, and does not generate tranaction costs.It is open source, decentralization
Digital encryption currency is designed exclusively for Internet of Things, it is real-time micro- transaction, and can simply and easily be expanded
Exhibition.IOTA is to be based on entanglement (Tangle) rather than block chain technology.
The directed acyclic graph that Tangle is made of transaction block, transaction common recognition are that the transaction of new cochain is tested by certain rule
Two existing unauthenticated transaction (tips) on chain are demonstrate,proved, transaction is legal, and the transaction of new cochain is connected to and is tested if being verified
Card is traded and is stored in Tangle.Specific rule is that, when network node initiates a transaction, which needs in Tangle
In by certain random chance rule select two tips (transaction of unauthenticated mistake), oneself will be directed toward the two tips, and
After completing a small amount of PoW (proof of work), broadcast synchronization is carried out in a network；It is illegal to be verified transaction, then reselects
Tips simultaneously repeats the above steps.It selects the process of two unauthenticated transaction for random walk process, it is random to can be analyzed to MCMC
Selection course and subchain transaction verification process.Its migration rule are as follows: migration person initiates walk process from certain point, and each step is based on
MCMC stochastic selection algorithm is concentrated from the verifier for directly verifying the point and selects next verifier, then the selected transaction of verifying and
Its subchain transaction (i.e. directly verifying or indirect verification transaction) legitimacy, if be verified transaction essential information it is legal and verifying
It trades in the verified subchain of person without honeysuckle, then continues migration, until at migration to Tangle boundary node, as selected by the transaction
Two tips.In entire random walk process, subchain transaction verification process is after selecting verifier each time, to require
It is traversed forward based on BFS algorithm and essential information verifying is carried out to the verifier and its subchain transaction, traversal is until some is marked
Until being denoted as " confirmed " (fully validated) or " consistent " (having guaranteed consistency) transaction.
In the open source of IOTA is realized, Tangle network node is divided into light node and two kinds of roles of full node.Full node
Safeguard that Tangle network, database information, updating decision shine, the processes such as MCMC random selection and subchain transaction verification.Light node
Full node need to be connected to ask for random walk result, part to it when it initiates transaction for the user for initiating transaction
PoW request and broadcast transaction.As user volume increases, when a large number of users initiates transaction and selects to full node request tips
When, the full node in part need to handle the processes such as the subchain transaction verification largely traded and random walk, and part transaction is caused to wait
Cochain overlong time influences Tangle and integrally trades throughput, in addition the complete unbearable huge computational load of node in part and collapse
It bursts.For the trading processing process of full node, found through experiment statistics, it is random to swim during entire transaction initiation and cochain
Walking process, to account for overall used time specific gravity larger, and in random walk process, MCMC random selection process and subchain transaction verification
Process holding time is longer.Therefore, the disclosure will carry out acceleration design to wherein subchain transaction verification process, to reduce full section
Point computational load, accelerates trading processing speed.
With the appearance of novel non-volatile memory device, there will be better solution for problems.Based on resistance
The ReRAM of value storing data is a kind of more solution in forward position now, it possess the DRAM that matches in excellence or beauty read or write speed and it is non-easily
The storage characteristics of mistake.Meanwhile the Cross-Bar structure that ReRAM has allows it to have the ability for running simple multiply-add operation, and
Large number of Cells allows it to possess powerful computation capability in ReRAM structure.Compared with CPU, with degree of parallelism
Height computes repeatedly the preferable advantage of ability；It is compared compared with GPU, with the relatively low advantage of power consumption.Most of all,
The mobile consumption of data calculated can greatly reduce between memory and CPU is directly carried out in the memory of ReRAM medium, to greatest extent
Realize that higher handling capacity and lower data postpone using limited memory bandwidth in ground.
In the random walk process of IOTA block chain, the smallest blocks data of Tangle are a transaction, and are initiated primary
The basic unit of process of exchange is Bundle.I.e. when initiating primary transaction, handed over for wherein exporting transaction, input transaction and member
It is easily numbered and is packed into Bundle, No. 0 transaction is that tail trades, and does not record Transaction Information, other each transaction additional one
A member transaction is to record other information.The Hash of two selected tips of each transaction is filled to trunk tip and branch
Tip field, wherein tail transaction two tips be random walk selection result, other transaction branch tip be directed toward with
Tail transaction identical branch tip, trunk tip are directed toward Bundle insider transaction, the tips respectively to trade in entire Bundle
It is directed toward as shown in Figure 1.
Therefore, the tail that the traversal point of subchain transaction verification process is each Bundle trades.In subchain transaction verification
In the process, using certain point as starting point, the direction of Xiang Zilian (directly or indirectly verifying transaction) carries out BFS traversal, each step time
During going through, subchain transaction verification process mainly includes following verification step:
(1) verify whether the transaction is marked as " PREFILLED_SLOT ", i.e. the transaction by other transaction verifications, but
It does not record in the database, i.e. situation Unit 1 in Fig. 2.
(2) whether Hash calculation result of the verifying tail exchange in Bundle be correct, wherein adding using keccak
Close algorithm is basic data with part field, carries out verification calculating.
(3) numerical value of the transaction amount of All Activity of the verifying tail exchange in Bundle and whether be zero, if not
It is zero, then Bundle error in data.
(4) if tail transaction is Bundle the 0th transaction, but it is not first friendship in Bundle transaction List Table
Easily, then Bundle is considered as invalid.
By analyzing subchain transaction verification process, step (2) hash calculation process, i.e. keccak Encryption Algorithm
Application process needs largely multiply, add, exclusive or, displacement, complementation.Therefore, the disclosure is devised for Hash verification process
Corresponding Hash calculation unit is that above five kinds of operations wherein included are decomposed into corresponding computing unit, then combines
It forms, achieves efficient parallel calculating.Interior calculating structure is deposited using ReRAM, avoids number of the data between CPU and memory
According to movement, the mobile expense of data is substantially reduced, the processing speed of subchain transaction verification process is accelerated.
After entire subchain transaction verification process carries out function division according to aforementioned four step, as shown in Fig. 2, the present embodiment
A kind of acceleration IOTA subchain transaction verification process chip integrated stand composition.
As shown in Fig. 2, a kind of chip of acceleration IOTA subchain transaction verification process of the present embodiment, comprising: ReRAM, control
Device, data buffering module and interconnection circuit processed.
Modules are described in detail below:
(1)ReRAM
ReRAM includes memory modules, and the memory modules are connected with subchain transaction verification module.The memory modules are matched
It is set to the cryptographic Hash for storing the transaction of unauthenticated mistake；
Wherein, memory modules are used to store the Hash of the transaction of tail acquired by BFS (breadth First of figure) ergodic process
Value, the data are by the input as subchain transaction verification module.
The subchain transaction verification module includes multiplying logic array, XOR logic array and logic array and cyclic shift
Logic array.
Subchain transaction verification module is main calculating center, is realized in the verifying calculating and step 2 of aforementioned four step
Hash calculation unit Parallel Implementation.
The calculating of subchain transaction verification module focuses primarily upon Hash authentication unit, and main body calculating operation is keccak encryption
Algorithm after being filled to input data, by absorption (absorb) process and squeezes its working principle is that sponge calculates structure
(squeeze) process of pressure, final output hashed value, calculating process is as shown in Fig. 2 Hash authentication unit.
Absorption process are as follows: the input message by filling is one group according to every r bit, several inputs is divided into be grouped,
The r bit of internal state and input grouping s [1] are subjected to XOR operation, using its result and initial c bit capacity as function f's
R bit of output valve of function f and input grouping s [2] are then carried out exclusive or by input value, by c after its result and output valve
Capacity is used as the input value of function f again, is executed repeatedly until the last one input grouping is calculated and completed.Wherein, r and c are
Positive integer；Internal state, which calculates, defaults original state when starting, that is, is defaulted as " 0 " of r+c bit；Function f refers to
The sponge function of keccak Encryption Algorithm, that is, entire keccak Encryption Algorithm calculating process.
Extrusion process is to save as r bit in function f output valve output grouping z [i], and by entire output valve
(r+c bit) is again inputted into function f, repeats above-mentioned taking-up output grouping operation, the output of the length needed for obtaining
Data.Include θ, tetra- ρ & π, χ, τ units in principal function, function f each unit operation is decomposed, the logic after decomposition includes
Largely multiply, add, with, displacement, complementation, for various logic operation mode, Fig. 3 shows illustrating for various operations
It is bright.For multiplying, adding, with operation, (a), (b), (c) are shown such as in Fig. 3, for shifting function, by taking ROR (1100,2) as an example, and conversion
It is as shown in formula 7 for matrix multiplication, and matrix unit is mapped to, former number (1100) is as a wordline high position in upper, low level
It is connected under, unit matrix is written in cell after accordingly adjusting, and corresponding positions are with rear up to as a result, as shown in Fig. 3 (d).
For complementation, calculating process is as shown in Figure 4.For 32, if dividend a is divided by divisor b, their quotient
32 are not exceeded centainly with remainder.It is 0 that a, which is converted into high 32, first, low 32 temp_a for a.B is converted into high by 32
Position be b, low 32 be 0 temp_b.At the beginning of each cycle, temp_a is moved to left one, end mends 0, with temp_b ratio
Compared with if temp_a is greater than temp_b, temp_a subtracts temp_b plus 1, otherwise continues cycling through the period.32 execution are recycled altogether
After, high 32 of temp_a are remainder, and low 32 are quotient.Using above-mentioned each design cell, according to hash algorithm
Process and respective formula feature, by Hash calculation unit Parallel Design as shown in figure 5, each element is according to its computation rule in array
It is designed as parallel computation unit, to realize the maximization degree of parallelism of each unit arithmetic operation during kecaak encrypted authentication.
Keccak Encryption Algorithm integrally uses sponge to calculate structure, is divided into absorption and squeezes two stages.Keccak encryption
The core displacement f of algorithm is acted on 5 × 5 × 64 three-dimensional matrice.Entire f shares 24 wheels, every wheel include 5 link θ, ρ, π,
χ,τ.5 links of algorithm are respectively acting on the different dimensions of three-dimensional matrice.θ link is the linear fortune acted on column
It calculates；ρ link is the linear operation acted on per on one, will carry out circulative shift operation per 64 bits on one；π link is
Element on per pass is integrally moved on into the linear operation on another road；χ link is the nonlinear operation acted in every a line, phase
When in 5 bits in every a line are replaced with another 5 bit；τ link is additive constant link.The solid of keccak Encryption Algorithm
Thought and sponge structure are encrypted, sponge function can be established from random length and be input to the mapping that random length exports.
(2) controller is configured as:
It transfers the data in memory modules and is input in subchain transaction verification module；
The control signal of respective array in the subchain transaction verification module is exported, according to keccak Encryption Algorithm with verifying
Whether the cryptographic Hash of the transaction of current unauthenticated mistake is correct and accelerates IOTA subchain transaction verification process.
Be given below the detailed implementation process of the present embodiment, and combination algorithm pseudocode to the present embodiment based on ReRAM's
Hash verification process parallel computation strategy and the specific calculation process of part calculating operation are described in further detail.
(2.1) Hash verification process parallel computation strategy
The Hash verification process parallelization calculative strategy based on ReRAM of the present embodiment effectively reduces computation delay, drop
Low processor computational load, increases the TPS of IOTA trade network, meanwhile, it ensure that the area stabilization Hang He of the full node of IOTA
The reliability of block chain data.
(2.2) remainder calculative strategy
The present embodiment propose based on the remainder calculative strategy for adding, subtracting, shifting basic computational ele- ment, keep calculating process simple
Change, preferably played the advantage of ReRAM internal calculation structure, strategy is as follows:
In specific implementation, the controller, is also configured to
Whether the current transaction of verifying is by other transaction verifications, if so, the cryptographic Hash of the transaction of unauthenticated mistake is deposited
Storage is into memory modules.
In specific implementation, the controller, is also configured to
In the case where verifying the correct situation of cryptographic Hash of transaction of current unauthenticated mistake, it is current unauthenticated to continue verifying
Exchange transaction basic unit in All Activity transaction amount numerical value and whether be zero, if not zero, then base of trading
The error in data of this unit.
In specific implementation, the controller, is also configured to
The current unauthenticated exchange of verifying transaction basic unit in All Activity transaction amount numerical value with
After being zero, continue the validity of judgement transaction basic unit.
In specific implementation, the controller, is also configured to
When basic unit of trading meets following either condition, determine that transaction basic unit is invalid；
(a) transaction of current unauthenticated mistake is No. 0 transaction in transaction basic unit；
(b) transaction of current unauthenticated mistake is not first transaction in transaction basic unit transaction List Table.
(3) data buffering module
Centre of the data buffering module for input data and subchain transaction verification module in scratch-pad memory functional module
And other buffered datas as a result.
(4) interconnection circuit
Interconnection circuit is serially connected between the data cache module and subchain transaction verification module.
The present embodiment using ReRAM self structure advantage realization preferably deposit-calculate integrated function, realize caching rank
Parallel work-flow based on specific calculation alleviates the computational load of processor.Largely multiply, add, exclusive or, shifting due to existing in calculating
The operation such as position, the present embodiment targetedly design this, it is made preferably to have catered to ReRAM internal calculation structure category
Property, integral operation speed is improved, realizes and the entirety of the modular algorithm is accelerated, increases the operational capability of the full node of IOTA
And the parallel processing speeds of Transaction Information, block chain transaction handling capacity is improved, is provided for IOTA block chain transaction reliability
It ensures.
The present embodiment additionally provides a kind of transaction verification system comprising acceleration IOTA subchain transaction as shown in Figure 2 is tested
The chip of card process.
The transaction verification system of the present embodiment includes the chip for accelerating IOTA subchain transaction verification process, which includes
ReRAM and controller, wherein ReRAM includes memory modules and subchain transaction verification module, and controller is by transferring memory modules
The cryptographic Hash of the transaction of the unauthenticated mistake of middle storage is input in subchain transaction verification module, then uses keccak Encryption Algorithm
The control signal of respective array in the subchain transaction verification module is exported, to verify the Hash of the currently transaction of unauthenticated mistake
Whether value is correct, reduces the mobile expense of data between CPU and memory, greatly reduces the calculating of subchain transaction verification process
Time delay accelerates IOTA subchain transaction verification process.
The transaction verification system of the present embodiment includes the chip for accelerating IOTA subchain transaction verification process, which utilizes
The multiple array structure of ReRAM, so that being greatly improved for the parallel computation of keccak Encryption Algorithm during subchain transaction verification
The degree of parallelism of subchain transaction verification process, improves overall performance.
It should be understood by those skilled in the art that, embodiment of the disclosure can provide as method, system or computer program
Product.Therefore, the shape of hardware embodiment, software implementation or embodiment combining software and hardware aspects can be used in the disclosure
Formula.Moreover, the disclosure, which can be used, can use storage in the computer that one or more wherein includes computer usable program code
The form for the computer program product implemented on medium (including but not limited to magnetic disk storage and optical memory etc.).
The disclosure is referring to method, the process of equipment (system) and computer program product according to the embodiment of the present disclosure
Figure and/or block diagram describe.It should be understood that every one stream in flowchart and/or the block diagram can be realized by computer program instructions
The combination of process and/or box in journey and/or box and flowchart and/or the block diagram.It can provide these computer programs
Instruct the processor of general purpose computer, special purpose computer, Embedded Processor or other programmable data processing devices to produce
A raw machine, so that being generated by the instruction that computer or the processor of other programmable data processing devices execute for real
The device for the function of being specified in present one or more flows of the flowchart and/or one or more blocks of the block diagram.
These computer program instructions, which may also be stored in, is able to guide computer or other programmable data processing devices with spy
Determine in the computer-readable memory that mode works, so that it includes referring to that instruction stored in the computer readable memory, which generates,
Enable the manufacture of device, the command device realize in one box of one or more flows of the flowchart and/or block diagram or
The function of being specified in multiple boxes.
These computer program instructions also can be loaded onto a computer or other programmable data processing device, so that counting
Series of operation steps are executed on calculation machine or other programmable devices to generate computer implemented processing, thus in computer or
The instruction executed on other programmable devices is provided for realizing in one or more flows of the flowchart and/or block diagram one
The step of function of being specified in a box or multiple boxes.
Those of ordinary skill in the art will appreciate that realizing all or part of the process in above-described embodiment method, being can be with
Relevant hardware is instructed to complete by computer program, the program can be stored in a computer-readable storage medium
In, the program is when being executed, it may include such as the process of the embodiment of above-mentioned each method.Wherein, the storage medium can be magnetic
Dish, CD, read-only memory (Read-Only Memory, ROM) or random access memory (Random
AccessMemory, RAM) etc..
Although above-mentioned be described in conjunction with specific embodiment of the attached drawing to the disclosure, model not is protected to the disclosure
The limitation enclosed, those skilled in the art should understand that, on the basis of the technical solution of the disclosure, those skilled in the art are not
Need to make the creative labor the various modifications or changes that can be made still within the protection scope of the disclosure.
Claims (10)
1. a kind of chip for accelerating IOTA subchain transaction verification process characterized by comprising
ReRAM, the ReRAM include memory modules, and the memory modules are connected with subchain transaction verification module, the memory mould
Block is configured as storing the cryptographic Hash of the transaction of unauthenticated mistake；The subchain transaction verification module includes multiplying logic array, different
Or logic array, with logic array and cyclic shift logic array；
Controller is configured as:
It transfers the data in memory modules and is input in subchain transaction verification module；
The control signal of respective array in the subchain transaction verification module is exported according to keccak Encryption Algorithm, it is current to verify
Whether the cryptographic Hash of the transaction of unauthenticated mistake is correct and accelerates IOTA subchain transaction verification process.
2. a kind of chip for accelerating IOTA subchain transaction verification process as described in claim 1, which is characterized in that the subchain
Transaction verification module is that sponge calculates structure.
3. a kind of chip for accelerating IOTA subchain transaction verification process as claimed in claim 2, which is characterized in that the control
Device is also configured to
The cryptographic Hash of the transaction of the unauthenticated mistake stored in the memory modules transferred is calculated structure to sponge to be filled；
By absorption process and extrusion process, final output hashed value.
4. a kind of chip for accelerating IOTA subchain transaction verification process as described in claim 1, which is characterized in that the control
Device is also configured to
The current transaction of verifying whether by other transaction verifications, if so, by the cryptographic Hash of the transaction of unauthenticated mistake store to
In memory modules.
5. a kind of chip for accelerating IOTA subchain transaction verification process as described in claim 1, which is characterized in that the control
Device is also configured to
In the case where verifying the correct situation of cryptographic Hash of transaction of current unauthenticated mistake, continue the current unauthenticated transaction of verifying
The numerical value of the transaction amount of All Activity and whether be zero in the transaction basic unit at place, if not zero, then it trades substantially single
The error in data of member.
6. a kind of chip for accelerating IOTA subchain transaction verification process as claimed in claim 5, which is characterized in that the control
Device is also configured to
The current unauthenticated exchange of verifying transaction basic unit in All Activity transaction amount numerical value and be zero
Afterwards, continue the validity of judgement transaction basic unit.
7. a kind of chip for accelerating IOTA subchain transaction verification process as claimed in claim 6, which is characterized in that the control
Device is also configured to
When basic unit of trading meets following either condition, determine that transaction basic unit is invalid；
(1) transaction of current unauthenticated mistake is No. 0 transaction in transaction basic unit；
(2) transaction of current unauthenticated mistake is not first transaction in transaction basic unit transaction List Table.
8. a kind of chip for accelerating IOTA subchain transaction verification process as described in claim 1, which is characterized in that the chip
It further include data cache module, the cryptographic Hash and subchain of the transaction for the unauthenticated mistake for being used in cache module store
The intermediate result of transaction verification module.
9. a kind of chip for accelerating IOTA subchain transaction verification process as claimed in claim 8, which is characterized in that the data
Interconnection circuit is also serially connected between cache module and subchain transaction verification module.
10. a kind of transaction verification system, which is characterized in that including accelerating IOTA as claimed in any one of claims 1-9 wherein
The chip of chain transaction verification process.
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109697606A (en) * | 2018-09-30 | 2019-04-30 | 贝克链区块链技术有限公司 | The distributed network and the ecosystem of common recognition agreement are proved based on innovative prestige |
| CN111432026A (en) * | 2020-04-14 | 2020-07-17 | 杭州复杂美科技有限公司 | Parallel chain transaction execution method, device and storage medium |
| EP3937051A1 (en) * | 2020-07-08 | 2022-01-12 | Alipay (Hangzhou) Information Technology Co., Ltd. | Methods and apparatuses for processing transactions based on blockchain integrated station |
| US11336660B2 (en) | 2020-07-08 | 2022-05-17 | Alipay (Hangzhou) Information Technology Co., Ltd. | Methods and apparatuses for identifying replay transaction based on blockchain integrated station |
| US11463553B2 (en) | 2020-07-08 | 2022-10-04 | Alipay (Hangzhou) Information Technology Co., Ltd. | Methods and apparatuses for identifying to-be-filtered transaction based on blockchain integrated station |
| US11665234B2 (en) | 2020-07-08 | 2023-05-30 | Alipay (Hangzhou) Information Technology Co., Ltd. | Methods and apparatuses for synchronizing data based on blockchain integrated station |
| US11783339B2 (en) | 2020-07-08 | 2023-10-10 | Alipay (Hangzhou) Information Technology Co., Ltd. | Methods and apparatuses for transferring transaction based on blockchain integrated station |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107124267A (en) * | 2017-03-30 | 2017-09-01 | 宁波大学 | A kind of fixation bit wide key generation method on crypto chip |
| CN108089817A (en) * | 2016-11-23 | 2018-05-29 | 三星电子株式会社 | The method of storage system and its operating method and operating data processing system |
| CN108984789A (en) * | 2018-08-15 | 2018-12-11 | 赵东洋 | Method, apparatus, storage medium and the electronic equipment of distribution book keeping operation |
| CN108985732A (en) * | 2018-06-08 | 2018-12-11 | 中国地质大学（武汉） | The common recognition and account book data organization method and system of DAG technology based on no block |
| CN109035011A (en) * | 2018-06-08 | 2018-12-18 | 中国地质大学（武汉） | A kind of control method and system of block chain DAG width |
| CN109214795A (en) * | 2018-09-18 | 2019-01-15 | 北京物链互联科技有限公司 | A kind of block chain mixing common recognition method based on DAG algorithm |
| CN109218289A (en) * | 2018-08-03 | 2019-01-15 | 中山大学 | A kind of common recognition mechanism of the entanglement network proved based on work in series amount |
-
2019
- 2019-03-01 CN CN201910156445.1A patent/CN109872161B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108089817A (en) * | 2016-11-23 | 2018-05-29 | 三星电子株式会社 | The method of storage system and its operating method and operating data processing system |
| CN107124267A (en) * | 2017-03-30 | 2017-09-01 | 宁波大学 | A kind of fixation bit wide key generation method on crypto chip |
| CN108985732A (en) * | 2018-06-08 | 2018-12-11 | 中国地质大学（武汉） | The common recognition and account book data organization method and system of DAG technology based on no block |
| CN109035011A (en) * | 2018-06-08 | 2018-12-18 | 中国地质大学（武汉） | A kind of control method and system of block chain DAG width |
| CN109218289A (en) * | 2018-08-03 | 2019-01-15 | 中山大学 | A kind of common recognition mechanism of the entanglement network proved based on work in series amount |
| CN108984789A (en) * | 2018-08-15 | 2018-12-11 | 赵东洋 | Method, apparatus, storage medium and the electronic equipment of distribution book keeping operation |
| CN109214795A (en) * | 2018-09-18 | 2019-01-15 | 北京物链互联科技有限公司 | A kind of block chain mixing common recognition method based on DAG algorithm |
Non-Patent Citations (1)
| Title |
|---|
| DEBJYOTI BHATTACHARJEE ETC: "SHA-3 implementation using ReRAM based in-memory computing architecture", 《IEEE XPLORE》 * |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109697606A (en) * | 2018-09-30 | 2019-04-30 | 贝克链区块链技术有限公司 | The distributed network and the ecosystem of common recognition agreement are proved based on innovative prestige |
| CN111432026A (en) * | 2020-04-14 | 2020-07-17 | 杭州复杂美科技有限公司 | Parallel chain transaction execution method, device and storage medium |
| CN111432026B (en) * | 2020-04-14 | 2022-10-28 | 杭州复杂美科技有限公司 | Parallel chain transaction execution method, device and storage medium |
| EP3937051A1 (en) * | 2020-07-08 | 2022-01-12 | Alipay (Hangzhou) Information Technology Co., Ltd. | Methods and apparatuses for processing transactions based on blockchain integrated station |
| US11336660B2 (en) | 2020-07-08 | 2022-05-17 | Alipay (Hangzhou) Information Technology Co., Ltd. | Methods and apparatuses for identifying replay transaction based on blockchain integrated station |
| US11444783B2 (en) | 2020-07-08 | 2022-09-13 | Alipay (Hangzhou) Information Technology Co., Ltd. | Methods and apparatuses for processing transactions based on blockchain integrated station |
| US11463553B2 (en) | 2020-07-08 | 2022-10-04 | Alipay (Hangzhou) Information Technology Co., Ltd. | Methods and apparatuses for identifying to-be-filtered transaction based on blockchain integrated station |
| US11665234B2 (en) | 2020-07-08 | 2023-05-30 | Alipay (Hangzhou) Information Technology Co., Ltd. | Methods and apparatuses for synchronizing data based on blockchain integrated station |
| US11783339B2 (en) | 2020-07-08 | 2023-10-10 | Alipay (Hangzhou) Information Technology Co., Ltd. | Methods and apparatuses for transferring transaction based on blockchain integrated station |
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