CN117033093A

CN117033093A - Chip verification device and method, electronic device, and computer-readable storage medium

Info

Publication number: CN117033093A
Application number: CN202310571061.2A
Authority: CN
Inventors: 余志同; 张亚苹
Original assignee: Beijing Eswin Computing Technology Co Ltd; Haining Eswin IC Design Co Ltd
Current assignee: Beijing Eswin Computing Technology Co Ltd; Haining Eswin IC Design Co Ltd
Priority date: 2023-05-17
Filing date: 2023-05-17
Publication date: 2023-11-10

Abstract

The embodiment of the application discloses a chip verification device and method, electronic equipment and a computer readable storage medium. The chip verification device includes: the buffer module is used for writing in sampling data output by the chip to be verified based on the sampling clock signal; and reading out the sampled data to the conversion module based on the read clock signal; the sampling clock signal is determined according to a plurality of clock signals in at least one clock domain corresponding to the sampling data; the frequency of the sampling clock signal is greater than the frequency of the reading clock signal; the conversion module is used for converting the sampling data into waveform data; a display module for displaying a waveform result based on the waveform data; the waveform result is used for determining the verification result of the chip to be verified.

Description

Chip verification device and method, electronic device, and computer-readable storage medium

Technical Field

The present application relates to the field of electronic technologies, and in particular, to a chip verification device and method, an electronic device, and a computer readable storage medium.

Background

Currently, a programmable array logic (Field Programmable Gate Array, FPGA) verification platform can support chip verification, and the FPGA platform can collect output data of a chip to be verified based on a sampling clock, and perform waveform display on the output data of the chip to be verified, so that code problems of the chip to be verified are intuitively displayed. However, since various signals of the platform to be verified may not be synchronous or have different frequencies, in order to acquire complete output data, a higher sampling clock frequency is required, and the FPGA itself has limited resources, which results in a reduction in the amount of data acquired, and insufficient accuracy of the chip verification result.

Disclosure of Invention

The embodiment of the application provides a chip verification device and method, electronic equipment and a computer readable storage medium, which improve the accuracy of chip verification.

The technical scheme of the application is realized as follows:

the embodiment of the application provides a chip verification device, which comprises:

the buffer module is used for writing in sampling data output by the chip to be verified based on the sampling clock signal; and reading out the sampled data to a conversion module based on a read clock signal; the sampling clock signal is determined according to a plurality of clock signals in at least one clock domain corresponding to the sampling data; the frequency of the sampling clock signal is greater than the frequency of the reading clock signal;

the conversion module is used for converting the sampling data into waveform data;

a display module for displaying a waveform result based on the waveform data; the waveform result is used for determining the verification result of the chip to be verified.

The embodiment of the application provides a chip verification method, which comprises the following steps:

writing in sampling data output by a chip to be verified based on a sampling clock signal through a buffer module; and reading out the sampled data to a conversion module based on a read clock signal; the sampling clock signal is determined according to a plurality of clock signals in at least one clock domain corresponding to the sampling data; the frequency of the sampling clock signal is greater than the frequency of the reading clock signal;

Converting the sampling data into waveform data through the conversion module;

displaying, by a display module, a waveform result based on the waveform data; the waveform result is used for determining the verification result of the chip to be verified.

The embodiment of the application provides electronic equipment, which comprises:

a memory for storing a computer program;

and the processor is used for executing the chip verification method when the computer program runs.

The embodiment of the application provides a computer readable storage medium, on which a computer program is stored, for implementing the chip verification method when being executed by a processor.

The embodiment of the application provides a chip verification device, a chip verification method, chip verification equipment and a chip verification device, and a computer readable storage medium, wherein sampling data can be written into a cache module firstly and then sent to a conversion module by the cache module; therefore, the conversion module can receive the sampling data by adopting a reading clock signal with lower frequency than the sampling clock signal, the resource occupation of the conversion module is reduced, the capacity of the conversion module for receiving the data depth is increased, and the accuracy of the chip verification result to be verified can be improved based on the waveform result displayed by the data received by the conversion module.

Drawings

Fig. 1 is a schematic diagram of a chip verification process in the related art according to an embodiment of the present application;

fig. 2 is a schematic structural diagram of an alternative chip verification device according to an embodiment of the present application;

FIG. 3 is a schematic diagram of an alternative chip verification process according to an embodiment of the present application;

FIG. 4 is a schematic diagram of an alternative cache module according to an embodiment of the present application;

FIG. 5 is a schematic diagram of an alternative cache module according to an embodiment of the present application;

FIG. 6 is a schematic diagram of an alternative cache module according to an embodiment of the present application;

FIG. 7 is a schematic diagram of an alternative cache module according to an embodiment of the present application;

FIG. 8 is a schematic diagram of an alternative cache module according to an embodiment of the present application;

FIG. 9 is a schematic diagram of an alternative cache module according to an embodiment of the present application;

FIG. 10 is a schematic flow chart of an alternative chip verification method according to an embodiment of the present application;

fig. 11 is a schematic diagram of a hardware structure of an alternative electronic device according to an embodiment of the present application.

Detailed Description

The present application will be further described in detail with reference to the accompanying drawings, for the purpose of making the objects, technical solutions and advantages of the present application more apparent, and the described embodiments should not be construed as limiting the present application, and all other embodiments obtained by those skilled in the art without making any inventive effort are within the scope of the present application.

In the following description, reference is made to "some embodiments" which describe a subset of all possible embodiments, but it is to be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments and can be combined with one another without conflict.

In the following description, the terms "first", "second", "third" and the like are merely used to distinguish similar objects and do not represent a specific ordering of the objects, it being understood that the "first", "second", "third" may be interchanged with a specific order or sequence, as permitted, to enable embodiments of the application described herein to be practiced otherwise than as illustrated or described herein.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of the application only and is not intended to be limiting of the application.

In order to facilitate understanding of the present solution, before explaining the embodiments of the present application, an application background in the embodiments of the present application is explained.

Fig. 1 shows a schematic diagram of a chip verification process in the related art, as shown in fig. 1, sampling data (including signal_0 and signal_ … … signal_n) output by a chip 01 to be verified is transmitted to a chip verification device 10, and a waveform result of the sampling signal is output by the chip verification device 10. The chip verification device 10 includes a conversion (debug) module 101 and a display (monitor) module 102, where the function of storing data of the conversion module 101 and the chip 01 to be verified can be implemented by an FPGA platform, and other functions of the conversion module 101 and the display module 102 can be implemented by debug_software matched with the FPGA platform. The conversion module 101 may collect a sample clock (sampling clock) to collect the chip to be verified, convert the output signal into waveform data, send the waveform data to the display module 102, and the display module 102 displays a waveform result based on the waveform data. The FPGA platform itself is also a chip product, in which the conversion module 101 needs a sampling clock to trigger the acquisition of the output signal of the chip to be verified. Under the limitation of FPGA own resources, under the conditions that output signals are not synchronous, different frequencies or frequency differences are large, part of the output signals may not be acquired, so that the acquired signals are incomplete, and the accuracy of a chip verification result is affected. In order to collect all output signals, the sampling clock needs to be set to a higher frequency, but the time domain timing cannot be converged due to the excessively high frequency, so that the data depth (data depth) of the output data of the chip to be verified can only be reduced, namely the collected data volume is reduced, and the accuracy of the chip verification result can still be influenced. Taking an FPGA VU440 chip as an example, the data depth of the output data can be up to 131072, but in practical application, the design complexity and timing convergence of the chip need to be considered, and 4096 and 8192 are generally selected, so that the data depth is difficult to meet the verification requirement.

In order to solve the above-mentioned problems, an embodiment of the present application provides a chip verification device, and fig. 2 is a schematic structural diagram of an alternative chip verification device according to an embodiment of the present application. As shown in fig. 2, the chip authentication device 20 may include: the buffer module 201 is configured to write sampling data output by the chip to be verified based on the sampling clock signal; and reading out the sampled data to the verification module 202 based on the read clock signal; the sampling clock signal is determined according to a plurality of clock signals in at least one clock domain corresponding to the sampling data; the frequency of the sampling clock signal is greater than the frequency of the reading clock signal; a conversion module 202 for converting the sampled data into waveform data; a display module 203 for displaying a waveform result based on the waveform data; the waveform result is used for determining the verification result of the chip to be verified.

In the embodiment of the application, the sampling data can be determined from the output data of the chip to be verified, where the sampling data can be set according to actual needs, and the embodiment of the application is not limited. Illustratively, the output data includes three output signals: the sampling data may include at least one signal of signal_ A, signal _b and signal_c. The information amount contained in the sampling data can be set according to actual needs, and the embodiment of the application is not limited. The information amount of the sampled data may be 2 bits, 8 bits, or 16 bits, for example.

In the embodiment of the present application, the buffer module 201 may write the sampling data into the buffer module 201 based on the high-frequency sampling clock signal, and read the sampling data written in the buffer module 201 to the conversion module 202 based on the low-frequency reading clock signal. The frequency of the sampling clock signal is determined according to a clock corresponding to the sampling data, and the clock corresponding to the sampling data can comprise clock signals under different clock domains or different clock signals under the same clock domain; the frequency of the sampling clock signal may enable the buffer module 201 to write all sampling data into the buffer module 201, and the specific frequency may be set as required.

For example, the sampling data includes signal_b and signal_c, the clock of signal_b is clock1, the clock of signal_c is clock2, clock1 and clock2 are synchronous and the frequency of clock1 is twice that of clock2, the sampling clock signal may be clock1; therefore, the buffer module can collect all data of the signal_B and the signal_C under the triggering of the clock edge of the clock 1.

In the embodiment of the application, the sampling clock signal and the reading clock signal are mutually independent clock signals, and can be synchronous signals or asynchronous signals; the two signals may be frequency signals or different frequency signals, which is not limited in the embodiment of the present application.

In the embodiment of the present application, the cache module 201 includes a storage queue; the write pointer points to a location in the store queue to be written to and the read pointer points to a location in the store queue to be read to. In the case that the sampling clock signal is valid, the buffer module 201 may write sampling data in the location to be written, and update the location to be written to the next location in the storage queue; in this manner, the buffer module 201 may continue writing the sample data at the next location in the case where the next sampling clock signal is valid. After writing the sample data in the storage queue, the buffer module 201 may read the sample data in the position to be read to the conversion module 202 each time the read clock signal is valid, and update the position to be read to the next position in the storage queue.

In an embodiment of the application, the store queue may be a first-in first-out (First Input First Output, FIFO) memory. In some embodiments of the application, the FIFO may be implemented by a block random memory (block Random Access Memory, BRAM).

In some embodiments of the present application, the buffer module 201 may start writing the sampling data into the buffer module 201 after receiving the write enable instruction; the buffer module 201 may begin reading out the sampled data in the buffer module 201 after receiving the read enable instruction.

In some embodiments of the present application, the buffer module 201 may perform an initialization process on the buffer module 201 in response to the initialization instruction, and delete all data in the buffer module 201.

In some embodiments of the present application, the buffer module 201 may stop writing data after writing a round of data in the storage queue, and may return to the initial writing position after writing a round of data in the storage queue to restart writing data. The buffer module 201 may stop reading data after the data in the storage queue is read for one round, or return to the initial reading position to restart reading data after the data in the storage queue is read for one round; in this regard, it may be set as needed, and the embodiment of the present application is not limited.

In some embodiments of the present application, the buffer module 201 may write all the sampled data and then read all the sampled data at once; the buffer module 201 may write the preset number of sample data into the storage queue, read the sample data once, then write the preset number of sample data again, and read the sample data again until all sample data are collected by the conversion module 202.

In the embodiment of the present application, the conversion module 202 may read the sampling data from the buffer module 201, convert the sampling data into waveform data, and then the display module 203 displays the waveform result of the sampling data based on the waveform data.

Referring to fig. 2, fig. 3 shows a schematic diagram of an alternative chip verification process, as shown in fig. 3, sampling data (including signal_0 and signal_1_ 1 … … signal_n) output by the chip 02 to be verified is written into the buffer module 201 in the chip verification device 20 based on the sampling clock signal write_clk, then is read from the buffer module 201 to the conversion module 202 based on the read clock signal read_clk, and is recorded as signal_0_data_0 and signal_1_data_1 … … signal_n_data_n, and finally, waveform results are output through the display module 203.

It can be appreciated that, since the sampled data may be written into the buffer module 201 first, and then sent to the conversion module 202 by the buffer module 201; in this way, the conversion module 202 may receive the sampling data by using a read clock signal with a frequency lower than that of the sampling clock signal, so as to reduce the resource occupation of the conversion module 202 and improve the capability of the conversion module 202 to receive the data depth, and thus, the accuracy of the chip verification result to be verified can be improved based on the waveform result displayed by the data received by the conversion module 202.

Based on fig. 2, fig. 4 shows a schematic structural diagram of an alternative cache module, and as shown in fig. 4, the cache module 201 further includes a store queue 2011. A storage queue 2011, configured to store the sampled data in a location to be written when the sampling clock signal is valid; and reading out the sampling data at the position to be read to the conversion module 202 in the case that the reading clock signal is valid.

In the embodiment of the present application, the storage queue 2011 includes a plurality of locations for storing data, a write pointer points to a location to be written, and a read pointer points to a location to be read. The buffer module 201 may sequentially write and read data in a positional order. In the embodiment of the present application, the buffer module 201 writes a data in a position to be written, and the position pointed by the writing pointer moves to the next position, so as to obtain an updated position to be written; thus, when the sampling clock signal is valid next time, the data to be written is written into the updated position to be written. In the embodiment of the present application, the buffer module 201 reads a data from a position to be read, and the position pointed by the reading pointer moves to the next position to obtain an updated position to be read; in this way, the buffer module 201 will read out the sample data from the updated data to be read when the next time the read clock signal is active.

In the embodiment of the present application, the sampling clock signal may be active high, and the storage queue 2011 may be triggered to write a sample data when the rising edge of the sampling clock signal arrives. The sampling clock signal may be active low, and the storage queue 2011 may be triggered to write a sample data when the falling edge of the sampling clock signal arrives. The read clock signal may be active high and may trigger the store queue 2011 to read a sample data to the conversion module 202 when the rising edge of the read clock signal arrives. The read clock signal may be active low, and the store queue 2011 may be triggered to read a sample data to the conversion module 202 when the falling edge of the read clock signal arrives.

It can be understood that the buffer module 201 can write the sampling data into the storage queue 2011 according to the sampling clock signal and the position indicated by the write pointer, and read the sampling data in the storage queue 2011 according to the position indicated by the read clock signal and the read pointer; in this way, the relative independence of reading and writing of data in the store queue can be improved, thereby reducing the frequency of the read clock signal.

In some embodiments of the application, the data depth of the store queue 2011 may be set as desired. As shown in fig. 4, the memory queue 2011 may adjust the bit width to the target bit width in response to the bit width adjustment instruction in the case of receiving the bit width adjustment instruction. Here, the bit width adjustment instruction includes a target bit width, which is used to characterize the maximum bit width supported by each location in the storage queue 2011. Illustratively, the store queue 2011 is a FIFO implemented based on an FPGA platform that can be configured with 18K BRAM and 36K BRAM. In the case of data depth 1024, 1 BRAM of 18K needs to be configured if the target bit width is 16 bits, and 1 BRAM of 36K needs to be configured if the target bit width is 36 bits. In this way, flexibility in storing data by the store queue 2011 can be improved.

Based on fig. 4, fig. 5 shows a schematic structural diagram of an alternative cache module, and as shown in fig. 5, the cache module 201 further includes an enabling module 2012; the enabling module 2012 is configured to send a write enable signal to the store queue 2011 in response to the write instruction; and, in response to the read instruction, transmitting a read enable signal to the store queue 2011; the storage queue 2011 is further configured to store, in response to the write enable signal, the sampled data at a location to be written indicated by the write pointer when the sampling clock signal is valid; and reading out the sampling data at the position to be read indicated by the read pointer to the conversion module 202 in the case that the read clock signal is valid.

In the embodiment of the present application, the enabling module 2012 may send a write enabling signal to the storage queue 2011 when receiving the write command, and the storage queue 2011 responds to the write enabling signal and writes the sampling data to the location to be written when the sampling clock signal is valid. In the embodiment of the present application, the storage queue 2011 does not trigger the write data even if the sampling clock signal is valid in the case that the write enable signal is not received.

In the embodiment of the present application, the write instruction may be an instruction from outside the cache module 201; or may be an instruction inside the buffer module 201, for example, the buffer module 201 may arrive the 5 th sampling data as a write instruction; the embodiments of the present application are not limited in this regard.

In the embodiment of the present application, the enabling module 2012 may send a read enable signal to the storage queue 2011 when receiving a read instruction, and the storage queue 2011 responds to the read enable signal and reads the sample data from the to-be-read position when the read clock signal is valid. In the embodiment of the present application, the memory queue 2011 does not trigger the read data even if the read clock signal is valid in the case that the read enable signal is not received.

In the embodiment of the present application, the read instruction may be an instruction from outside the cache module 201; or may be an instruction inside the cache module 201, for example, the cache module 201 may take the write data in the storage queue 2011 greater than or equal to the read threshold as a read instruction; the embodiments of the present application are not limited in this regard.

It can be appreciated that, by enabling module 2012 to control the timing of the start of reading and writing of the storage queue 2011, the flexibility of reading and writing of the cache module is improved.

Based on fig. 5, fig. 6 shows a schematic structural diagram of an alternative cache module, and as shown in fig. 6, the cache module 201 further includes a pointer position management module 2013. An enabling module 2012, further configured to send a write location update signal to the pointer location management module 2013 if the sampling clock signal is valid; and, in case the read clock signal is valid, transmitting a read location update signal to the pointer location management module 2013; the pointer position management module 2013 is further configured to update the position to be written to a next position in response to the writing position update signal, so as to obtain an updated position to be written; the updated position to be written is sent to a storage queue 2011; and responding to the reading position updating signal, updating the position to be read to the next position, and obtaining the updated position to be read; the updated position to be read is sent to a storage queue 2011; the storage queue 2011 is further configured to store the sampled data in the updated position to be written when the sampling clock signal is valid; and reading the updated sampling data at the position to be read to the conversion module 202 under the condition that the reading clock signal is valid.

In an embodiment of the present application, the enabling module 2012 may receive the sampling clock signal, and since the storage queue 2011 may write the sampling data when the sampling clock signal is valid, the enabling module 2012 may send a write-once location update signal to the pointer location management module 2013 when the sampling clock signal is valid each time, and the pointer location management module 2013 may update the location to be written to the next location in response to the write location update signal.

In some embodiments of the present application, the store queue 2011 writes the sample data only after receiving the write enable signal from the enable module 2012, and the location to be written changes. Thus, the enabling module 2012 may send a write location update signal to the pointer location management module 2013 after receiving the write instruction if the sampling clock signal is valid.

In the embodiment of the present application, the enabling module 2012 may receive the read clock signal, and since the storage queue 2011 may read the sampling data when the read clock signal is valid, the enabling module 2012 may send a read position update signal to the pointer position management module 2013 when the read clock signal is valid each time, and the pointer position management module 2013 may update the position to be read to the next position in response to the read position update signal.

In some embodiments of the present application, the memory queue 2011 only reads the sample data after receiving the read enable signal from the enable module 2012, and the position to be read changes. Accordingly, the enabling module 2012 may send a read location update signal to the pointer location management module 2013 after receiving the read instruction if the read clock signal is valid.

In the embodiment of the present application, when the data in the storage queue 2011 is empty, the position to be written is the initial writing position, if the writing enabling signal is valid and the sampling clock signal is valid, the sampling data can be written into the initial writing position, and meanwhile, the pointer position management module 2013 updates the position to be written to the next position of the initial writing position. After the location to be written is updated, the pointer location management module 2013 sends the updated location to be written to the storage queue 2011, so that the storage queue 2011 can continue writing the sampling data to the received updated location to be written when the sampling clock signal is valid again. If the location to be written is not updated, the storage queue 2011 will stop writing the sample data without receiving the updated location to be written.

In the embodiment of the present application, when the data in the storage queue 2011 is empty, the position to be read is the initial read position, the initial read position does not point to any position in the storage queue 2011, and after the storage queue receives the reading enabling instruction, the position to be read is updated from the initial read position to the initial write position. At this time, if the read enable signal is valid and the read clock signal is valid, the sample data may be read from the initial write location, and the pointer location management module 2013 updates the location to be read to the next location of the initial write location. After the position to be read is updated, the pointer position management module 2013 sends the updated position to be read to the storage queue 2011, so that the storage queue 2011 can continue to read the sampling data from the updated position to be read under the condition that the reading clock signal is valid again. If the location to be read is not updated, the storage queue 2011 will stop reading the sampled data without receiving the updated location to be written.

It can be understood that the enabling module 2012 can update the position to be written according to the sampling clock signal pointer position management module 2013, update the position to be read according to the reading clock signal pointer position management module 2013, and send the real-time position to be written and the real-time position to be read to the storage queue 2011, so that the storage queue 2011 can write or read the sampling data in the corresponding position according to the instruction of the pointer position management module 2013, thereby improving the accuracy of the writing position and the reading position.

In some embodiments of the present application, the enabling module 2012 is further configured to send a write location stop update signal to the pointer location management module 2013 in response to the write stop signal; the writing position stop update signal is used for instructing the pointer position management module 2013 to stop updating the position to be written; and, in response to the read stop signal, transmitting a read position stop update signal to the pointer position management module 2013; the read position stop update signal is used to instruct the pointer position management module 2013 to stop updating the position to be read.

In this embodiment of the present application, the enabling module 2012 may receive a write stop signal, and send a write position stop update signal to the pointer position management module 2013 in response to the write stop signal, to instruct the pointer position management module 2013 to stop updating the position to be written, so that the storage queue 2011 cannot receive a new position to be written, and will stop writing the sampled data.

In the embodiment of the present application, the write stop signal may be a signal from outside the cache module 201, or a signal from a module other than the enable module 2012 inside the cache module 201; in this regard, it may be set as needed, and the embodiment of the present application is not limited.

In an embodiment of the present application, the enabling module 2012 may receive a read stop signal, and send a read position stop update signal to the pointer position management module 2013 in response to the read stop signal, to instruct the pointer position management module 2013 to stop updating the position to be read, so that the storage queue 2011 cannot receive a new position to be read, and will stop reading the sampled data.

In the embodiment of the present application, the read stop signal may be a signal from the outside of the cache module 201, or may be a signal from a module other than the enabling module 2012 inside the cache module 201; in this regard, it may be set as needed, and the embodiment of the present application is not limited.

It may be appreciated that the enabling module 2012 may control the storage queue 2011 to stop writing by sending a write stop signal to the pointer position management module 2013 to cause the pointer position management module 2013 to stop updating the to-be-written position; and, sending a read stop signal to the pointer position management module 2013 to cause the pointer position management module 2013 to stop updating the position to be read, thereby stopping the storage queue 2011 and further controlling the storage queue 2011 to stop reading; in this way, flexibility in reading data and writing data in the memory queue 2011 is improved.

Based on fig. 6, fig. 7 shows a schematic structural diagram of an alternative cache module, and as shown in fig. 7, the cache module 201 further includes a storage state management module 2014. A storage status management module 2014, configured to send a write stop signal to the enable module 2012 in response to the write stop instruction; and, in response to the read stop instruction, sending a read stop signal to the enable module 2012; or, the position to be written and the position to be read are obtained from the pointer position management module 2013; in the case where the position to be written is equal to the preset writing position, a writing stop signal is sent to the enabling module 2012; and, in the case where the position to be read is equal to the preset read position, transmitting a read stop signal to the enabling module 2012.

In this embodiment of the present application, the storage status management module 2014 may obtain the position to be written and the position to be read from the pointer position management module 2013, determine whether the storage queue 2011 can continue writing according to the relationship between the position to be written and the preset writing position, and send a write stop signal to the enabling module 2012 if it is determined that writing cannot be continued. The storage status management module 2014 may determine whether the storage queue 2011 can continue to read according to the relationship between the to-be-read position and the preset read position, and send a read stop signal to the enabling module 2012 if it is determined that the reading cannot continue.

In some embodiments, the preset writing position may be the highest storage position of the storage queue, and after the preset writing position is written with the sample data, all the positions in the storage queue 2011 write the data, and one round of data writing is completed. In some embodiments, the preset writing position may also be any position in the preset storage queue 2011. The preset writing position can be set according to the requirement, and the embodiment of the application is not limited. The store queue 2011 illustratively includes 1000 storage locations: position 1-position 1000, the preset writing position 1000 indicates that the storage queue 2011 stops writing after the sampling data is fully written.

In some embodiments, the preset read position may be the highest storage position of the storage queue, and after the sample data of the preset read position is read, the sample data of all positions in the storage queue 2011 are read, and one round of data reading is completed. In some embodiments, the preset read position may also be any position in the preset storage queue 2011, where the preset read position is less than or equal to the preset write position. The preset reading position can be set according to the requirement, and the embodiment of the application is not limited. The store queue 2011 illustratively includes 1000 storage locations: position 1-position 1000, the preset read position 1000 indicates that the sample data in the storage queue 2011 is read empty and then stops reading.

It is understood that the storage status management module 2014 may determine whether the storage queue 2011 can continue to read or write the sample data according to the to-be-read position and the to-be-written position, send the write stop signal to the enable module 2012 to stop writing the sample data into the storage queue 2011, and send the read stop signal to the enable module 2012 to stop reading the sample data from the storage queue 2011. In this way, the storage status management module 2014 can implement read-write control on the storage queue 2011 according to the actual storage condition of the sampled data in the storage queue 2011, so as to improve the accuracy of reading and writing the sampled data in the storage queue 2011.

Based on fig. 7, fig. 8 shows a schematic structural diagram of an optional cache module, and as shown in fig. 8, the cache module 201 further includes a mode control module 2015. The mode control module 2015 is configured to send an offline operation indication signal to the pointer position management module 2013 in response to the offline operation instruction; the pointer position management module 2013 is further configured to send a position to be written and a position to be read to the storage state management module 2014 in response to the offline operation indication signal.

In an embodiment of the present application, the operation modes of the storage queue 2011 include an on-line mode and an off-line mode. In the on-line mode, the memory queue 2011 may continuously read the sample data while writing the sample data. In the on-line mode, the pointer location management module 2013 needs to send the location to be written and the location to be read to the storage status management module 2014. In this way, the storage status management module 2014 may instruct, through the enabling module 2012 and the pointer position management module 2013, the storage queue 2011 to stop writing the sample data in a case where the to-be-written position is equal to the preset writing position; the storage status management module 2014 may instruct the storage queue 2011 to stop reading the sample data through the enabling module 2012 and the pointer position management module 2013 in a case where the position to be read is equal to the preset read position.

In some embodiments of the present application, the enable module 2012 may operate in an on-line mode without receiving an off-line on-indication signal.

In some embodiments of the present application, the mode control module 2015 may send an on-line work instruction signal to the enable module 2012 in case of receiving an on-line work instruction, where the on-line work instruction signal is used to instruct the pointer management module 2013 not to send the location to be read and the location to be written to the storage status management module 2014; in this way, the storage status management module 2014 will not send the write stop signal and the read stop signal to the enable module, and the storage queue 2011 will continue to write and read the sample data.

In some embodiments of the present application, the storage queue 2011 may operate in an on-line mode in the case where the number of sample data is less than or equal to the total number of data locations in the storage queue 2011, so that the storage queue 2011 stops writing data if writing all sample data is completed, and stops reading data if reading all sample data is completed, reducing the resource consumption of the storage queue.

It can be appreciated that the storage queue 2011 works in an on-line mode, and the sampled data written into the storage queue 2011 can be controlled by the write enable signal and the write position stop update signal, so that the waveform result is displayed by the conversion module 202 and the display module 203 through the selected part of the sampled data. The mode control module 2015 can improve the flexibility of the working mode of the storage queue 2011, and further improve the flexibility of the read sampling data.

Based on fig. 8, fig. 9 shows a schematic structural diagram of an alternative cache module, and as shown in fig. 9, the cache module 201 further includes an initialization module 2016. The initialization module 2016 is further configured to perform an initialization process on the cache module 202 in response to the initialization command.

In an embodiment of the present application, the initialization process represents restoring all of the cache modules 202 to an initial state. For example, the initialization process may include flushing all sample data in the buffer module 202.

In the embodiment of the present application, the initialization instruction may be an instruction from outside the cache module 202 or an instruction inside the cache module 202. For example, the pointer position management module 2013 may send an initialization instruction to the initialization module 2016 when it determines that the storage queue 2011 is full of data and all data is read according to the to-be-written position, the to-be-read position, the preset writing position, and the preset reading position.

It will be appreciated that the initialization module 2016 may restore the buffer module 202 to the initial state, and thus, the buffer module 202 may transmit the sampled data to the conversion module 203 again based on the sampling clock signal and the reading clock signal, and further display the waveform through the display module. In this way, the flexibility of the buffer module 202 to read the sampled data may be improved.

In some embodiments of the present application, the initialization module 2016 is further configured to send an initialization indication signal to the enable module 2012, the pointer location management module 2013, and the store queue 2011; an enabling module 2012, further configured to stop sending the write enable signal and the read enable signal to the store queue 2011 in response to the initialization indication signal; the pointer position management module 2013 is further configured to update the position to be written to the initial writing position in response to the initialization indication signal; updating the position to be read to an initial reading position; store queue 2011 is also used to empty data in response to an initialization instruction.

In the embodiment of the present application, when receiving the initialization instruction, the initialization module 2016 sends an initialization instruction signal to the enable module 2012, the pointer position management module 2013, and the storage queue 2011, where the initialization instruction signal is used to instruct the enable module 2012, the pointer position management module 2013, and the storage queue 2011 to perform initialization processing.

In an embodiment of the present application, the enabling module 2012 may stop sending the write enable signal and the read enable signal to the store queue 2011 when receiving the initialization indication signal. For example, if the write enable signal and the read enable signal are both active high, the enable module 2012 may adjust both the write enable signal and the read enable signal to low in response to the initialization indication signal.

In the embodiment of the present application, the pointer position management module 2013 may update the position to be written to the initial writing position and update the position to be read to the initial reading position when receiving the initialization indication signal; the initial write position and the initial read position are positions in the memory queue 2011 where sample data is not written.

In the embodiment of the present application, the storage queue 2011 may empty the internal data when receiving the initialization indication signal.

It will be appreciated that the initialization module 2016, upon receiving an initialization instruction, may restore the cache module 202 to an initial state through respective initialization processes of the enable module 2012, the pointer position management module 2013, and the store queue 2011.

Based on the above-mentioned chip verification device, an embodiment of the present application provides a chip verification method, as shown in fig. 10, the method may include: S101-S103.

S101, writing sampling data output by a chip to be verified based on a sampling clock signal through a buffer module; and reading out the sampled data to the conversion module based on the read clock signal; the sampling clock signal is determined according to a plurality of clock signals in at least one clock domain corresponding to the sampling data; the frequency of the sampling clock signal is greater than the frequency of the reading clock signal;

S102, converting the sampling data into waveform data through a conversion module;

s103, displaying a waveform result based on the waveform data through a display module; the waveform result is used for determining the verification result of the chip to be verified.

In the embodiment of the application, the chip verification device can write the sampling data of the chip data to be verified into the buffer module under the condition that the sampling clock signal is effective, and then read the written sampling data under the condition that the reading clock signal is effective. The buffer module may buffer the sampled data such that the frequency of the read clock signal may be lower than the frequency of the sampling clock signal. The conversion module of the chip verification device reads the sampling data under the low-frequency reading clock signal, and then the waveform result of the sampling data is displayed through the display module.

It can be understood that the chip verification device can enable the conversion module to read the sampling data under the reading clock signal lower than the sampling clock signal frequency through the buffer module, so that the clock frequency of the conversion module is reduced, the capability of the conversion module for processing the sampling data is improved, the integrity of the waveform result of the sampling data can be improved, and the accuracy of the chip verification result to be verified is further improved.

In some embodiments, the method further comprises: storing the sampling data in a position to be written indicated by a writing pointer under the condition that the sampling clock signal is valid through a storage queue; and under the condition that the reading clock signal is valid, reading out the sampling data at the position to be read indicated by the reading pointer to the conversion module.

In some embodiments, the method further comprises: transmitting a write-in enabling signal to the storage queue through an enabling module in response to a write-in instruction; and, in response to a read instruction, sending a read enable signal to the store queue; responding to the write-in enabling signal through the storage queue, and storing the sampling data in the position to be written in under the condition that the sampling clock signal is valid; and under the condition that the reading clock signal is valid, reading out the sampling data on the position to be read to the conversion module.

In some embodiments, the method further comprises: sending, by the enabling module, a write location update signal to the pointer location management module if the sampling clock signal is valid; and sending a read location update signal to the pointer location management module if the read clock signal is valid; updating the position to be written to the next position by the pointer position management module in response to a writing position updating signal to obtain an updated position to be written; transmitting the updated position to be written to the storage queue; and responding to the reading position updating signal, updating the position to be read to the next position, and obtaining the updated position to be read; transmitting the updated position to be read to the storage queue; storing the sampling data in the updated position to be written under the condition that the sampling clock signal is valid through the storage queue; and under the condition that the reading clock signal is valid, reading the sampling data at the updated position to be read to the conversion module.

In some embodiments, the method further comprises: transmitting a write position stop update signal to the pointer position management module in response to a write stop signal by the enabling module; the writing position stop updating signal is used for indicating the pointer position management module to stop updating the position to be written; and, in response to a read stop signal, sending a read position stop update signal to the pointer position management module; the reading position stop updating signal is used for indicating the pointer position management module to stop updating the position to be read.

In some embodiments, the method further comprises: the storage state management module responds to a write-stop instruction and sends the write-stop signal to the enabling module; and, in response to a read stop instruction, sending the read stop signal to the enable module; or, the position to be written and the position to be read are obtained from the pointer position management module; sending the write stop signal to the enabling module under the condition that the position to be written is equal to a preset writing position; and sending the reading stop signal to the enabling module under the condition that the position to be read is equal to a preset reading position.

In some embodiments, the method further comprises: the mode control module responds to an off-line working instruction and sends an off-line working instruction signal to the pointer position management module; and responding to the off-line work indication signal through the pointer position management module, and sending the position to be written and the position to be read to the storage state management module.

In some embodiments, the method further comprises: and responding to the bit width adjusting instruction through the storage queue, and adjusting the bit width to the target bit width.

In some embodiments, the method further comprises: the initialization instruction is responded through an initialization module, and the initialization instruction signal is sent to an enabling module, a pointer position management module and a storage queue; stopping sending a write enabling signal and a read enabling signal to the storage queue in response to the initialization indication signal through the enabling module; the pointer position management module responds to the initialization indication signal to update the position to be written to an initial writing position; updating the position to be read to an initial reading position; and responding to the initialization instruction through the storage queue, and clearing data.

Fig. 11 is a schematic structural diagram of an alternative electronic device according to an embodiment of the present application, as shown in fig. 11, the electronic device 110 includes a memory 1107, a processor 1108, and a computer program stored in the memory 1107 and executable on the processor 1108; wherein the processor 1108 is configured to execute the chip authentication method according to the previous embodiment when executing the computer program.

It will be appreciated that the electronic device 110 also includes a bus system 1109; the various components in the electronic device 110 are coupled together by a bus system 1109. It is appreciated that the bus system 1109 is employed to facilitate connected communications between these components. The bus system 1109 includes a power bus, a control bus, and a status signal bus in addition to a data bus.

It will be appreciated that the memory in embodiments of the application may be either volatile memory or nonvolatile memory, and may include both volatile and nonvolatile memory. Wherein the nonvolatile Memory may be Read-Only Memory (ROM), programmable Read-Only Memory (Programmable Read-Only Memory, PROM), erasable programmable Read-Only Memory (Erasable Programmable Read-Only Memory, EPROM), electrically erasable programmable Read-Only Memory (Electrically Erasable Programmable Read-Only Memory, EEPROM), magnetic random access Memory (Ferromagnetic Random Access Memory, FRAM), flash Memory (Flash Memory), magnetic surface Memory, optical disk, or Read-Only optical disk (Compact Disc Read-Only Memory, CD-ROM); the magnetic surface memory may be a disk memory or a tape memory. The volatile memory may be random access memory (Random Access Memory, RAM) which acts as an external cache. By way of example, and not limitation, many forms of RAM are available, such as static random access memory (Static Random Access Memory, SRAM), synchronous static random access memory (Synchronous Static Random Access Memory, SSRAM), dynamic random access memory (Dynamic Random Access Memory, DRAM), synchronous dynamic random access memory (Synchronous Dynamic Random Access Memory, SDRAM), double data rate synchronous dynamic random access memory (Double Data Rate Synchronous Dynamic Random Access Memory, ddr SDRAM), enhanced synchronous dynamic random access memory (Enhanced Synchronous Dynamic Random Access Memory, ESDRAM), synchronous link dynamic random access memory (SyncLink Dynamic Random Access Memory, SLDRAM), direct memory bus random access memory (Direct Rambus Random Access Memory, DRRAM). The memory described by embodiments of the present application is intended to comprise, without being limited to, these and any other suitable types of memory.

The method disclosed by the embodiment of the application can be applied to a processor or realized by the processor. The processor may be an integrated circuit chip having signal processing capabilities. In implementation, the steps of the above method may be performed by integrated logic circuits of hardware in a processor or by instructions in the form of software. The processor may be a general purpose processor, DSP, or other programmable logic device, discrete gate or transistor logic device, discrete hardware components, or the like. The processor may implement or perform the methods, steps, and logic blocks disclosed in embodiments of the present application. The general purpose processor may be a microprocessor or any conventional processor or the like. The steps of the method disclosed in the embodiment of the application can be directly embodied in the hardware of the decoding processor or can be implemented by combining hardware and software modules in the decoding processor. The software module may be located in a storage medium, the storage medium being located in a memory, the processor reading signals in the memory, the steps of the method being performed in combination with its hardware.

Embodiments of the present application provide a computer readable storage medium having stored thereon a computer program which, when executed by a processor, performs the steps of the above method.

In the several embodiments provided by the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above described device embodiments are only illustrative, e.g. the division of the modules is only one logical function division, and there may be other divisions in practice, such as: multiple modules or components may be combined, or may be integrated into another system, or some features may be omitted, or not performed. In addition, the various components shown or discussed may be coupled or directly coupled or communicatively coupled to each other via some interface, whether indirectly coupled or communicatively coupled to devices or modules, whether electrically, mechanically, or otherwise.

The foregoing is merely exemplary embodiments of the present application and is not intended to limit the scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and scope of the present application are included in the protection scope of the present application.

Claims

1. A chip authentication apparatus, comprising:

2. The apparatus of claim 1, wherein the caching module comprises:

a storage queue, configured to store, when the sampling clock signal is valid, the sampling data at a position to be written indicated by a write pointer; the method comprises the steps of,

and under the condition that the reading clock signal is valid, reading out the sampling data at the position to be read indicated by the reading pointer to the conversion module.

3. The apparatus of claim 2, wherein the caching module further comprises:

the enabling module is used for responding to the writing instruction and sending a writing enabling signal to the storage queue; and, in response to a read instruction, sending a read enable signal to the store queue;

the storage queue is further configured to store the sampling data in the location to be written in, in response to the write enable signal, when the sampling clock signal is valid; and under the condition that the reading clock signal is valid, reading out the sampling data on the position to be read to the conversion module.

4. The apparatus of claim 3, wherein the caching module further comprises: a pointer position management module;

the enabling module is further configured to send a write location update signal to the pointer location management module when the sampling clock signal is valid; and sending a read location update signal to the pointer location management module if the read clock signal is valid;

the pointer position management module is further configured to update the position to be written to a next position in response to a writing position update signal, so as to obtain an updated position to be written; transmitting the updated position to be written to the storage queue; and responding to the reading position updating signal, updating the position to be read to the next position, and obtaining the updated position to be read; transmitting the updated position to be read to the storage queue;

the storage queue is further configured to store the sampled data in the updated location to be written when the sampling clock signal is valid; and under the condition that the reading clock signal is valid, reading the sampling data at the updated position to be read to the conversion module.

5. The apparatus of claim 4, wherein the device comprises a plurality of sensors,

the enabling module is further used for responding to a write-in stop signal and sending a write-in position stop update signal to the pointer position management module; the writing position stop updating signal is used for indicating the pointer position management module to stop updating the position to be written;

and, in response to a read stop signal, sending a read position stop update signal to the pointer position management module; the reading position stop updating signal is used for indicating the pointer position management module to stop updating the position to be read.

6. The apparatus of claim 4 or 5, wherein the caching module further comprises:

the storage state management module is used for responding to the write-in stop instruction and sending the write-in stop signal to the enabling module; and, in response to a read stop instruction, sending the read stop signal to the enable module; or,

acquiring the position to be written and the position to be read from the pointer position management module; sending the write stop signal to the enabling module under the condition that the position to be written is equal to a preset writing position; and sending the reading stop signal to the enabling module under the condition that the position to be read is equal to a preset reading position.

7. The apparatus of claim 6, wherein the caching module further comprises:

the mode control module is used for responding to the offline working instruction and sending an offline working instruction signal to the pointer position management module;

the pointer position management module is further configured to send the position to be written and the position to be read to the storage state management module in response to the offline operation indication signal.

8. The apparatus of claim 2, wherein the device comprises a plurality of sensors,

the memory queue is further configured to adjust the bit width to a target bit width in response to a bit width adjustment instruction.

9. A chip authentication method, comprising:

converting the sampling data into waveform data through the conversion module;

10. An electronic device, comprising

A memory for storing a computer program;

a processor for performing the chip authentication method as claimed in claim 9 when said computer program is run.

11. A computer readable storage medium, having stored thereon a computer program for implementing the chip authentication method according to claim 9 when executed by a processor.