CN116820349A - SDRAM deterministic time delay method and system - Google Patents

Abstract

The application discloses an SDRAM deterministic delay method and system, which solve the problem of low delay accuracy of a DRFM system based on SDRAM. A deterministic latency method comprising the steps of: responding to the delay updating and the completion of all read-write processes of the current ping-pong operation, and acquiring the data length of the input and output data stream caches; judging the relation between the writing address of SDRAM in writing state and new delay amount in ping-pong operation, and updating the initial position of a new round of ping-pong operation; and compensating and correcting delay drift introduced by the depth change of the input and output cache data. According to the application, the delay drift caused by the depth change of the input and output buffer data is compensated and corrected through the BRAM in the FPGA, and finally the deterministic delay of the DRFM system based on double SDRAM ping-pong reading and writing is realized.

Description

SDRAM deterministic time delay method and system

Technical Field

The application relates to the technical field of microwave signal storage and forwarding, in particular to a deterministic delay method and a deterministic delay system based on SDRAM.

Background

The digital radio frequency memory system (DRFM) is a microwave signal storing and forwarding system and is used for completing the functions of sampling, storing, modulating, forwarding and the like of radio frequency signals and realizing the characteristic simulation of the distance, speed, RCS and the like of radar targets. The DRFM system can adapt to changeable, quick-changing and complex signal environments, so that the relativity between target echo/interference signals and the radar is kept, and a vivid complex electromagnetic environment can be generated. Therefore, the DRFM system is widely applied to an electronic countermeasure and semi-physical simulation system and becomes an integral part of modern war.

In the DRFM system, the storing and forwarding of the signal refers to storing the received radar signal, reading the stored signal and modulating the stored signal by delaying for a certain time as required, and finally outputting the signal through a digital-to-analog converter for simulating the radar target distance. For the delay forwarding process, the storage bandwidth and capacity of the data are key indicators of the system. SDRAM has the advantages of high read-write bandwidth and large storage capacity, can realize the expansion of bandwidth and capacity in a multi-piece splicing mode, and is widely applied to DRFM systems. Because the data and address interfaces of SDRAM are shared for reading and writing, a single chip cannot simultaneously perform reading and writing operations, and two groups of SDRAM are generally adopted for ping-pong reading and writing so as to ensure the continuity of data reading and writing. However, because the read-write operation of the SDRAM is complex, a series of operations such as precharging, row selection and the like are required to be performed for one time, so that the execution time of the read-write action is uncertain, the drift of the actual storage forwarding time of the DRFM system based on the SDRAM during time delay updating is caused, and the time delay accuracy of the DRFM system is reduced. Therefore, a deterministic latency method is needed to meet the latency accuracy requirements of SDRAM-based DRFM systems.

Disclosure of Invention

The embodiment of the application provides an SDRAM deterministic delay method and system, which solve the problem of low delay accuracy of a DRFM system based on SDRAM.

The embodiment of the application provides an SDRAM deterministic delay method, which comprises the following steps:

responding to the delay updating and the completion of all read-write processes of the current ping-pong operation, and acquiring the data length of the input and output data stream caches;

judging the relation between the writing address of SDRAM in writing state and new delay amount in ping-pong operation, and updating the initial position of a new round of ping-pong operation;

and compensating and correcting delay drift introduced by the depth change of the input and output cache data.

Further, the specific flow of ping-pong operation of the two SDRAMs further comprises the steps of:

judging the relation between the write address and the delay amount of the first SDRAM in the write state;

the first SDRAM is ready to enter a read state in response to the write address of the first SDRAM being not less than the delay amount, the second SDRAM is ready to enter a write state, or the first SDRAM is ready to continue the write state in response to the write address of the first SDRAM being less than the delay amount, the second SDRAM is ready to enter the read state;

and updating the states and addresses of the two SDRAM chips according to the current delay amount.

Preferably, the delay drift is compensated and corrected by adopting the BRAM inside the FPGA.

Preferably, the buffer data length monitoring is set in the input data stream buffer and the output data stream buffer.

Further, in response to the delay amount update, the relationship between the write address of the SDRAM in the write state and the delay amount is re-judged.

Further, in response to the delayed output being turned off, the two pieces of SDRAM alternately store the input data stream.

Further, the output data stream buffer is reset and emptied.

The embodiment of the application also provides an SDRAM deterministic delay system which is used for realizing the deterministic delay method described in the embodiment, and comprises an input data stream buffer, a ping-pong read-write engine, an output data stream buffer and delay compensation storage. The input data stream enters the ping-pong read-write engine through the input data stream buffer, and the output data stream buffer and the delay compensation storage. The input data stream buffer is used for matching the data bandwidth between the input data stream and the ping-pong read-write engine and processing the data across clock domains. The ping-pong read-write engine is used for completing ping-pong operation and data stream management. The output data stream buffer is used for matching the data bandwidth between the ping-pong read-write engine and the output data stream and processing the data bandwidth across clock domains. The delay compensation storage is used for compensating delay drift introduced by the depth change of the input and output buffer data when correcting delay updating, and transmitting the output data stream.

Further, the ping-pong read-write engine comprises a master control state machine, an SDRAM write driver and an SDRAM read driver. The master control state machine is used for controlling the read-write direction, address management and data scheduling of the SDRAM. The SDRAM write driver is used for realizing the bottom layer of SDRAM write operation. The SDRAM read driver is used for realizing the bottom layer of SDRAM read operation.

The embodiment of the present application also provides a computer readable storage medium, on which a computer program is stored, which when executed by a processor, implements the method according to any of the above embodiments.

The above at least one technical scheme adopted by the embodiment of the application can achieve the following beneficial effects:

according to the application, the delay drift caused by the depth change of the input and output buffer data is compensated and corrected through the BRAM in the FPGA, and finally the deterministic delay of the DRFM system based on double SDRAM ping-pong reading and writing is realized.

Drawings

The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute a limitation on the application. In the drawings:

FIG. 1 is a flow chart of a deterministic latency method according to an embodiment of the present application;

FIG. 2 is a table tennis operation flow chart of two SDRAM according to the embodiment of the present application;

FIG. 3 is a block diagram of a deterministic latency system according to an embodiment of the present application;

FIG. 4 is a control flow diagram of a deterministic latency system according to an embodiment of the present application;

FIG. 5 is a diagram of a ping-pong read-write engine according to an embodiment of the present application.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the technical solutions of the present application will be clearly and completely described below with reference to specific embodiments of the present application and corresponding drawings. It will be apparent that the described embodiments are only some, but not all, embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

The following describes in detail the technical solutions provided by the embodiments of the present application with reference to the accompanying drawings.

FIG. 1 is a flow chart of a deterministic latency method according to an embodiment of the present application.

The embodiment of the application provides an SDRAM deterministic delay method, which comprises the following steps:

step 110, responding to the delay updating and the completion of all read-write processes of the current ping-pong operation, and acquiring the data length of the input and output data stream caches;

preferably, the buffer data length monitoring is set in the input data stream buffer and the output data stream buffer.

For example, a monitor of the buffer data length is added in an input data stream buffer and an output data stream buffer connected with an SDRAM-based ping-pong read-write engine for obtaining the buffer data length.

When the delay updating is carried out, after all read-write operations in the current ping-pong read-write engine are completed, acquiring the data length of the input and output data stream caches;

step 120, judging the relation between the write address of SDRAM in a write state and the new delay amount in ping-pong operation, and updating the initial position of a new round of ping-pong operation;

for example, judging the relation between the writing address of SDRAM in writing state and new delay amount in ping-pong read-write engine, and updating the initial position of the ping-pong read-write engine for new read-write operation;

and 130, compensating and correcting delay drift caused by depth change of input and output cache data.

Because the internal BRAM has stronger and more stable anti-interference capability relative to the external, the delay drift is preferably compensated and corrected by adopting the FPGA internal BRAM.

Adopting a BRAM in the FPGA to compensate and correct delay drift caused by depth change of input and output cache data;

further, the method further comprises the steps of:

step 140, starting a new round of ping-pong operation to ensure uninterrupted and stable output of the data stream, and so on until all delayed ping-pong operations are completed.

FIG. 2 is a table tennis operation flow chart of two SDRAM according to the embodiment of the present application.

Further, the specific flow of ping-pong operation of the two SDRAMs further comprises the steps of:

step 111, judging the relation between the write address of the first SDRAM in the write state and the delay amount;

step 112, in response to the write address of the first SDRAM not being less than the delay amount, the first SDRAM is ready to enter a read state, the second SDRAM is ready to enter a write state, or in response to the write address of the first SDRAM being less than the delay amount, the first SDRAM is ready to continue the write state, the second SDRAM is ready to enter a read state;

and 113, updating the states and addresses of the two SDRAM according to the current delay amount.

The current delay amount refers to the delay amount of a new round after delay updating.

Further, the method further comprises the steps of:

and 114, in response to the delay amount update, re-judging the relationship between the write address of the SDRAM in the write state and the delay amount.

When the delay amount is updated, the step 111 is shifted to;

and judging the delay relation between the write address of the SDRAM in the write state and the delay amount again every time the delay amount is updated.

Further, the method further comprises the steps of:

in step 115, two pieces of SDRAM alternately store the input data stream in response to the delayed output being turned off.

When the DRFM system starts to work, the delay output is closed, the ping-pong read-write module is IN a pre-storage state, input data flow through the FIFO_IN buffer and then enter the ping-pong read-write engine, two SDRAMs alternately store, do not read output, and the data storage depth is the maximum storage depth of the SDRAMs.

It should be noted that, before the DRFM system starts to operate and after the DRFM system ends to operate, two pieces of SDRAM are needed to alternately store the input data stream.

Further, the output data stream buffer is reset and emptied.

After the work is finished, when the delay is closed, the two SDRAMs alternately store the input data stream, and reset and empty the output data stream buffer FIFO_OUT to wait for the restart of the delay.

FIG. 3 is a block diagram of a deterministic latency system according to an embodiment of the present application.

The embodiment of the application also provides an SDRAM deterministic delay system for realizing the deterministic delay method described in the above embodiment, which comprises an input data stream buffer 1, a ping-pong read-write engine 2, an output data stream buffer 3 and a delay compensation storage 4.

The input data stream buffer is used for matching the data bandwidth between the input data stream and the ping-pong read-write engine and processing the data across clock domains.

The ping-pong read-write engine is used for completing ping-pong read-write of two SDRAM.

The output data stream buffer is used for matching the data bandwidth between the ping-pong read-write engine and the output data stream and processing the data bandwidth across clock domains.

The delay compensation storage is realized in the FPGA and is used for compensating delay drift caused by the depth change of input and output cache data when correcting delay updating and transmitting output data streams.

Fig. 4 is a control flow chart of a deterministic latency system according to an embodiment of the present application.

The embodiment of the application also provides a control flow chart of the deterministic delay system based on SDRAM, which is used for realizing the control of the deterministic delay system described in the above embodiment, and comprises the following steps:

step 410: when the system starts to work, the delay output is closed, the ping-pong read-write module is in a pre-storage state, data flow enters the ping-pong read-write engine after being buffered by an input data flow, two SDRAMs are alternately stored and are not read for output, and the data storage depth is the maximum storage depth of the SDRAMs;

step 420: judging whether the delay is started or not, if so, waiting for the completion of all current read-write states, and turning to step 430; otherwise, continuing with step 410;

step 430: judging the relation between the current writing address of the SDRAM and the delay amount, and if the current writing address is not smaller than the delay amount, preparing the SDRAM to enter a reading operation in a writing state, and preparing the SDRAM to enter the writing operation in a reading state; otherwise, the writing state SDRAM is ready to continue writing operation, and the reading state SDRAM is ready to enter new reading operation;

step 440: according to the current delay amount, the parameters such as read/write states, read/write addresses and the like of the two SDRAM are updated;

step 450: acquiring the data length in the current input data stream buffer and the current output data stream buffer, and calculating and updating the delay amount stored by delay compensation;

step 460: starting a ping-pong read-write mode of the SDRAM, switching the read-write operation of the two SDRAMs when the write operation of the write-state SDRAM is completed and the read operation of the read-state SDRAM is completed, starting a new round of read-write operation, and ensuring the continuity of input and output data;

step 470: when the delay amount is updated, waiting for all current read-write states to be completed, and turning to step 303;

step 480: when the delay is off, go to step 410 and reset and empty the output data stream buffer waiting for the delay to restart.

FIG. 5 is a diagram of a ping-pong read-write engine according to an embodiment of the present application.

Further, as shown in fig. 5, the ping-pong read-write engine includes a master control state machine, an SDRAM write driver, and an SDRAM read driver.

The master control state machine is used for controlling the read-write direction, address management and data scheduling of the SDRAM;

the SDRAM write driver is used for realizing the bottom layer of SDRAM write operation;

the SDRAM read driver is used for realizing the bottom layer of SDRAM read operation.

The basic principle of ping-pong reading and writing is as follows: the memory architecture consists of two groups of SDRAM chips, the memory and the read are simultaneously carried out in the two groups of SDRAM, and when the memory SDRAM is completely written and the read SDRAM chip is empty, the operations of the two groups of SDRAM are seamlessly alternated, so that the continuity of data memory and read is realized as a whole.

The deterministic delay method of the application carries out special judgment on the ping-pong read-write switching moment of the SDRAM, and obtains the data depth of the input cache and the output cache which are used for matching different data bandwidths at the moment on the premise of ensuring the delay certainty of the double SDRAM read/write modules; and compensating and correcting delay drift caused by depth change of input and output cache data by adopting an FPGA (field programmable gate array) internal BRAM (binary synchronous dynamic random access memory), and finally realizing deterministic delay of the DRFM system based on double SDRAM ping-pong reading and writing.

By using the method of the application, the digital radio frequency storage system can accurately acquire the system delay drift caused by uncertainty of SDRAM read-write operation time when the delay amount is updated. The delay drift is reflected on the ping-pong read-write module and is represented by the change of the delay amount of the input and output data cache. And the delay drift is compensated and corrected by adopting the BRAM in the FPGA, so that the delay certainty of the DRFM system based on double SDRAM ping-pong reading and writing is realized.

It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

The application therefore also proposes a computer-readable storage medium, on which a computer program is stored, which program, when being executed by a processor, implements a method according to any of the embodiments of the application.

Furthermore, the application also provides an electronic device, which comprises a memory, a processor and a computer program stored on the memory and capable of being run by the processor, wherein the processor executes the computer program to realize the method according to any embodiment of the application.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

In one typical configuration, a computing device includes one or more processors (CPUs), input/output interfaces, network interfaces, and memory. The memory may include volatile memory in a computer-readable medium, random Access Memory (RAM) and/or nonvolatile memory, such as Read Only Memory (ROM) or flash memory (flash RAM). Memory is an example of computer-readable media.

It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article or apparatus that comprises the element.

The foregoing is merely exemplary of the present application and is not intended to limit the present application. Various modifications and variations of the present application will be apparent to those skilled in the art. Any modification, equivalent replacement, improvement, etc. which come within the spirit and principles of the application are to be included in the scope of the claims of the present application.

Claims (10)

1. The SDRAM deterministic delay method is characterized by comprising the following steps:

responding to the delay updating and the completion of all read-write processes of the current ping-pong operation, and acquiring the data length of the input and output data stream caches;

judging the relation between the writing address of SDRAM in writing state and new delay amount in ping-pong operation, and updating the initial position of a new round of ping-pong operation;

and compensating and correcting delay drift introduced by the depth change of the input and output cache data.

2. The SDRAM deterministic latency method of claim 1 wherein the specific flow of ping-pong operations for both SDRAM's further comprises the steps of:

judging the relation between the write address and the delay amount of the first SDRAM in the write state;

the first SDRAM is ready to enter a read state in response to the write address of the first SDRAM being not less than the delay amount, the second SDRAM is ready to enter a write state, or the first SDRAM is ready to continue the write state in response to the write address of the first SDRAM being less than the delay amount, the second SDRAM is ready to enter the read state;

and updating the states and addresses of the two SDRAM chips according to the current delay amount.

3. The SDRAM deterministic latency method of claim 1, wherein the latency drift is compensated and corrected using an FPGA internal BRAM.

4. The SDRAM deterministic latency method according to claim 1, wherein a buffer data length monitor is provided in the input data stream buffer and the output data stream buffer.

5. The SDRAM deterministic latency method according to claim 2, wherein the relationship of the write address of the SDRAM in the write state and the latency amount is re-judged in response to the latency amount update.

6. The SDRAM deterministic latency method of claim 2 wherein the two SDRAM bits alternately store the input data stream in response to the latency output being off.

7. The deterministic latency method according to claim 6, wherein the output data stream buffer is reset emptied.

8. An SDRAM deterministic delay system for realizing the deterministic delay method as claimed in claim 1, characterized by comprising an input data stream buffer, a ping-pong read-write engine, an output data stream buffer and delay compensation storage;

the input data flow enters a ping-pong read-write engine through an input data flow cache, an output data flow cache and delay compensation storage;

the input data stream buffer is used for matching the data bandwidth between the input data stream and the ping-pong read-write engine and performing cross-clock domain processing;

the ping-pong read-write engine is used for completing ping-pong operation and data stream management;

the output data stream buffer is used for matching the data bandwidth between the ping-pong read-write engine and the output data stream and performing cross-clock domain processing;

the delay compensation storage is used for compensating delay drift introduced by the depth change of the input and output buffer data when correcting delay updating, and transmitting the output data stream.

9. The SDRAM deterministic latency system of claim 2 wherein said ping-pong read-write engine comprises a master state machine, an SDRAM write driver and an SDRAM read driver;

the master control state machine is used for controlling the read-write direction, address management and data scheduling of the SDRAM;

the SDRAM write driver is used for realizing the bottom layer of SDRAM write operation;

the SDRAM read driver is used for realizing the bottom layer of SDRAM read operation.

10. A computer readable storage medium, on which a computer program is stored, characterized in that the program, when being executed by a processor, implements the method according to any one of claims 1-7.