CN116470793A - High-stability control interface of multi-way driving motor - Google Patents
High-stability control interface of multi-way driving motor Download PDFInfo
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- CN116470793A CN116470793A CN202310314806.7A CN202310314806A CN116470793A CN 116470793 A CN116470793 A CN 116470793A CN 202310314806 A CN202310314806 A CN 202310314806A CN 116470793 A CN116470793 A CN 116470793A
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- logic controller
- motor
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- motor control
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- 238000001514 detection method Methods 0.000 claims abstract description 17
- 238000000034 method Methods 0.000 claims description 5
- 230000001934 delay Effects 0.000 claims description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 206010063385 Intellectualisation Diseases 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
- H02P6/00—Arrangements for controlling synchronous motors or other dynamo-electric motors using electronic commutation dependent on the rotor position; Electronic commutators therefor
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0423—Input/output
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Automation & Control Theory (AREA)
- Control Of Motors That Do Not Use Commutators (AREA)
Abstract
The invention discloses a high-stability control interface of a multi-way driving motor. In the invention, the following components are added: the CPU writes data into a special function register in the motor control module through a bus; the motor control module comprises an interrupt control logic controller, a waveform output logic controller and a fault detection logic controller; the waveform output logic controller calculates and outputs PWM waveform signals according to the data written in the special function register; after the triggering event, the interrupt control logic controller outputs a corresponding signal to the ADC module; the fault detection logic controller controls the waveform output logic controller to stop PWM waveform signal output when the fault signal is received. The invention writes data into a register in a motor control module through the CPU, and is used for generating PWM waveforms for driving the motor; the motor control module can monitor the fault detection pins to avoid faults, and is used for collecting motor related information through the ADC module, so that the motor operation can be controlled more accurately.
Description
Technical Field
The invention belongs to the technical field of motor control, and particularly relates to a high-stability multi-drive motor control interface.
Background
With the development of new energy technology, related technologies of motors are also rapidly developing. The control mode of the motor also shows diversified growth, and the control technology of the motor is gradually developed towards intellectualization. The conventional motor driving interface cannot meet the requirement of accurate driving of the motor.
The publication number CN101814878B discloses a direct current brushless motor controller integrating various input signal interface circuits and a control method thereof, and discloses a motor controller which comprises a user control system, a direct current brushless motor controller and a direct current brushless motor, wherein the user control system, the direct current brushless motor controller and the direct current brushless motor are sequentially connected together, the direct current brushless motor controller comprises an input interface circuit, a microprocessor unit and an intelligent power module IPM, control signals of the user control system are input to the microprocessor unit through the input interface circuit, and output signals of the microprocessor unit are input to the direct current brushless motor through the intelligent power module IPM and drive and control the direct current brushless motor to run.
However, it is not mentioned that the CPU is configured to write data into a register in the motor control module for generating a PWM waveform for driving the motor, so that the flexibility of the user in controlling the motor is improved; the motor control module monitors the fault detection pins to avoid faults.
Disclosure of Invention
The invention aims to provide a high-stability multipath driving motor control interface, which is used for generating PWM waveforms of a driving motor by setting a CPU to write data into a register in a motor control module, so that the flexibility of a user in motor control is improved; the motor control module can monitor the fault detection pin to avoid fault generation, and is used for collecting motor related information through the ADC module, so that the motor operation can be controlled more accurately, and faults occurring in the motor operation are avoided.
In order to solve the technical problems, the invention is realized by the following technical scheme:
the invention relates to a high-stability multipath driving motor control interface, which comprises a motor control module; the motor control module is respectively connected with the ADC module and the motor; the motor control module is also connected with the CPU through a bus; the ADC module collects motor operation data and transmits the motor operation data to the CPU; the CPU writes data into a special function register in the motor control module through a bus; the motor control module comprises an interrupt control logic controller, a waveform output logic controller and a fault detection logic controller; the waveform output logic controller calculates and outputs PWM waveform signals according to the data written in the special function register; the interrupt control logic controller judges the waveform signals output by the waveform output logic controller, and outputs corresponding signals to the ADC module after a trigger event; the fault detection logic controller receives a fault signal of the fault detection pin FLTPIN, and controls the waveform output logic controller to stop PWM waveform signal output after receiving the fault signal.
Further, the waveform output logic controller counts by taking the input system clock as a counting clock, compares the current counting with a duty ratio register configured by a user to output a waveform with a corresponding duty ratio, delays by front and back dead time to output a PWM waveform with a dead zone, and outputs the PWM waveform to the motor to control the motor.
Further, the counting modes of the waveform output logic controller are an up-counting mode, a center counting mode and a single counting mode respectively; the waveform output logic controller outputs three or less sets of motor drive waveform signals and six or less paths of motor drive waveform signals according to the register configuration data.
Further, the system clock signal is transmitted to a PWM counter for processing after being processed by a pre-allocation counting logic controller; the PWM controller divides the signals into a plurality of paths for output, one path of the signals is transmitted to the post frequency division counter for processing after being compared in period, and the other path of the signals is respectively output to the duty ratio comparator and the PWM waveform generator for processing and is transmitted to the output control logic controller through the dead zone and the polarity control logic controller.
Further, the post frequency division counter processes the received signal and outputs the processed signal to the interrupt controller and the ADC trigger; the interrupt controller and the ADC trigger also receive signals of a PWM waveform generator; the interrupt controller is used for outputting an interrupt signal PWMINT; the ADC trigger outputs an ADC trigger signal ADCTRI.
Further, the post frequency division counter receives the period matching interrupt signal and the return-to-zero matching interrupt signal, and then outputs an interrupt signal to the ADC module through the interrupt controller.
The invention has the following beneficial effects:
according to the invention, the CPU is set to write data into the register in the motor control module for generating the PWM waveform of the driving motor, so that the flexibility of the motor control by a user is improved; the motor control module can monitor the fault detection pin to avoid fault generation, and is used for collecting motor related information through the ADC module, so that the motor operation can be controlled more accurately, and faults occurring in the motor operation are avoided.
Of course, it is not necessary for any one product to practice the invention to achieve all of the advantages set forth above at the same time.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a system block diagram of a high stability multiple drive motor control interface;
fig. 2 is a logic block diagram of a high-stability multiplex drive motor control interface.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Referring to fig. 1, the present invention is a high-stability multi-path driving motor control interface, which includes a motor control module; the motor control module is respectively connected with the ADC module and the motor; the motor control module is also connected with the CPU through a bus; the ADC module collects motor operation data and transmits the motor operation data to the CPU;
the CPU writes data into a special function register in the motor control module through a bus; the internal special function register must be written in through a specific time sequence, and the data in the register cannot be directly written in to change the data, so that the stability of motor driving is greatly improved. The special function register with BUFFER can not directly change the output of the PWM waveform, and the current counting period can not be loaded until the period matching interrupt or the zero resetting matching interrupt is generated, but the selection of the event can also be configured by the corresponding register.
The motor control module comprises an interrupt control logic controller, a waveform output logic controller and a fault detection logic controller; the waveform output logic controller calculates and outputs PWM waveform signals according to the data written in the special function register; the counting modes of the waveform output logic controller are an up-counting mode, a center counting mode and a single counting mode respectively; the waveform output logic controller outputs three or less groups of motor driving waveform signals and six or less paths of motor driving waveform signals according to the register configuration data; the interrupt control logic controller judges the waveform signal output by the waveform output logic controller, and outputs a corresponding signal to the ADC module after the trigger event; the interrupt control logic controller supports cycle matched interrupts and return to zero matched interrupts on waveform counts and also supports edge triggered interrupts on each waveform output. And the motor is directly connected with the ADC module, so that the current motor operation information can be read better, and the motor operation accuracy is improved.
The fault detection logic controller receives a fault signal of the fault detection pin FLTPIN, and controls the waveform output logic controller to stop PWM waveform signal output after receiving the fault signal; the fault detection logic controller comprises a plurality of trigger levels, filtering time and detection modes, and a user can configure corresponding registers according to specific requirements, so that the safety of motor driving is greatly improved.
As shown in fig. 2, the waveform output logic controller counts with the input system clock as a count clock, compares the current count with a duty ratio register configured by a user to output a waveform of a corresponding duty ratio, delays by a front dead time and a rear dead time to output a PWM waveform with a dead time, and outputs the PWM waveform to the motor to control the motor.
The system clock signal is transmitted to the PWM counter for processing after being processed by the pre-allocation counting logic controller; the PWM controller divides the signals into a plurality of paths for output, one path of the signals is transmitted to the post frequency division counter for processing after being subjected to period comparison, and the other path of the signals is respectively output to the duty ratio comparator and the PWM waveform generator for processing and is transmitted to the output control logic controller through the dead zone and the polarity control logic controller.
The post frequency division counter processes the received signal and outputs the processed signal to the interrupt controller and the ADC trigger; the interrupt controller and the ADC trigger also receive signals of the PWM waveform generator; the interrupt controller is used for outputting an interrupt signal PWMINT; the ADC trigger outputs an ADC trigger signal ADCTRI, and the post-frequency division counter receives the period matching interrupt signal and the return-to-zero matching interrupt signal and then outputs the interrupt signal to the ADC module through the interrupt controller.
It should be noted that, in the above system embodiment, each unit included is only divided according to the functional logic, but not limited to the above division, so long as the corresponding function can be implemented; in addition, the specific names of the functional units are also only for distinguishing from each other, and are not used to limit the protection scope of the present invention.
In addition, it will be understood by those skilled in the art that all or part of the steps in implementing the methods of the embodiments described above may be implemented by a program to instruct related hardware, and the corresponding program may be stored in a computer readable storage medium, such as a ROM/RAM, a magnetic disk or an optical disk, etc.
The preferred embodiments of the invention disclosed above are intended only to assist in the explanation of the invention. The preferred embodiments are not exhaustive or to limit the invention to the precise form disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best understand and utilize the invention. The invention is limited only by the claims and the full scope and equivalents thereof.
Claims (6)
1. The multipath driving motor control interface with high stability is characterized by comprising a motor control module; the motor control module is respectively connected with the ADC module and the motor; the motor control module is also connected with the CPU through a bus; the ADC module collects motor operation data and transmits the motor operation data to the CPU;
the CPU writes data into a special function register in the motor control module through a bus;
the motor control module comprises an interrupt control logic controller, a waveform output logic controller and a fault detection logic controller;
the waveform output logic controller calculates and outputs PWM waveform signals according to the data written in the special function register;
the interrupt control logic controller judges the waveform signals output by the waveform output logic controller, and outputs corresponding signals to the ADC module after a trigger event;
the fault detection logic controller receives a fault signal of the fault detection pin FLTPIN, and controls the waveform output logic controller to stop PWM waveform signal output after receiving the fault signal.
2. The high-stability multi-drive motor control interface of claim 1, wherein the waveform output logic controller counts with an input system clock as a count clock, compares the current count with a duty ratio register configured by a user to output a waveform of a corresponding duty ratio, and delays by a front dead time and a rear dead time to output a PWM waveform with a dead time to the motor to control the motor.
3. The high-stability multi-drive motor control interface of claim 1, wherein the waveform output logic controller has a count mode of up-count mode, a center count mode, and a single count mode, respectively; the waveform output logic controller outputs three or less sets of motor drive waveform signals and six or less paths of motor drive waveform signals according to the register configuration data.
4. The high-stability multi-drive motor control interface of claim 2, wherein the system clock signal is processed by the pre-allocation count logic controller and then transmitted to the PWM counter for processing;
the PWM controller divides the signals into a plurality of paths for output, one path of the signals is transmitted to the post frequency division counter for processing after being compared in period, and the other path of the signals is respectively output to the duty ratio comparator and the PWM waveform generator for processing and is transmitted to the output control logic controller through the dead zone and the polarity control logic controller.
5. The high stability multiple drive motor control interface of claim 4, wherein the post-divide counter processes the received signal and outputs it to the interrupt controller and ADC flip-flop;
the interrupt controller and the ADC trigger also receive signals of a PWM waveform generator;
the interrupt controller is used for outputting an interrupt signal PWMINT; the ADC trigger outputs an ADC trigger signal ADCTRI.
6. The high stability multiple drive motor control interface of claim 5, wherein the post-divide counter receives the period match interrupt signal and the zero-reset match interrupt signal and the post-output signal outputs the interrupt signal to the ADC module via the interrupt controller.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310314806.7A CN116470793A (en) | 2023-03-29 | 2023-03-29 | High-stability control interface of multi-way driving motor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310314806.7A CN116470793A (en) | 2023-03-29 | 2023-03-29 | High-stability control interface of multi-way driving motor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116470793A true CN116470793A (en) | 2023-07-21 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310314806.7A Pending CN116470793A (en) | 2023-03-29 | 2023-03-29 | High-stability control interface of multi-way driving motor |
Country Status (1)
| Country | Link |
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| CN (1) | CN116470793A (en) |
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2023
- 2023-03-29 CN CN202310314806.7A patent/CN116470793A/en active Pending
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