CN115144740A - Power-on latch circuit, power-on latch device and power-on latch method - Google Patents

Power-on latch circuit, power-on latch device and power-on latch method Download PDF

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Publication number
CN115144740A
CN115144740A CN202210745094.XA CN202210745094A CN115144740A CN 115144740 A CN115144740 A CN 115144740A CN 202210745094 A CN202210745094 A CN 202210745094A CN 115144740 A CN115144740 A CN 115144740A
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signal
latch
module
unit
reset
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不公告发明人
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Chengdu Aich Technology Co Ltd
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Chengdu Aich Technology Co Ltd
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Priority to CN202210745094.XA priority Critical patent/CN115144740A/en
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31704—Design for test; Design verification
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318541—Scan latches or cell details
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318583—Design for test
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/24—Resetting means
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

The invention discloses a power-on latch circuit, a power-on latch device and a power-on latch method, which relate to the technical field of digital circuits and are used for latching input signals of a target chip pin unit and reducing occupation of chip pins. The power-on latch circuit comprises a reset control unit, a latch control unit and a signal registering unit. The output end of the reset control unit is electrically connected with the input end of the latch control unit, the output end of the latch control unit is electrically connected with the enable end of the signal registering unit, the target chip pin unit is electrically connected with the data input end of the signal registering unit, and the output end of the signal registering unit is electrically connected with the external test mode signal end. The power-on latch device comprises the power-on latch circuit provided by the technical scheme. The power-on latch circuit, the power-on latch device and the power-on latch method provided by the invention are applied to a digital circuit.

Description

Power-on latch circuit, power-on latch device and power-on latch method
Technical Field
The invention relates to the field of digital circuits, in particular to a power-on latch circuit, a power-on latch device and a power-on latch method.
Background
At present, with the high-speed development of integrated circuits, the chip integration degree is higher and higher, which leads to the logic scale and the working mode being more and more complex, and the Design for test based on chip level is more and more important.
In existing DFT test schemes, it is often necessary to provide a dedicated chip pin for providing the signal level of the test mode to control whether the chip is in DFT mode or in functional mode. When the signal level input signal of the chip pin is a signal '1', the chip is in a DFT mode and can be subjected to DFT test; when the signal level input signal of the chip pin is a signal '0', the chip is in a functional mode, and the chip can work normally. However, after the chip is packaged and delivered from a factory, the chip does not need to be switched to a DFT mode to test the chip, and the chip pin can only be used as an idle pin to be connected with a signal "0". In the case where the chip pins are limited, this results in a loss of chip pin resources.
Disclosure of Invention
The invention aims to provide a power-on latch circuit, a power-on latch device and a power-on latch method, which are used for latching an input signal of a target chip pin unit so as to avoid the loss of chip pin resources.
In a first aspect, the present invention provides a power-on latch circuit for latching an input signal of a target chip pin unit, including a reset control unit, a latch control unit, and a signal register unit. The output end of the reset control unit is electrically connected with the input end of the latch control unit, the output end of the latch control unit is electrically connected with the enable end of the signal registering unit, the target chip pin unit is electrically connected with the data input end of the signal registering unit, and the output end of the signal registering unit is electrically connected with the external test mode signal end.
In the latch period, the reset control unit is used for providing a latch starting signal for the latch control unit, and the latch control unit is used for generating a latch control signal under the action of the latch starting signal and sending the latch control signal to the signal registering unit; the signal registering unit is used for latching the input signal of the target chip pin unit according to the latching control signal and transmitting the latched input signal to an external test mode signal end.
After the latch period, the latch control unit is also used for generating a latch stop signal and sending the latch stop signal to the signal registering unit; the signal registering unit is used for stopping latching the input signal of the target chip pin unit according to the latching stopping signal.
Compared with the prior art, in the power-on latch circuit provided by the invention, the output end of the reset control unit is electrically connected with the input end of the latch control unit, the output end of the latch control unit is electrically connected with the enable end of the signal registering unit, the target chip pin unit is electrically connected with the data input end of the signal registering unit, and the output end of the signal registering unit is electrically connected with the external test mode signal end. Based on this, in the latch period, the reset control unit supplies a latch enable signal to the latch control unit, and the latch control unit can generate a latch control signal according to the latch enable signal and send the latch control signal to the signal register unit. The signal registering unit can latch the input signal of the target chip pin unit according to the latch control signal, and finally transmit the latched input signal to an external test mode signal end. When the latched input signal is signal "1", the signal received by the external test mode signal terminal is also signal "1", and finally signal "1" may be output to control the chip to be in the DFT test mode. When the latched input signal is a signal "0", the signal received by the external test mode signal terminal is also a signal "0", and finally the signal "0" can be output to control the chip to be in the functional mode. After the latch period, the latch control unit can generate a latch stop signal and send the latch stop signal to the signal register unit to stop latching the input signal of the latch target chip pin unit, so that the input signal jump of the target chip pin unit does not affect the signal received by the external test mode signal end, that is, the working mode of the chip is not changed no matter how the input signal of the target chip pin unit changes. Therefore, the target chip pin unit can be used as other chip functional pins, and can also provide signals to an external test mode signal end through the power-on latch circuit provided by the invention to complete the switching of the chip working mode.
In a second aspect, the present invention further provides a power-on latch device, including the power-on latch circuit of the first aspect.
Compared with the prior art, the beneficial effects of the power-on latch device provided by the invention are the same as those of the power-on latch circuit in the technical scheme, and are not repeated here.
In a third aspect, the present invention further provides a power-on latch method, which is applied to the power-on latch circuit in the first aspect, and the power-on latch method includes:
in the latch period, controlling the reset control unit to provide a latch starting signal to the latch control unit;
in response to a latch enable signal, the latch control unit provides a latch control signal to the signal registering unit;
in response to the latch control signal, the signal registering unit latches an input signal of the target chip pin unit and transmits the latched input signal to an external test mode signal end;
after the latch period, the latch control unit provides a latch stop signal to the signal registering unit;
in response to the latch stop signal, the signal registering unit stops latching the input signal of the target chip pin unit.
Compared with the prior art, the beneficial effects of the power-on latch method provided by the invention are the same as those of the power-on latch circuit in the technical scheme, and the details are not repeated here.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and not to limit the invention. In the drawings:
fig. 1 is a power-on latch circuit provided in an embodiment of the present invention;
fig. 2 is a timing diagram of the power-on latch circuit provided in the embodiment of the present invention.
Reference numerals:
1-a reset control unit, 11-a power-on reset module,
12-a reset synchronization module, 13-a filtering module,
2-latch control unit, 21-count register module,
211-a counter, 212-a second register,
22-clock module, 221-clock signal terminal,
222-a clock gater, 3-a signal register unit,
31-a third register, 32-a fourth register,
4-target chip pin cell.
Detailed Description
In order to facilitate clear description of technical solutions of the embodiments of the present invention, in the embodiments of the present invention, terms such as "first" and "second" are used to distinguish the same items or similar items having substantially the same functions and actions. For example, the first threshold and the second threshold are only used for distinguishing different thresholds, and the sequence order of the thresholds is not limited. Those skilled in the art will appreciate that the terms "first," "second," etc. do not denote any order or quantity, nor do the terms "first," "second," etc. denote any order or importance.
It is to be understood that the terms "exemplary" or "such as" are used herein to mean serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary" or "e.g.," is not necessarily to be construed as preferred or advantageous over other embodiments or designs. Rather, use of the word "exemplary" or "such as" is intended to present concepts related in a concrete fashion.
In the present invention, "at least one" means one or more, "a plurality" means two or more. "and/or" describes the association relationship of the associated object, indicating that there may be three relationships, for example, a and/or B, which may indicate: a exists alone, A and B exist simultaneously, and B exists alone, wherein A and B can be singular or plural. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship. "at least one of the following" or similar expressions refer to any combination of these items, including any combination of the singular or plural items. For example, at least one (one) of a, b, or c, may represent: a, b, c, a and b combination, a and c combination, b and c combination, or a, b and c combination, wherein a, b and c can be single or multiple.
As shown in fig. 1, the embodiment of the present invention provides a power-on latch circuit for latching an input signal of a target chip pin unit 4, which includes a reset control unit 1, a latch control unit 2, and a signal register unit 3.
The output end of the reset control unit 1 is electrically connected with the input end of the latch control unit 2, the output end of the latch control unit 2 is electrically connected with the enable end E of the signal registering unit 3, the target chip pin unit 4 is electrically connected with the data input end D of the signal registering unit 3, and the output end of the signal registering unit 3 is electrically connected with the external test mode signal end TM.
In the latch period, the reset control unit 1 is configured to provide a latch start signal to the latch control unit 2, and the latch control unit 2 is configured to generate a latch control signal under the action of the latch start signal and send the latch control signal to the signal registering unit 3; the signal register unit 3 is configured to latch an input signal of the target chip pin unit 4 according to the latch control signal, and transmit the latched input signal to the external test mode signal terminal TM.
After the latch period, the latch control unit 2 is further configured to generate a latch stop signal and send the latch stop signal to the signal registering unit 3; the signal registering unit 3 is configured to stop latching the input signal of the target chip pin unit 4 according to the latch stop signal.
In the specific implementation: when the input signal of the target chip pin unit 4 needs to be latched, the reset control unit 1 is controlled to generate a latch start signal and send the latch start signal to the latch control unit 2, and the latch control unit 2 is started under the action of the latch start signal. After being started, the latch control unit 2 generates a latch control signal and sends the latch control signal to the signal registering unit 3, and the signal registering unit 3 latches the input signal of the target chip pin unit 4 under the action of the latch control signal, that is, the input signal of the target chip pin unit 4 is stored in the signal registering unit 3 and then provided to the external test mode signal end TM by the signal registering unit 3. When the latched input signal is signal "1", the signal received by the external test mode signal terminal TM is also signal "1", and finally signal "1" may be output, so as to control the chip to be in the DFT test mode. When the latched input signal is a signal "0", the signal received by the external test mode signal terminal TM is also a signal "0", and finally, the signal "0" may be output, so that the control chip is in the functional mode. After the latch is finished, the latch control unit 2 generates a latch stop signal and sends the latch stop signal to the signal register unit 3, and the signal register unit 3 stops latching the input signal of the target chip pin unit 4 under the action of the latch stop signal, that is, the input signal is not stored by the chip register unit and does not affect the output signal of the external test mode signal terminal TM no matter how the input signal of the target chip pin unit 4 changes.
The circuit structure and the specific implementation process of the power-on latch circuit can be known as follows: in the power-on latch circuit provided by the embodiment of the invention, the output end of the reset control unit 1 is electrically connected with the input end of the latch control unit 2, the output end of the latch control unit 2 is electrically connected with the enable end E of the signal registering unit 3, the target chip pin unit 4 is electrically connected with the data input end D of the signal registering unit 3, and the output end of the signal registering unit 3 is electrically connected with the external test mode signal end TM. Based on this, in the latch period, the reset control unit 1 supplies the latch start signal to the latch control unit 2, and the latch control unit 2 can generate the latch control signal according to the latch start signal and send the latch control signal to the signal register unit 3. The signal registering unit 3 can latch the input signal of the target chip pin unit 4 according to the latch control signal, and finally transmit the latched input signal to the external test mode signal terminal TM. When the latched input signal is signal "1", the signal received by the external test mode signal terminal TM is also signal "1", and finally signal "1" may be output to control the chip to be in the DFT test mode. When the latched input signal is signal "0", the signal received by the external test mode signal terminal TM is also signal "0", and finally signal "0" may be output to control the chip to be in the functional mode. After the latch period, the latch control unit 2 can generate a latch stop signal and send the latch stop signal to the signal register unit 3 to stop latching the input signal of the latch target chip pin unit 4, so that the input signal transition of the target chip pin unit 4 does not affect the signal received by the external test mode signal terminal TM, that is, the operation mode of the chip is not changed no matter how the input signal of the target chip pin unit 4 changes. Therefore, the target chip pin unit 4 can be used as other chip functional pins, and can also provide a signal to the external test mode signal end TM through the power-on latch circuit provided in the embodiment of the present invention to complete switching of the chip operating mode.
In practice, the target chip PIN unit 4 includes a chip PIN0, and a silicon chip PIN PAD0 electrically connected to the chip PIN 0. The silicon chip pin PAD0 is provided with three input and output ends including a PAD end, a C end and an I end, and also provided with an output enable OEN end which is used for controlling the silicon chip pin to be in an output mode or an input mode. When the output enable OEN end is electrically connected with the signal '1', the silicon chip pin PAD0 is in an input mode, namely, an input signal is received from a PAD end, and a signal is output from a C end; when the output enable OEN terminal is electrically connected with the signal '0', the silicon chip pin PAD0 is in an output mode, namely, a signal is received from the I terminal, and a signal is output from the PAD terminal. In the embodiment of the invention, when the chip PIN0 is electrically connected with the PAD end of the silicon chip PIN PAD0, the output enable OEN end needs to be electrically connected with the signal "1" so as to transmit an input signal received by the chip PIN0 to the data input end D of the signal registering unit 3 through the C end of the silicon chip PIN PAD 0; when the chip PIN0 is electrically connected to the I terminal of the silicon chip PIN PAD0, the output enable OEN terminal needs to be electrically connected to the signal "0" so as to transmit the input signal received by the chip PIN0 to the data input terminal D of the signal registering unit 3 through the PAD terminal of the silicon chip PIN PAD0.
In one possible implementation, the reset control unit 1 includes a power-on reset module 11 and a reset synchronization module 12. The output end of the power-on reset module 11 is electrically connected to the data input end D of the reset synchronization module 12, and is configured to provide a power-on reset signal to the reset synchronization module 12, the output end of the reset synchronization module 12 is electrically connected to the input end of the latch control unit 2, the reset end of the latch control unit 2, and the reset end of the signal registering unit 3, and is configured to provide a latch start signal to the input end of the latch control unit 2, the reset end of the latch control unit 2, and the reset end of the signal registering unit 3 according to the power-on reset signal, where the latch start signal is used to control the latch control unit 2 to start, and control the latch control unit 2 and the signal registering unit 3 to stop resetting.
In specific implementation, when an input signal of the target chip pin unit 4 needs to be latched, the power-on reset module 11 is first controlled to be powered on, in the process of powering on the power-on reset module 11, the output signal is "0", after the reset synchronization module 12 receives the signal "0", the signal "0" is transmitted to the input end of the latch control unit 2, the reset end of the latch control unit 2 and the reset end of the signal registering unit 3, and since the reset ends are generally active at a low level, when the signal "0" is received, the latch control unit 2 and the signal registering unit 3 always maintain a reset state under the action of the low-level signal "0". When the power-on reset module 11 is powered on, the output signal jumps to signal "1" after a delay of millisecond level, and at this time, the signal "1" is the power-on reset signal generated by the power-on reset module 11. The reset synchronization module 12 provides a latch start signal to the input terminal of the latch control unit 2, the reset terminal of the latch control unit 2, and the reset terminal of the signal registering unit 3 according to the received signal "1", at this time, the latch start signal is the signal "1", after receiving the high level signal "1", the latch control unit 2 and the signal registering unit 3 stop resetting, and the latch control unit 2 starts under the action of the signal "1".
Based on this, when the input signal of the target chip pin unit 4 needs to be latched, the power-on reset module 11 is controlled to be powered on, and then the latch signal circuit is controlled to be in the latch period through the signal "1" generated after the power-on reset module 11 is powered on. For example, when the input signal of the target chip pin unit 4 is a signal "0", if the signal "0" needs to be latched at this time, the power-on reset module 11 needs to be controlled to be powered on.
It is understood that the signal registering unit 3 can latch only the input signal of the target chip pin unit 4 during a latch period. After the last latch period is finished, if the input signal of the current target chip pin unit 4 needs to be latched, the power-on reset module 11 needs to be controlled to be powered on again to control the latch signal circuit to enter another round of latch period.
In some embodiments, as shown in fig. 1, the reset control unit 1 further includes a filtering module 13, a data input terminal of the filtering module 13 is electrically connected to an output terminal of the power-on reset module 11, an output terminal of the filtering module 13 is electrically connected to a data input terminal of the reset synchronization module 12, and the filtering module 13 is configured to filter the power-on reset signal and transmit the filtered power-on reset signal to the reset synchronization module 12.
It should be understood that, during the power-on process, the output jitter of the power supply may directly affect the power-on reset signal output by the power-on reset module 11, so that the power-on reset signal generates an unnecessary transition, which in turn causes a transition of the latch enable signal, for example, when the latch enable signal is a signal "1", if the transition is a signal "0", the latch signal control unit and the signal registering unit 3 are reset, which causes latch confusion. Based on this, the filtering module 13 may filter the output signal of the power-on reset module 11, and filter the glitch in the power-on reset signal, so that the power-on reset signal can always keep stable output of the signal "1". In practice, in order to avoid a circuit abnormality of the power-on latch circuit caused by a timing problem or a metastable state problem, the reset synchronization module 12 needs to delay several clock cycles after receiving the power-on reset signal passing through the filtering module 13, and then synchronously outputs the latch start signal, where the number of the delayed cycles is related to the frequency of the clock signal in practical application, which is not limited in the embodiment of the present invention.
In one embodiment, as shown in fig. 1, the filtering module 13 includes a plurality of first registers and an or gate. A plurality of first registers are connected in series, and the output terminal of each first register is further electrically connected to a corresponding input terminal of the or gate, and the output terminal of the or gate is electrically connected to the input terminal of the reset synchronization module 12.
For example, as shown in fig. 1, the filtering module 13 may include 3 first registers, where the 3 first registers are sequentially connected end to end, and output terminals of the 3 first registers are all electrically connected to input terminals of the or gate. When the power-on reset module 11 is powered on, the output signal thereof becomes signal "1", and at this time, the signal "1" is the power-on reset signal generated by the power-on reset module 11. After receiving the signal "1", the 1 st first register transmits the signal "1" to the 2 nd first register, and simultaneously transmits the signal "1" to the first input end of the or gate, after receiving the signal "1", the 2 nd first register transmits the signal "1" to the 3 rd first register, and simultaneously transmits the signal "1" to the second input end of the or gate, after receiving the signal "1", the 3 rd first register transmits the signal "1" to the third input end of the or gate, and after receiving the signal "1" at one of the input ends of the or gate, the signal "1" is transmitted to the reset synchronization module 12. If in the process of outputting the signal "1" by the power-on reset module 11, the signal jumps due to the existence of the glitch, so that the signal "0" is received by the 1 st first register, and since the register only collects the signal of the data input end D to the output end when the rising edge of the clock signal arrives, at this time, the signal sent by the 2 nd first register to the 3 rd first register is also the signal "1", and the signal sent by the 2 nd first register to the or gate is also the signal "1", so that the or gate can continue to output the signal "1". Based on this, the filter circuit can filter the low-level glitch in the power-on reset signal, so that the reset synchronization module 12 can receive the stable power-on reset signal. It is understood that the filtering module 13 may further include 2, 4, or 5 first registers, which is not specifically limited in this embodiment of the present invention.
In one possible implementation, as shown in fig. 1, the latch control unit 2 includes a count register module 21 and a clock module 22. The input end of the counting register module 21 is electrically connected with the output end of the reset control unit 1, and is used for starting counting under the control of the latch start signal. The reset end of the counting register module 21 is electrically connected with the output end of the reset control unit 1, and is used for stopping resetting under the action of the latch start signal.
The first output end of the counting and registering module 21 is electrically connected to the enable end E of the clock module 22 and is used for controlling the clock module 22 to be opened, the first output end of the clock module 22 is electrically connected to the counting end of the counting and registering module 21, and the counting and registering module 21 is used for counting the output signal of the clock module 22; the counting and registering module 21 is further configured to control the clock module 22 to turn off when the counting value of the counting and registering module 21 reaches the target value.
The second output end of the counting and registering module 21 is electrically connected to the enable end E of the signal registering unit 3, and is configured to generate a latch control signal when the counting value of the counting and registering module 21 reaches a target value, where the latch control signal is used to control the signal registering unit 3 to latch an input signal of the target chip pin unit 4.
After the latch period, the count register block 21 is further configured to generate a latch stop signal, where the latch stop signal is used to control the signal register unit 3 to stop latching the input signal of the target chip pin unit 4.
A second output end of the clock module 22 is electrically connected to the clock input end of the reset control unit 1, the clock input end of the counting and registering module 21, and the clock input end of the signal registering unit 3, respectively, and is configured to provide clock signals to the reset control unit 1, the counting and registering module 21, and the signal registering unit 3.
In specific implementation, the counting register module 21 starts counting after receiving the signal "1" sent by the reset synchronization module 12, and stops resetting under the action of the signal "1". At this time, after the counting and registering module 21 stops resetting, the first output end of the counting and registering module 21 outputs a signal "1", the enable end E of the clock module 22 receives the signal "1", the clock module 22 is turned on and outputs the signal to the counting end of the counting and registering module 21, the counting and registering module 21 counts the output signal of the clock module 22, when the counting value of the counting and registering module 21 reaches the target value, that is, when the counting and registering module 21 is full of counting, the first output end of the counting and registering module 21 outputs a signal "0", and the enable end E of the clock module 22 receives the signal "0", the clock module 22 is turned off. Meanwhile, after the counting and registering module 21 is started and before the counting and registering module 21 counts fully, the second output end of the counting and registering module 21 outputs a signal "0" to the enable end E of the signal registering unit 3, and when the enable end E of the signal registering unit 3 receives the signal "0", the signal received by the data input end D is not stored. After the count register module 21 counts completely, the second output end of the count register module 21 outputs a signal "1" to the enable end E of the signal register unit 3, and the enable end E of the signal register unit 3 stores the signal received by the data input end D after receiving the signal "1".
After the input signal of the target pin cell is stored in the signal register unit 3, the latch period is over, and the second output terminal of the count register module 21 outputs a signal "0" to the enable terminal E of the signal register unit 3 to stop latching the input signal of the target chip pin cell 4. After the latch period, the signal registering unit 3 will not register the input signal of the target chip pin unit 4, and at this time, no matter how the input signal of the target chip pin unit 4 changes, the output signal of the signal registering unit 3 will not be affected.
In some embodiments, as shown in fig. 1, the count register module 21 includes a counter 211 and a second register 212. The input end and the reset end of the counter 211 are electrically connected to the output end of the reset control unit 1, the first output end Q1 of the counter 211 is electrically connected to the enable end E of the clock module 22, the first output end Q of the clock module 22 is electrically connected to the counting end of the counter 211, and the counter 211 is configured to control the clock module 22 to be turned on and count the output signal of the clock module 22 under the control of the latch start signal.
The second output terminal Q2 of the counter 211 is electrically connected to the data input terminal of the second register 212, the output terminal of the second register 212 is electrically connected to the enable terminal E of the signal registering unit 3, and the second register 212 is configured to transmit the latch control signal or the latch stop signal generated by the counter 211 to the enable terminal E of the signal registering unit 3.
The second output of the clock module 22 is also electrically connected to a clock input of the second register 212 for providing a clock signal to the second register 212.
In a specific implementation, after receiving the signal "1" sent by the reset synchronization module 12, the counter 211 starts counting, and the counter 211 and the second register 212 stop resetting under the action of the signal "1". At this time, after the counter 211 stops resetting, the first output end Q1 of the counter 211 outputs the signal "1", the enable end E of the clock module 22 receives the signal "1", the clock module 22 is turned on and outputs the signal to the counting end of the counter 211, the counter 211 counts the output signal of the clock module 22, when the counting number of the counter 211 reaches the target number, that is, the counter 211 is full, the first output end Q1 of the counter 211 outputs the signal "0", and the enable end E of the clock module 22 receives the signal "0", the clock module 22 is turned off. Meanwhile, after the counter 211 is started and before the counter 211 counts fully, the second output terminal Q2 of the counter 211 outputs a signal "0" to the second register 212, and when the rising edge of the clock signal arrives, the second register 212 transmits the signal "0" to the enable terminal E of the signal registering unit 3, and at this time, the signal registering unit 3 does not store the signal received by the data input terminal D. After the counter 211 counts fully, the second output terminal of the counter 211 outputs a signal "1" to the second register 212, the second register 212 transmits the signal "1" to the enable terminal E of the signal registering unit 3 when the rising edge of the clock signal arrives, and the enable terminal E of the signal registering unit 3 stores the signal received by the data input terminal after receiving the signal "1".
In some embodiments, as shown in FIG. 1, clock module 22 includes a clock gater 222 and a clock signal terminal 221. The clock signal terminal 221 is electrically connected to the clock input terminal of the reset control unit 1, the clock input terminal of the counting register module 21, the clock input terminal of the signal register unit 3, and the clock input terminal CP of the clock gater 222, respectively, and is configured to provide a clock signal to the reset control unit 1, the counting register module 21, the signal register unit 3, and the clock gater 222.
The enable terminal E of the clock gater 222 is electrically connected to the first output terminal of the counting register module 21, and the output terminal of the clock gater 222 is electrically connected to the counting terminal of the counting register module 21.
In specific implementation, when the enable terminal E of the clock gater 222 receives the signal "1" output by the counter 211, the clock gater 222 is turned on, the clock signal terminal 221 provides a clock signal to the counter 211 through the clock gater 222, and the counter 211 counts the clock signal, for example, the period of 1 clock signal is 1, and the period of 2 clock signals is 2, so that after the counter 211 is full, the counter 211 outputs the signal "0" to the enable terminal E of the clock gater to control the clock gater 222 to be turned off, thereby stopping counting by the counter 211.
In practical applications, the clock signal terminal 221 is used to provide clock signals to the reset control unit 1, the count register module 21, the signal register unit 3, and the clock gater 222, and the same clock signal terminal 221 is used to provide clock signals, so that the timing disorder of the latch circuit can be avoided to the greatest extent. The clock signal provided by the clock signal terminal 221 may be generated using a crystal clock.
In one possible implementation, as shown in fig. 1, the signal registering unit 3 includes a third register 31 and a fourth register 32. The output end of the latch control unit 2 is electrically connected to the enable end E of the third register 31, the data input end D of the third register 31 is electrically connected to the target chip pin unit 4, and the output end of the third register 31 is electrically connected to the data input end D of the fourth register 32. An output terminal of the fourth register 32 is electrically connected to the external test mode signal terminal TM.
Specifically, when the enable terminal E of the third register 31 receives the signal "0", the third register 31 is in the disable state, and at this time, the third register 31 does not transmit the signal received by the data input terminal D to the output terminal Q regardless of whether the rising edge of the clock signal arrives. When the enable terminal E of the third register 31 receives the signal "1", the third register 31 is in an enable state, at this time, when the rising edge of the clock signal arrives, the third register 31 transmits the signal received by the data input terminal D to the output terminal Q, and after the fourth register 32 receives the signal, when the rising edge of the next clock cycle arrives, the acquired signal is transmitted to the output terminal Q, and then the signal is provided to the external test mode signal terminal TM.
It should be noted that the first register, the second register 212, the third register 31, and the fourth register 32 in the above embodiments may be rising edge registers, that is, only when a rising edge of a clock signal arrives, a signal of the data input end D can be transmitted to the output end Q, or the first register, the second register 212, the third register 31, and the fourth register 32 in the above embodiments may also be falling edge registers, that is, only when a falling edge of a clock signal arrives, a signal of the data input end D can be transmitted to the output end Q, and thus, the embodiment of the present invention is not limited in particular.
The working principle of the power-on latch circuit provided by the embodiment of the present invention will be described in detail below with reference to fig. 1 and 2, taking the example that the input signal of the target chip pin unit 4 is signal "1", and the following description is only for explanation and not for limitation.
The power-on reset module 11 is first controlled to power on the chip, and the clock signal terminal 221 provides a clock signal.
In the power-on process, the power-on reset module 11 outputs a signal "0"; the output signals of the first registers in the filtering module 13 and the reset synchronization module 12 are both signals "0"; the counting end and the reset end of the counter 211 simultaneously receive the signal "0", the reset end of the counter 211 is enabled and is in a reset state, the first output end Q1 of the counter 211 outputs the signal "1" by default, the second output end Q2 outputs the signal "0" by default, the reset end of the second register 212, the reset end of the third register 31 and the reset end of the fourth register 32 receive the signal "0", the reset end is enabled, the second register 212, the third register 31 and the fourth register 32 are all in a reset state and output as the signal "0", and the external test mode signal end TM also receives the signal "0".
After the power-on is completed, the output signal of the power-on reset module 11 is changed from the signal "0" to the signal "1", the output signal of the filtering module 13 is changed from the signal "0" to the signal "1", the output signal of the reset synchronization module 12 is changed from the signal "0" to the signal "1", and finally, the signals received by the counting terminal and the reset terminal of the counter 211, the reset terminal of the second register 212, the reset terminal of the third register 31, and the reset terminal of the fourth register 32 are all changed from the signal "0" to the signal "1", at this time, the chip is in a non-reset state, and the counter 211 starts to count. The first output Q1 of the counter 211 and the second output Q2 of the counter 211 are still in the initial state, i.e.: q1=1, q2=0, the gating of the clock gater 222 is still open, and the signal received by the enable terminal E of the third register 31 is still the signal "0" and is in the disable state.
When the counter 211 counts up to the current clock cycle, the first output terminal Q1=1 of the counter 211 and the second output terminal Q2=1 of the counter 211, the input terminal of the second register 212 starts to change to the signal "1".
When the counter 211 is full in the 2 nd clock cycle, the first output Q1=0 of the counter 211, the clock gater 222 is turned off, and the counter 211 stops counting. The second output Q2=0 of the counter 211, and when the rising edge of the clock signal arrives, the second register 212 collects the signal "1" received by the data input terminal in the previous cycle to the output terminal, so that the signal received by the enable terminal E of the third register 31 is the signal "1", and the third register 31 is in an enable state. Thereafter, the data input of the second register 212 becomes the signal "0" again.
In the 3 rd clock cycle after the counter 211 is full, since the signal received by the enable terminal E of the third register 31 in the 2 nd clock cycle is the signal "1", the 3 rd clock cycle may transmit the signal received by the data input terminal D of the third register 31, that is, the input signal of the target chip pin unit 4 to the output terminal Q of the third register 31. At this time, the second output Q2=0 of the counter 211 in the 2 nd clock cycle is collected by the output terminal of the second register 212, and the enable terminal E of the third register 31 is also the signal "0".
In the 4 th clock cycle after the counter 211 is full, the fourth register 32 collects the output of the third register 31 in the 3 rd clock cycle, that is, the input signal of the target chip pin unit 4, and since the enable end E of the third register 31 receives the signal "0", the output end Q of the third register 31 keeps the output signal of the target chip pin unit 4 unchanged in the 3 rd clock cycle after the counter 211 is full.
After the latching process is finished, the fourth register 32 outputs the input signal of the target chip pin unit 4 in the latching period unless the power-on reset module 11 is powered on again.
The embodiment of the invention also provides a power-on latch device which comprises the power-on latch circuit provided in the embodiment.
Compared with the prior art, the beneficial effects of the power-on latch device provided by the embodiment of the invention are the same as those of the power-on latch circuit in the technical scheme, and are not described herein again.
The embodiment of the present invention further provides a power-on latch method, which is applied to the power-on latch circuit provided in the above embodiment, and the power-on latch method includes:
in the latch period, controlling the reset control unit to provide a latch starting signal to the latch control unit;
in response to the latch enable signal, the latch control unit provides a latch control signal to the signal register unit;
in response to the latch control signal, the signal registering unit latches the input signal of the target chip pin unit and transmits the latched input signal to an external test mode signal end;
after the latch period, the latch control unit provides a latch stop signal to the signal registering unit;
in response to the latch stop signal, the signal registering unit stops latching the input signal of the target chip pin unit.
Compared with the prior art, the beneficial effects of the power-on latch method provided by the embodiment of the invention are the same as the beneficial effects of the power-on latch circuit in the technical scheme, and the details are not repeated here.
While the invention has been described in connection with various embodiments, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a review of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the word "a" or "an" does not exclude a plurality. A single processor or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.
While the invention has been described in conjunction with specific features and embodiments thereof, it will be evident that various modifications and combinations can be made thereto without departing from the spirit and scope of the invention. Accordingly, the specification and drawings are merely illustrative of the invention as defined by the appended claims and are intended to cover any and all modifications, variations, combinations, or equivalents within the scope of the invention. It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims (10)

1. A power-on latch circuit is characterized in that the power-on latch circuit is used for latching an input signal of a target chip pin unit and comprises a reset control unit, a latch control unit and a signal registering unit, wherein:
the output end of the reset control unit is electrically connected with the input end of the latch control unit, the output end of the latch control unit is electrically connected with the enable end of the signal registering unit, the target chip pin unit is electrically connected with the data input end of the signal registering unit, and the output end of the signal registering unit is electrically connected with the external test mode signal end;
in a latch period, the reset control unit is used for providing a latch starting signal to the latch control unit, and the latch control unit is used for generating a latch control signal under the action of the latch starting signal and sending the latch control signal to the signal registering unit; the signal registering unit is used for latching the input signal of the target chip pin unit according to the latch control signal and transmitting the latched input signal to the external test mode signal end;
after the latch period, the latch control unit is also used for generating a latch stop signal and sending the latch stop signal to the signal registering unit; the signal registering unit is used for stopping latching the input signal of the target chip pin unit according to the latching stop signal.
2. The power-on latch circuit according to claim 1, wherein the reset control unit comprises a power-on reset module and a reset synchronization module, wherein:
the output end of the power-on reset module is electrically connected with the data input end of the reset synchronous module and is used for providing a power-on reset signal for the reset synchronous module, the output end of the reset synchronous module is electrically connected with the input end of the latch control unit, the reset end of the latch control unit and the reset end of the signal registering unit, the latch control unit is used for controlling the latch control unit to start and controlling the latch control unit and the signal registering unit to stop resetting according to the power-on reset signal.
3. The power-on latch circuit according to claim 2, wherein the reset control unit further comprises a filtering module, a data input terminal of the filtering module is electrically connected to an output terminal of the power-on reset module, an output terminal of the filtering module is electrically connected to a data input terminal of the reset synchronization module, and the filtering module is configured to filter the power-on reset signal and transmit the filtered power-on reset signal to the reset synchronization module.
4. The power-on latch circuit according to claim 3, wherein the filter module comprises a plurality of first registers and an OR gate, wherein:
the plurality of first registers are connected in series, the output end of each first register is also electrically connected with the corresponding input end of the OR gate, and the output end of the OR gate is electrically connected with the input end of the reset synchronization module.
5. The power-on latch circuit according to claim 1, wherein the latch control unit comprises a count register module and a clock module, wherein:
the input end of the counting register module is electrically connected with the output end of the reset control unit and is used for starting counting under the control of the latching starting signal; the reset end of the counting register module is electrically connected with the output end of the reset control unit and used for stopping resetting under the action of the latching starting signal;
the first output end of the counting and registering module is electrically connected with the enabling end of the clock module and is used for controlling the clock module to be opened, the first output end of the clock module is electrically connected with the counting end of the counting and registering module, and the counting and registering module is used for counting output signals of the clock module; the counting and registering module is also used for controlling the clock module to be closed when the counting value of the counting and registering module reaches a target value;
the second output end of the counting and registering module is electrically connected with the enable end of the signal registering unit and is used for generating the latching control signal after the counting value of the counting and registering module reaches a target value, and the latching control signal is used for controlling the signal registering unit to latch the input signal of the target chip pin unit;
after the latch period, the counting register module is further configured to generate the latch stop signal, where the latch stop signal is used to control the signal register unit to stop latching the input signal of the target chip pin unit;
and the second output end of the clock module is respectively and electrically connected with the clock input end of the reset control unit, the clock input end of the counting register module and the clock input end of the signal register unit and is used for providing clock signals for the reset control unit, the counting register module and the signal register unit.
6. The power-on latch circuit according to claim 5, wherein the count register module comprises a counter and a second register, wherein:
the input end and the reset end of the counter are electrically connected with the output end of the reset control unit, the first output end of the counter is electrically connected with the enabling end of the clock module, the first output end of the clock module is electrically connected with the counting end of the counter, and the counter is used for controlling the clock module to be opened and counting the output signal of the clock module under the control of the latch starting signal;
a second output end of the counter is electrically connected with a data input end of the second register, an output end of the second register is electrically connected with an enable end of the signal registering unit, and the second register is used for transmitting the latch control signal or the latch stop signal generated by the counter to the enable end of the signal registering unit;
the second output end of the clock module is also electrically connected with the clock input end of the second register and used for providing the clock signal for the second register.
7. The power-on latch circuit according to claim 5, wherein the clock module comprises a clock gater and a clock signal terminal, wherein:
the clock signal end is respectively and electrically connected with the clock input end of the reset control unit, the clock input end of the counting and registering module, the clock input end of the signal registering unit and the clock input end of the clock door controller and is used for providing the clock signal for the reset control unit, the counting and registering module, the signal registering unit and the clock door controller;
the enabling end of the clock gate controller is electrically connected with the first output end of the counting and registering module, and the output end of the clock gate controller is electrically connected with the counting end of the counting and registering module.
8. The power-on latch circuit according to claim 1, wherein the signal registering unit comprises a third register and a fourth register, wherein:
the output end of the latch control unit is electrically connected with the enable end of the third register, the data input end of the third register is electrically connected with the target chip pin unit, and the output end of the third register is electrically connected with the data input end of the fourth register;
and the output end of the fourth register is electrically connected with the external test mode signal end.
9. A power-on latch device comprising the power-on latch circuit according to any one of claims 1 to 8.
10. A power-on latch method applied to the power-on latch circuit according to any one of claims 1 to 8, the power-on latch method comprising:
in the latch period, the reset control unit is controlled to provide a latch starting signal for the latch control unit;
the latch control unit provides a latch control signal to the signal register unit in response to the latch enable signal;
in response to the latch control signal, the signal registering unit latches an input signal of a target chip pin unit and transmits the latched input signal to an external test mode signal terminal;
after the latch period, the latch control unit provides a latch stop signal to the signal registering unit;
in response to the latch stop signal, the signal registering unit stops latching the input signal of the target chip pin unit.
CN202210745094.XA 2022-06-27 2022-06-27 Power-on latch circuit, power-on latch device and power-on latch method Pending CN115144740A (en)

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CN202210745094.XA CN115144740A (en) 2022-06-27 2022-06-27 Power-on latch circuit, power-on latch device and power-on latch method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210745094.XA CN115144740A (en) 2022-06-27 2022-06-27 Power-on latch circuit, power-on latch device and power-on latch method

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CN115144740A true CN115144740A (en) 2022-10-04

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