CN116453955A - Manufacturing method of single particle radiation resistant VDMOS device terminal - Google Patents
Manufacturing method of single particle radiation resistant VDMOS device terminal Download PDFInfo
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- CN116453955A CN116453955A CN202310727751.2A CN202310727751A CN116453955A CN 116453955 A CN116453955 A CN 116453955A CN 202310727751 A CN202310727751 A CN 202310727751A CN 116453955 A CN116453955 A CN 116453955A
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- 239000002245 particle Substances 0.000 title claims abstract description 27
- 230000005855 radiation Effects 0.000 title claims abstract description 21
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 37
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 37
- 239000010703 silicon Substances 0.000 claims abstract description 37
- 239000002184 metal Substances 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 238000005530 etching Methods 0.000 claims abstract description 13
- 238000000034 method Methods 0.000 claims abstract description 12
- 238000000151 deposition Methods 0.000 claims abstract description 9
- 229910004298 SiO 2 Inorganic materials 0.000 claims abstract description 6
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims abstract description 4
- 238000002513 implantation Methods 0.000 claims description 16
- -1 boron ions Chemical class 0.000 claims description 9
- 230000015556 catabolic process Effects 0.000 claims description 8
- 150000002500 ions Chemical class 0.000 claims description 7
- 229910052796 boron Inorganic materials 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 6
- 229910052698 phosphorus Inorganic materials 0.000 claims description 3
- 239000011574 phosphorus Substances 0.000 claims description 3
- 230000008569 process Effects 0.000 claims description 2
- 230000002787 reinforcement Effects 0.000 abstract description 5
- 238000006243 chemical reaction Methods 0.000 abstract description 3
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 10
- 238000010586 diagram Methods 0.000 description 5
- 239000007943 implant Substances 0.000 description 4
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 230000005669 field effect Effects 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000005865 ionizing radiation Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000191 radiation effect Effects 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses a method for manufacturing a single particle radiation resistant VDMOS device terminal, which belongs to the field of semiconductor devices and comprises the following steps: providing a silicon wafer comprising an n+ silicon substrate and an n-epitaxial layer; forming a P-field limiting ring in the n-epitaxial layer; forming an N-stop ring in the N-epitaxial layer; forming a P+ collection ring in the P-field limiting ring; sequentially depositing SiO 2 And polycrystal and carrying out polycrystal etching to form a polycrystal field plate; redeposition SiO 2 Etching to form a polycrystalline contact hole and a silicon contact hole; continuing to etch the polycrystalline field plate and the monocrystalline silicon substrate to form a silicon groove; depositing front metal on the front surface and etching to form a metal field plate; and depositing back metal on the back of the n+ silicon substrate to form a drain electrode. The invention improves the capability of the VDMOS terminal field limiting ring for collecting holes, realizes terminal single particle reinforcement, and can be used in the aerospace fieldThe design and manufacture of power devices in an electric propulsion system and a power supply system realize high-efficiency power electronic conversion in a radiation environment.
Description
Technical Field
The invention relates to the technical field of VDMOS devices, in particular to a manufacturing method of a single particle radiation resistant VDMOS device terminal.
Background
VDMOS (Vertical Diffused Metal-Oxide Semiconductor field effect transistor, vertical diffusion metal oxide field effect transistor) has the advantages of low power consumption, high switching speed, strong driving capability, negative temperature coefficient and the like, and is widely applied to power modules of satellite electronic systems. Under the space ionizing radiation environment, radiation effects generated on the VDMOS device mainly comprise SEB (Single Event Burnout, single particle burning), SEGR (Single Event Gate Rupture, single particle gate breakdown), total dose (Total dose) effect and the like. Compared with the conventional VDMOS device structure, the radiation-resistant VDMOS device structure needs special reinforcement design.
The SEB is a device burnout phenomenon caused by the fact that when charged particles are incident into the power device, a large number of electron-hole pairs are generated on an incident track of the charged particles, electrons move to a drain electrode and holes move to a source electrode under the action of an external voltage, and the lattice temperature of the material is rapidly increased in a region where high-density current and high voltage exist simultaneously. When high energy particles are incident from the termination region of the power device, holes generated by the incidence need to flow out from the termination equipotential ring because the termination surface region has no extraction path for hole carriers. This tends to cause a sharp increase in the transient current in this region, creating a breakdown point, which causes the device to experience a SEB failure.
Disclosure of Invention
The invention aims to provide a manufacturing method of a single particle radiation resistant VDMOS device terminal, which aims to solve the problems in the background technology and improve the single particle burning resistant capability of a medium-high voltage radiation resistant power device product.
In order to solve the technical problems, the invention provides a manufacturing method of a single particle radiation resistant VDMOS device terminal, which comprises the following steps:
providing a silicon wafer material, wherein the silicon wafer material comprises an n+ silicon substrate and an n-epitaxial layer which are stacked in sequence;
the implantation dose in the field-limiting ring pattern window in the n-epitaxial layer is 1×10 13 cm -2 Forming a P-field limiting ring;
the implantation dose in the cut-off ring pattern window in the n-epitaxial layer is 1×10 13 cm -2 Form an N-stop ring;
the implantation dose in the collection ring pattern window in the P-field limiting ring was 5 x 10 15 cm -2 And pushing the ions to form a P+ collecting ring;
sequentially depositing SiO on the whole surface 2 And polycrystal, and performing polycrystal etching to form a polycrystal field plate;
redeposition SiO 2 Etching to form a polycrystalline contact hole and a silicon contact hole in the contact hole pattern window; continuing to etch the polycrystalline field plate and the monocrystalline silicon substrate to form a silicon groove;
depositing front metal on the front surface, and etching in the metal pattern window to form a metal field plate;
and depositing back metal on the back of the n+ silicon substrate to form a drain electrode.
In one embodiment, the n+ silicon substrate is low-resistance with a doping concentration greater than 1.0X10 19 cm -3 The resistivity is 0.002-0.004 ohm cm; the n-epitaxial layer has a resistivity of 15 Ω.cm and a thickness of 60 μm.
In one embodiment, the implanted ions forming the P-field limiting ring are boron ions with an implantation energy of 100keV; the junction depth and doping profile of the P-field limiting ring meet the contact breakdown voltage requirements.
In one embodiment, the implanted ions forming the N-stop ring are phosphorus ions with an implantation energy of 100keV.
In one embodiment, the P-field limiter ring and N-stop ring are pushed together at 1200 ℃ for 300 minutes prior to forming the p+ collector ring.
In one embodiment, the implanted ions forming the P+ collection ring are boron ions, the implantation energy is 25keV, the junction pushing condition is 1100 ℃ for 100 minutes, and the junction depth after junction pushing is 1-2 μm.
In one embodiment, the distance between the polycrystalline contact hole and the silicon contact hole is 0-10 μm, which is determined by the process overlay capability; the depth of the silicon groove is 0.2-1 μm.
In one embodiment, the backside metal is TiNiAg, wherein the thickness of Ag is 2 μm.
The manufacturing method of the single-particle radiation resistant VDMOS device terminal improves the capability of collecting holes of a VDMOS terminal field limiting ring, realizes terminal single-particle reinforcement, can be used for designing and manufacturing power devices in an electric propulsion system and a power supply system in the aerospace field, and realizes high-efficiency power electronic conversion in a radiation environment.
Drawings
Fig. 1 is a schematic flow chart of a manufacturing method of a single particle radiation resistant VDMOS device terminal provided by the present invention.
Fig. 2 is a schematic diagram of a P-field limiting ring mask pattern and implant.
Fig. 3 is a schematic diagram of an N-stop-loop mask pattern and implant.
Fig. 4 is a schematic illustration of a p+ collection ring mask pattern and implant.
Fig. 5 is a schematic diagram of a mask pattern of a poly field plate and a post-poly etch.
Fig. 6 is a schematic diagram of a contact hole mask pattern and silicon hole etch.
Fig. 7 is a schematic diagram of a metal field plate after mask pattern metal etching.
Detailed Description
The following describes in further detail a method for manufacturing a single particle radiation resistant VDMOS device terminal according to the present invention with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
The invention provides a method for manufacturing a single particle radiation resistant VDMOS device terminal, which has a flow shown in figure 1 and comprises the following steps:
step one: p-field limiting ring implantation. As shown in fig. 2, the silicon wafer material includes an n+ silicon substrate and an n-epitaxial layer stacked in sequence; the resistivity of the n+ silicon substrate is 0.002-0.004 ohm cm; the resistivity of the n-epitaxial layer was 15. Omega. Cm and the thickness of the n-epitaxial layer was 60. Mu.m. Coating photoresist on silicon wafer, exposing pattern window, implanting boron ion to form P-field limiting ring, implanting energy of 100keV, and implanting dose of 1×10 13 cm -2 。
Step two: n-stop ring injection. As shown in fig. 3, the photoresist in the first step is removed, the photoresist is coated again on the silicon wafer and the pattern window is exposed, phosphorus ions are implanted to form an N-stop ring, the implantation energy is 100keV, and the implantation dose is 1×10 13 cm -2 。
Step three: p+ collection ring implant. Firstly removing the photoresist in the second step, and performing junction pushing on the P-field limiting ring and the N-cut-off ring under the conditions of 1200 ℃ and 300 minutes; as shown in fig. 4, a photoresist is coated again on a silicon wafer and a pattern window is exposed, boron ions are implanted and junction pushing is performed, a p+ collecting ring is formed on the inner upper surface of the P-field limiting ring, the implantation energy is 25keV, and the implantation dosage is 5×10 15 cm -2 The junction pushing condition is 1100 ℃ for 100 minutes, and the junction depth is 1-2 mu m after junction pushing.
For the breakdown voltage BVds, since the cells (repeating units) are planar junctions, the breakdown voltage of the planar junctions is the largest, but at the boundary of the chip, the planar junctions cannot be kept, and the breakdown voltage is reduced. A common termination structure is a field stop + field plate, and the field stop connected to the cell is called the main junction, i.e. as shown in fig. 4.
Step four: forming a polycrystalline field plate structure. As shown in fig. 5, in the removing step threeA layer of SiO with a thickness of 1000nm is deposited on the whole surface 2 And at SiO 2 A layer of polycrystal with the thickness of 1000nm is deposited on the surface of the silicon wafer, photoresist is coated again, a pattern window is exposed, polycrystal corrosion is carried out, and the coated photoresist is removed, so that a polycrystal field plate is formed; wherein the length and position of the poly-field plate are only related to the breakdown voltage BVds and the single particle performance is not directly related.
Step five: and manufacturing a contact hole structure. As shown in FIG. 6, after the completion of the polycrystalline field plate, a further layer of SiO with a thickness of 1000nm is deposited on the surface 2 Making the polycrystalline field plate be SiO 2 Coating, namely coating photoresist on a silicon wafer, exposing a pattern window, and etching contact holes to form contact holes (comprising polycrystalline contact holes and silicon contact holes), wherein the distance between the polycrystalline contact holes and the silicon contact holes is 0-10 mu m; continuously etching the monocrystalline silicon substrate and the polycrystalline field plate, and removing the coated photoresist to form a silicon groove with the depth of 0.2-1 mu m;
step six: a metal field plate structure. As shown in fig. 7, a metal having a thickness of 5 μm was deposited on the surface, a photoresist was coated on a silicon wafer and a pattern window was exposed, and metal etching was performed to form a metal field plate. Finally, a layer of TiNiAg is deposited on the back surface of the n+ silicon substrate, wherein the thickness of the Ag is 2 mu m, and a drain electrode is formed.
According to the method for adding the P+ collecting ring, the capability of collecting holes of the VDMOS terminal field limiting ring is improved, and terminal single particle reinforcement is realized. The single particle reinforcement terminal provided by the invention can be used for designing and manufacturing power devices in an electric propulsion system and a power supply system in the aerospace field, and can realize high-efficiency power electronic conversion in a radiation environment.
The above description is only illustrative of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, and any alterations and modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the appended claims.
Claims (8)
1. The manufacturing method of the single particle radiation resistant VDMOS device terminal is characterized by comprising the following steps:
providing a silicon wafer material, wherein the silicon wafer material comprises an n+ silicon substrate and an n-epitaxial layer which are stacked in sequence;
the implantation dose in the field-limiting ring pattern window in the n-epitaxial layer is 1×10 13 cm -2 Forming a P-field limiting ring;
the implantation dose in the cut-off ring pattern window in the n-epitaxial layer is 1×10 13 cm -2 Form an N-stop ring;
the implantation dose in the collection ring pattern window in the P-field limiting ring was 5 x 10 15 cm -2 And pushing the ions to form a P+ collecting ring;
sequentially depositing SiO on the whole surface 2 And polycrystal, and performing polycrystal etching to form a polycrystal field plate;
redeposition SiO 2 Etching to form a polycrystalline contact hole and a silicon contact hole in the contact hole pattern window; continuing to etch the polycrystalline field plate and the monocrystalline silicon substrate to form a silicon groove;
depositing front metal on the front surface, and etching in the metal pattern window to form a metal field plate;
and depositing back metal on the back of the n+ silicon substrate to form a drain electrode.
2. The method for manufacturing a single particle radiation resistant VDMOS device terminal as defined in claim 1, wherein the n+ silicon substrate has a low resistance and a doping concentration of greater than 1.0X10 19 cm -3 The resistivity is 0.002-0.004 ohm cm; the n-epitaxial layer has a resistivity of 15 Ω.cm and a thickness of 60 μm.
3. The method for manufacturing a single particle radiation resistant VDMOS device terminal as defined in claim 1, wherein the implanted ions forming the P-field limiting ring are boron ions with an implantation energy of 100keV; the junction depth and doping profile of the P-field limiting ring meet the contact breakdown voltage requirements.
4. The method of manufacturing a single particle radiation-resistant VDMOS device termination of claim 1 wherein the implanted ions forming the N-stop ring are phosphorus ions with an implantation energy of 100keV.
5. The method of claim 1, wherein the P-field limiting ring and the N-stop ring are pushed together before forming the p+ collection ring, the push-together condition being 1200 ℃ for 300 minutes.
6. The method of claim 1, wherein the p+ collecting ring is formed by implanting boron ions at 25keV, the junction pushing condition is 1100 ℃ for 100 minutes, and the junction depth is 1-2 μm after the junction pushing.
7. The method for manufacturing the single particle radiation resistant VDMOS device terminal as claimed in claim 1, wherein the distance between the polycrystalline contact hole and the silicon contact hole is 0-10 μm, which is determined by the process overlay capability; the depth of the silicon groove is 0.2-1 μm.
8. The method for manufacturing a single particle radiation resistant VDMOS device terminal of claim 1 wherein the backside metal is TiNiAg, wherein the thickness of Ag is 2 μm.
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| CN202310727751.2A CN116453955A (en) | 2023-06-20 | 2023-06-20 | Manufacturing method of single particle radiation resistant VDMOS device terminal |
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| CN202310727751.2A CN116453955A (en) | 2023-06-20 | 2023-06-20 | Manufacturing method of single particle radiation resistant VDMOS device terminal |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102034818A (en) * | 2009-09-30 | 2011-04-27 | 万国半导体股份有限公司 | High voltage mosfet diode reverse recovery by minimizing p-body charges |
| CN104779303A (en) * | 2015-02-15 | 2015-07-15 | 电子科技大学 | Vertical constant-current diode and manufacturing method thereof |
| CN109103248A (en) * | 2018-08-23 | 2018-12-28 | 深圳市南硕明泰科技有限公司 | A kind of power device terminal structure and preparation method thereof |
| CN112071905A (en) * | 2020-09-07 | 2020-12-11 | 上海陆芯电子科技有限公司 | Terminal structure of semiconductor device and insulated gate bipolar transistor |
| CN114335154A (en) * | 2022-03-10 | 2022-04-12 | 深圳市威兆半导体有限公司 | Semiconductor device, terminal structure and manufacturing method thereof |
-
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- 2023-06-20 CN CN202310727751.2A patent/CN116453955A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102034818A (en) * | 2009-09-30 | 2011-04-27 | 万国半导体股份有限公司 | High voltage mosfet diode reverse recovery by minimizing p-body charges |
| CN104779303A (en) * | 2015-02-15 | 2015-07-15 | 电子科技大学 | Vertical constant-current diode and manufacturing method thereof |
| CN109103248A (en) * | 2018-08-23 | 2018-12-28 | 深圳市南硕明泰科技有限公司 | A kind of power device terminal structure and preparation method thereof |
| CN112071905A (en) * | 2020-09-07 | 2020-12-11 | 上海陆芯电子科技有限公司 | Terminal structure of semiconductor device and insulated gate bipolar transistor |
| CN114335154A (en) * | 2022-03-10 | 2022-04-12 | 深圳市威兆半导体有限公司 | Semiconductor device, terminal structure and manufacturing method thereof |
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