CN116436446B - Integrated circuit logic failure monitoring circuit and isolation circuit - Google Patents

Integrated circuit logic failure monitoring circuit and isolation circuit Download PDF

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Publication number
CN116436446B
CN116436446B CN202310688193.3A CN202310688193A CN116436446B CN 116436446 B CN116436446 B CN 116436446B CN 202310688193 A CN202310688193 A CN 202310688193A CN 116436446 B CN116436446 B CN 116436446B
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circuit
logic
logic level
gate
electrically connected
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CN116436446A (en
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周仲武
程君健
翟冠杰
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Shenzhen Saiyuan Microelectronics Co ltd
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Shenzhen Saiyuan Microelectronics Co ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/125—Discriminating pulses
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/007—Fail-safe circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Nonlinear Science (AREA)
  • Logic Circuits (AREA)

Abstract

The invention relates to the technical field of circuit monitoring and discloses an integrated circuit logic failure monitoring circuit and an isolation circuit; the invention connects the first logic level unit and the first combined logic circuit, the first logic level unit outputs the first logic level or the second logic level according to the working voltage state of the first combined logic circuit, the AND gate unit outputs the monitoring signal according to the received logic level, when the working voltage of the first combined logic circuit fails, the first logic level unit outputs the second logic level, and the AND gate unit outputs the second monitoring signal at the moment, thus the working voltage failure of the first combined logic circuit can be detected.

Description

Integrated circuit logic failure monitoring circuit and isolation circuit
Technical Field
The invention relates to the technical field of circuit monitoring, in particular to an integrated circuit logic failure monitoring circuit and an isolation circuit.
Background
An integrated circuit is a miniature electronic device that includes logic circuitry comprised of a number of transistors and other electronic components that can be used to implement various logic functions.
In a logic circuit, there is a risk that the circuit fails, that is, when the operating voltage of the logic circuit is lower than the failure voltage of the logic circuit, the logic circuit cannot operate normally, so in actual operation, a low voltage monitoring module is generally required to monitor the operating voltage of the logic circuit, and reset is performed when the operating voltage of the logic circuit is lower than a preset value, so as to avoid the failure of the logic circuit under the low voltage.
In this method, when setting the preset value, the range of the failure voltage of the logic circuit needs to be considered to ensure that the circuit failure does not occur, and since the logic failure voltage is usually a range, not a specific value, the preset value needs to be higher than the minimum value in the range of the failure voltage to ensure the reliability of the circuit.
However, since the preset value needs to be higher than the minimum value in the failure voltage range, the low voltage monitor value may be actually higher than necessary, thereby limiting the wide voltage range of the circuit.
Disclosure of Invention
The invention aims to provide an integrated circuit logic failure monitoring circuit and an isolation circuit, which aim to solve the problem that failure voltage monitoring of a logic circuit in the prior art can limit the wide voltage range of the circuit.
The present invention is achieved in a first aspect by providing an integrated circuit logic failure monitoring circuit provided in an integrated circuit, the integrated circuit including a first combinational logic circuit and a second combinational logic circuit, the integrated circuit logic failure monitoring circuit comprising:
the first logic level unit, the second logic level unit and the AND gate circuit;
the first logic level unit is electrically connected with the first combinational logic circuit, and generates a first logic level when the working voltage of the first combinational logic circuit is normal, and generates a second logic level when the working voltage of the first combinational logic circuit is invalid;
the second logic level unit is grounded, and the second logic level unit is used for generating a second logic level;
the AND gate circuit is provided with a forward input end, a reverse input end and an AND gate output end, is electrically connected with the first logic level unit through the forward input end, is electrically connected with the second logic level unit through the reverse input end and is electrically connected with the second combinational logic circuit through the AND gate output end;
when the AND gate circuit receives a first logic level through the forward input end and receives a second logic level through the reverse input end, the AND gate circuit outputs a first monitoring signal through the AND gate output end;
and when the AND gate circuit receives the second logic level through the forward input end and receives the second logic level through the reverse input end, the AND gate circuit outputs a second monitoring signal through the AND gate output end.
In some embodiments, the first logic level cell includes a pull-up resistor, a first buffer, a first inverter, and a first operational amplifier;
the pull-up resistor is electrically connected with the first combinational logic circuit, the first buffer and the first inverter respectively, the first operational amplifier is provided with two input ends and one output end, the first operational amplifier is electrically connected with the first buffer through one input end, is electrically connected with the first inverter through the other input end and is electrically connected with the AND gate circuit through the output end;
when the working voltage of the first combinational logic circuit is normal, the pull-up resistor receives a voltage signal of the first combinational logic circuit and generates a high-level signal, the first buffer and the first inverter are used for converting the high-level signal into a differential signal 1, and the first operational amplifier is used for converting the differential signal 1 into a first logic level;
when the working voltage of the first combinational logic circuit fails, the pull-up resistor receives the voltage signal of the first combinational logic circuit and generates a low-level signal, the first buffer and the first inverter are used for converting the low-level signal into a differential signal 0, and the first operational amplifier is used for converting the differential signal 0 into a second logic level.
In some embodiments, the second logic level cell includes a pull-down resistor, a second buffer, a second inverter, and a second operational amplifier;
the pull-down resistor is respectively and electrically connected with the first combination logic circuit, the second buffer and the second inverter, the second operational amplifier is provided with two input ends and one output end, the second operational amplifier is electrically connected with the first buffer through one input end, is electrically connected with the second inverter through the other input end, and is electrically connected with the AND gate circuit through the output end;
the pull-down resistor is used for generating a low-level signal, the second buffer and the second inverter are used for converting the low-level signal into a differential signal 0, and the second operational amplifier is used for converting the differential signal 0 into a second logic level.
In a second aspect, the present invention provides an integrated circuit logic failure isolation circuit, disposed in an integrated circuit, the integrated circuit logic failure isolation circuit being electrically connected to an integrated circuit logic failure monitoring circuit, a first combinational logic circuit, and a second combinational logic circuit according to any one of the first aspect, the integrated circuit logic failure isolation circuit comprising:
a gate circuit unit;
the gate circuit unit is provided with two input ends and an output end, and is respectively and electrically connected with the integrated circuit logic failure monitoring circuit and the first combination logic circuit through the two input ends and is electrically connected with the second combination logic circuit through the output end.
In some embodiments, the gate unit is an and gate.
In some embodiments, the gate unit is an or gate.
The invention provides an integrated circuit logic failure monitoring circuit, which has the following beneficial effects:
the invention connects the first logic level unit and the first combined logic circuit, the first logic level unit outputs the first logic level or the second logic level according to the working voltage state of the first combined logic circuit, the AND gate unit outputs the monitoring signal according to the received logic level, when the working voltage of the first combined logic circuit fails, the first logic level unit outputs the second logic level, and the AND gate unit outputs the second monitoring signal at the moment, thus the working voltage failure of the first combined logic circuit can be detected.
Drawings
FIG. 1 is a schematic diagram of an integrated circuit logic failure monitoring circuit according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of an integrated circuit logic failure isolation circuit according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of integrated circuit monitoring using a low voltage monitoring module in a conventional approach;
fig. 4 is a schematic diagram of integrated circuit monitoring using integrated circuit logic failure monitoring circuit gold according to an embodiment of the present invention.
Reference numerals: 1-first logic level unit, 2-second logic level unit, 3-AND gate circuit, 11-pull-up resistor, 12-first buffer, 13-first inverter, 14-first operational amplifier, 21-pull-down resistor, 22-second buffer, 23-second inverter, 24-second operational amplifier, 31-forward input, 32-reverse input, 33-AND gate output.
Detailed Description
The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
The same or similar reference numerals in the drawings of the present embodiment correspond to the same or similar components; in the description of the present invention, it should be understood that, if there is an azimuth or positional relationship indicated by terms such as "upper", "lower", "left", "right", etc., based on the azimuth or positional relationship shown in the drawings, it is only for convenience of describing the present invention and simplifying the description, but it is not indicated or implied that the apparatus or element referred to must have a specific azimuth, be constructed and operated in a specific azimuth, and thus terms describing the positional relationship in the drawings are merely illustrative and should not be construed as limitations of the present patent, and specific meanings of the terms described above may be understood by those skilled in the art according to specific circumstances.
The implementation of the present invention will be described in detail below with reference to specific embodiments.
Referring to fig. 1, 2, 3 and 4, a preferred embodiment of the present invention is provided.
In a first aspect, the present invention provides an integrated circuit logic failure monitoring circuit disposed in an integrated circuit, the integrated circuit including a first combinational logic circuit and a second combinational logic circuit, the integrated circuit logic failure monitoring circuit comprising:
a first logic level unit 1, a second logic level unit 2 and an AND gate 3.
Specifically, in the present invention, the integrated circuit is divided into a first combinational logic circuit and a second combinational logic circuit, wherein the first combinational logic circuit provides a voltage signal for the second combinational logic circuit, so that the whole integrated circuit can normally operate.
More specifically, the first combinational logic circuit and the second combinational logic circuit belong to the combinational logic circuit, and the functional characteristics of the combinational logic circuit are that the output at any moment only depends on the input at the moment and is irrelevant to the original state of the circuit, so that when the voltage signal input into the combinational logic circuit fails, the output result can be wrong.
Preferably, in order to avoid the occurrence of the above phenomenon, the present invention inserts an integrated circuit logic failure monitoring circuit between the first combinational logic circuit and the second combinational logic circuit to monitor the failure voltage of the integrated circuit.
Specifically, the first logic level unit 1 is electrically connected to the first combinational logic circuit, the second logic level unit 2 is grounded, the first logic level unit 1 and the second logic level unit 2 are both circuit units for generating logic levels, the logic levels generated by the first logic level unit 1 depend on the working voltage of the first combinational logic circuit, and the logic level generated by the second logic level unit 2 due to grounding is fixed.
More specifically, the logic levels may be roughly divided into a high voltage, which may be identified as a first logic level, and a low voltage, which may be identified as a second logic level.
More specifically, the first logic level unit 1 generates the first logic level when the operation voltage of the first combinational logic circuit is normal, and the first logic level unit 1 generates the second logic level when the operation voltage of the first combinational logic circuit is invalid.
More specifically, the second logic level unit 2 generates the second logic level fixedly due to the ground.
Specifically, the and circuit 3 has a forward input terminal 31, a reverse input terminal 32, and an and gate output terminal 33, and the and circuit 3 is electrically connected to the first logic level unit 1 through the forward input terminal 31, to the second logic level unit 2 through the reverse input terminal 32, and to the second combinational logic circuit through the and gate output terminal 33.
More specifically, the inverting input 32 has a function of inverting the signal, that is, when the second logic level circuit inputs the second logic level to the and circuit 3 through the inverting input 32, the inverting input 32 converts the second logic level to the first logic level, and when the second logic level circuit inputs the first logic level to the and circuit 3 through the inverting input 32, the inverting input 32 converts the first logic level to the second logic level.
Whereas in the present invention the second logic level unit 2 generates the second logic level, so that the logic level received by the and gate unit from the second logic level unit 2 via the direction input is actually the first logic level.
It should be noted that the and circuit 3 is a logic gate circuit, and generally has a plurality of input terminals and one output terminal, when the plurality of input terminals of the and circuit 3 are all input with a high level, the output terminal of the and circuit 3 outputs a high level, and when the one input terminal of the and circuit 3 is input with a low level, the output terminal of the and circuit 3 outputs a low level.
In connection with the above, it is apparent that the and gate output 33 of the and gate 3 outputs the first monitor signal when the and gate 3 receives the first logic level through the forward input terminal 31 and the second logic level through the reverse input terminal 32, and the and gate output 33 of the and gate 3 outputs the second monitor signal when the and gate 3 receives the second logic level through the forward input terminal 31 or the first logic level through the reverse input terminal 32.
It will be appreciated that when the first logic level unit 1 outputs the first logic level and the second logic level unit 2 outputs the second logic level, the forward input terminal 31 receives the first logic level and the reverse input terminal 32 receives the second logic level, and the operation voltage of the first combinational logic circuit is in a normal state, and the and gate output terminal 33 outputs the first logic level.
When the first logic level unit 1 outputs the second logic level, the positive input terminal 31 receives the second logic level, and the working voltage of the first combinational logic circuit is in a failure state, and the and gate output terminal 33 outputs the second logic level.
Therefore, when the second combinational logic circuit receives the first logic level output from the and circuit 3, the operation voltage of the first combinational logic circuit can be confirmed to be in a normal state, and when the second combinational logic circuit receives the second logic level output from the and circuit 3, the operation voltage of the first combinational logic circuit can be confirmed to be in a failure state.
Referring to fig. 3 and 4, it can be seen that the present invention has advantages over the conventional monitoring method: the traditional method needs to set a preset value which is higher than the failure voltage of the circuit, and the method monitors and isolates the circuit when the working voltage of the circuit fails, so that the circuit has a wider working range compared with the traditional method.
The invention provides an integrated circuit logic failure monitoring circuit, which has the following beneficial effects:
the first logic level unit 1 is electrically connected with the first combined logic circuit, the first logic level unit 1 outputs the first logic level or the second logic level according to the working voltage state of the first combined logic circuit, the AND gate unit outputs the monitoring signal according to the received logic level, when the working voltage of the first combined logic circuit fails, the first logic level unit 1 outputs the second logic level, and the AND gate unit outputs the second monitoring signal at the moment, so that the working voltage failure of the first combined logic circuit can be detected.
In some embodiments, the first logic level cell 1 includes a pull-up resistor 11, a first buffer 12, a first inverter 13, and a first operational amplifier 14.
Specifically, the pull-up resistor 11 is electrically connected to the first combinational logic circuit, the first buffer 12, and the first inverter 13, respectively, the first operational amplifier 14 has two input terminals and one output terminal, the first operational amplifier 14 is electrically connected to the first buffer 12 through one input terminal, is electrically connected to the first inverter 13 through the other input terminal, and is electrically connected to the and circuit 3 through the output terminal.
More specifically, when the operation voltage of the first combinational logic circuit is normal, the pull-up resistor 11 receives the voltage signal of the first combinational logic circuit and generates a high level signal, the first buffer 12 and the first inverter 13 are used for converting the high level signal into the differential signal 1, and the first operational amplifier 14 is used for converting the differential signal 1 into the first logic level.
More specifically, when the operating voltage of the first combinational logic circuit fails, the pull-up resistor 11 will receive the voltage signal of the first combinational logic circuit and generate a low level signal, the first buffer 12 and the first inverter 13 are used to convert the low level signal into the differential signal 0, and the first operational amplifier 14 is used to convert the differential signal 0 into the second logic level.
It should be noted that, the buffer and the inverter are both electronic devices in the prior art, where the purpose of the buffer is to enhance the driving capability and the transmission capability of the signal, and the purpose of the inverter is to invert the input signal into an output signal opposite to the input signal.
More specifically, the operational amplifier is also an electronic device in the prior art, and is an amplifying circuit capable of performing mathematical operations, and in the present invention, the first operational amplifier 14 converts the received differential signal to generate the first logic level or the second logic level, and transmits the first logic level or the second logic level to the and circuit 3.
In some embodiments, the second logic level unit 2 includes a pull-down resistor 21, a second buffer 22, a second inverter 23, and a second operational amplifier 24.
Specifically, the pull-down resistor 21 is electrically connected to the first combinational logic circuit, the second buffer 22, and the second inverter 23, respectively, the second operational amplifier 24 has two input terminals and one output terminal, the second operational amplifier 24 is electrically connected to the first buffer 12 through one input terminal, is electrically connected to the second inverter 23 through the other input terminal, and is electrically connected to the and circuit 3 through the output terminal.
More specifically, the pull-down resistor 21 is used to generate a low level signal, the second buffer 22 and the second inverter 23 are used to convert the low level signal into a differential signal 0, and the second operational amplifier 24 is used to convert the differential signal 0 into a second logic level.
It will be appreciated that the second logic level unit 2 will continue to transmit the second logic level to the and circuit 3, and the inverting input 32 of the and circuit 3 will convert the second logic level to the first logic level, and depending on the characteristics of the and circuit 3, it can be seen that the output of the and circuit 3 is dependent on the output of the first logic level unit 1 as either logic signal 1 or logic signal 0.
In a second aspect, the present invention provides an integrated circuit logic failure isolation circuit, disposed in an integrated circuit, the integrated circuit logic failure isolation circuit being electrically connected to an integrated circuit logic failure monitoring circuit, a first combinational logic circuit, and a second combinational logic circuit according to any one of the first aspect, comprising:
and a gate unit.
Specifically, the gate circuit unit has two input terminals and one output terminal, and the gate circuit unit is electrically connected with an integrated circuit logic failure monitoring circuit and a first combinational logic circuit through the two input terminals, and is electrically connected with a second combinational logic circuit through the output terminal.
More specifically, the gate units may be the and gate 3 and the or gate, and the number of the gate units may be one or a plurality.
It should be noted that the and circuit 3 and the or circuit belong to basic logic gates, and are used to implement the and relationship and the or relationship.
When the gate circuit unit is an AND gate, the AND gate receives the voltage signals of the first combinational logic circuit and converts the voltage signals into 0 to realize signal isolation of the first combinational logic circuit.
When the gate circuit unit is an OR gate, the OR gate receives the voltage signals of the first combinational logic circuit and converts all the voltage signals into 1 so as to realize signal isolation of the first combinational logic circuit.
The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the invention.

Claims (6)

1. An integrated circuit logic failure monitoring circuit disposed in an integrated circuit, the integrated circuit comprising a first combinational logic circuit and a second combinational logic circuit, the integrated circuit logic failure monitoring circuit comprising:
the first logic level unit, the second logic level unit and the AND gate circuit;
the first logic level unit is electrically connected with the first combinational logic circuit, and generates a first logic level when the working voltage of the first combinational logic circuit is normal, and generates a second logic level when the working voltage of the first combinational logic circuit is invalid;
the second logic level unit is grounded, and the second logic level unit is used for generating a second logic level;
the AND gate circuit is provided with a forward input end, a reverse input end and an AND gate output end, is electrically connected with the first logic level unit through the forward input end, is electrically connected with the second logic level unit through the reverse input end and is electrically connected with the second combinational logic circuit through the AND gate output end;
when the AND gate circuit receives a first logic level through the forward input end and receives a second logic level through the reverse input end, the AND gate circuit outputs a first monitoring signal through the AND gate output end;
and when the AND gate circuit receives the second logic level through the forward input end and receives the second logic level through the reverse input end, the AND gate circuit outputs a second monitoring signal through the AND gate output end.
2. The integrated circuit logic failure monitoring circuit of claim 1, wherein the first logic level unit comprises a pull-up resistor, a first buffer, a first inverter, and a first operational amplifier;
the pull-up resistor is electrically connected with the first combinational logic circuit, the first buffer and the first inverter respectively, the first operational amplifier is provided with two input ends and one output end, the first operational amplifier is electrically connected with the first buffer through one input end, is electrically connected with the first inverter through the other input end and is electrically connected with the AND gate circuit through the output end;
when the working voltage of the first combinational logic circuit is normal, the pull-up resistor receives a voltage signal of the first combinational logic circuit and generates a high-level signal, the first buffer and the first inverter are used for converting the high-level signal into a differential signal 1, and the first operational amplifier is used for converting the differential signal 1 into a first logic level;
when the working voltage of the first combinational logic circuit fails, the pull-up resistor receives the voltage signal of the first combinational logic circuit and generates a low-level signal, the first buffer and the first inverter are used for converting the low-level signal into a differential signal 0, and the first operational amplifier is used for converting the differential signal 0 into a second logic level.
3. The integrated circuit logic failure monitoring circuit of claim 1, wherein the second logic level unit includes a pull-down resistor, a second buffer, a second inverter, and a second operational amplifier;
the pull-down resistor is respectively and electrically connected with the first combination logic circuit, the second buffer and the second inverter, the second operational amplifier is provided with two input ends and one output end, the second operational amplifier is electrically connected with the second buffer through one input end, is electrically connected with the second inverter through the other input end, and is electrically connected with the AND gate circuit through the output end;
the pull-down resistor is used for generating a low-level signal, the second buffer and the second inverter are used for converting the low-level signal into a differential signal 0, and the second operational amplifier is used for converting the differential signal 0 into a second logic level.
4. An integrated circuit logic failure isolation circuit disposed in an integrated circuit, wherein the integrated circuit logic failure isolation circuit is electrically connected to an integrated circuit logic failure monitoring circuit, a first combinational logic circuit, and a second combinational logic circuit as described in any of claims 1-3, the integrated circuit logic failure isolation circuit comprising:
a gate circuit unit;
the gate circuit unit is provided with two input ends and an output end, and is electrically connected with the integrated circuit logic failure monitoring circuit through one input end, is electrically connected with the first combinational logic circuit through the other input end and is electrically connected with the second combinational logic circuit through the output end.
5. The integrated circuit logic failure isolation circuit of claim 4, wherein the gate unit is an and gate.
6. The integrated circuit logic failure isolation circuit of claim 4, wherein the gate unit is an or gate.
CN202310688193.3A 2023-06-12 2023-06-12 Integrated circuit logic failure monitoring circuit and isolation circuit Active CN116436446B (en)

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JP2003198361A (en) * 2001-12-28 2003-07-11 Fujitsu Ltd Programmable logical device
CN1975934A (en) * 2005-01-28 2007-06-06 株式会社瑞萨科技 A semiconductor integlated circuit having test function and manufacturing method
CN108646170A (en) * 2018-05-15 2018-10-12 安徽理工大学 A kind of soft fault preventing ageing predetermination sensor based on duplication redundancy
CN113009257A (en) * 2021-02-26 2021-06-22 西安微电子技术研究所 Simple and reliable power-on state detection circuit
CN113933677A (en) * 2021-10-26 2022-01-14 重庆大学 SiC MOSFET device grid electrode aging monitoring circuit and online monitoring method
CN115833863A (en) * 2022-11-11 2023-03-21 中国电子科技集团公司第二十九研究所 TR assembly protection logic circuit, control logic and transceiving control system

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JP2003198361A (en) * 2001-12-28 2003-07-11 Fujitsu Ltd Programmable logical device
CN1975934A (en) * 2005-01-28 2007-06-06 株式会社瑞萨科技 A semiconductor integlated circuit having test function and manufacturing method
CN108646170A (en) * 2018-05-15 2018-10-12 安徽理工大学 A kind of soft fault preventing ageing predetermination sensor based on duplication redundancy
CN113009257A (en) * 2021-02-26 2021-06-22 西安微电子技术研究所 Simple and reliable power-on state detection circuit
CN113933677A (en) * 2021-10-26 2022-01-14 重庆大学 SiC MOSFET device grid electrode aging monitoring circuit and online monitoring method
CN115833863A (en) * 2022-11-11 2023-03-21 中国电子科技集团公司第二十九研究所 TR assembly protection logic circuit, control logic and transceiving control system

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