CN113009257A - Simple and reliable power-on state detection circuit - Google Patents
Simple and reliable power-on state detection circuit Download PDFInfo
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- CN113009257A CN113009257A CN202110222527.9A CN202110222527A CN113009257A CN 113009257 A CN113009257 A CN 113009257A CN 202110222527 A CN202110222527 A CN 202110222527A CN 113009257 A CN113009257 A CN 113009257A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/0084—Arrangements for measuring currents or voltages or for indicating presence or sign thereof measuring voltage only
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
- G01R31/66—Testing of connections, e.g. of plugs or non-disconnectable joints
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Abstract
The invention provides a simple and reliable electrifying state detection circuit, which is characterized in that an electrifying voltage signal is acquired through a signal acquisition circuit and generates an acquisition signal, the acquisition signal is compared with a reference voltage formed in a reference circuit and then is converted into an OC interface signal through a logic state conversion circuit, and the OC interface signal is converted into an OC interface signal through a driver, so that a state indicating circuit is conveniently connected; the power-on state detection circuit judges the state by multi-point characteristic voltage subsection detection, and has simple structure and convenient debugging; meanwhile, the power-on state detection circuit has continuous voltage output logic state in a partition mode, and an output interface is high in compatibility and easy to adjust.
Description
Technical Field
The invention relates to the technical field of detection, in particular to a simple and reliable power-on state detection circuit.
Background
At present, the power-on state of an electronic product is usually determined by whether an actual voltage signal after power-on exists or not, and the result is used for indicating that the product is normal or faulty. From the perspective of a product user, the trend of the working quality change of the electronic product with long service life and long-term operation can be prompted, the electronic product is more humanized, and the current power-on state detection mode does not have the interpretation of the working quality change trend of the product in use.
Disclosure of Invention
The invention provides a simple and reliable electrified state detection circuit, which is simple in structure and convenient to adjust, and improves the safety of an electronic product in the using process by carrying out characteristic segmentation state detection and continuous state output on electrified voltage of the electronic product.
The invention is realized by the following technical scheme:
a simple and reliable power-on state detection circuit comprises a signal acquisition circuit, a logic state conversion circuit and a driver U6; the signal acquisition circuit comprises an input interface circuit and a reference circuit, wherein the input interface circuit is connected with a power-on voltage signal V of an external detection pointtestThe input interface circuit is provided with a first resistance unit, and the voltage division network of the first resistance unit acquires an external detection point VtestVoltage of (3) generating corresponding acquisition signal Usap(ii) a 5V voltage-stabilized power supply V is connected to an input port of the reference circuitcc5VThe reference circuit is provided with a second resistance unit, and the second resistance unit voltage division network generates a section reference voltage; the reference voltage of the section respectively passes through a unit gain buffer arranged in the first-stage operational amplifier unit and then is connected with the acquisition signal UsapThe internal state signals are input into the logic state conversion circuit to generate logic state signals, and the logic state signals are input into a driver U6 to form low-level effective OC driving signals which are used for connecting a power-on state indicating or alarming circuit and a direct butt joint digital interface acquisition circuit.
Preferably, the first resistor unit comprises a resistor R1 and a resistor R2, and the resistor R1 and the resistor R2 divide the voltage network to collect the external detection point VtestVoltage of generating acquisition signal Usap(ii) a The second resistance unit comprises a resistor R3, a resistor R4, a resistor R5 and a resistor R6; voltage-stabilized power supply Vcc5VThe first reference voltage U is generated after the voltage division network of the resistor R3, the resistor R4, the resistor R5 and the resistor R6 respectivelyreaA second reference voltage UrebAnd a third reference voltage Urec。
Further, collecting signal UsapThe signal attenuation coefficient of (2) is R2/(R1+ R2).
Further, the first stage operational amplifier unit includes an operational amplifier U1A, an operational amplifier U2A and an operational amplifier U3A, wherein the operational amplifier U1A, the operational amplifier U2A and the operational amplifier U3A are respectively designed to be in a unity gain buffer state, and the operational amplifier U1A applies a first reference voltage U1reaThe stable output is sent to a post-stage circuit; the operational amplifier U2A converts the second reference voltage UrebThe stable output is sent to a post-stage circuit; the operational amplifier U3A converts the third reference voltage UrecThe stable output is sent to a post-stage circuit;
the second stage operational amplifier unit comprises an operational amplifier U1B, an operational amplifier U2B and an operational amplifier U3B, wherein the operational amplifier U1B, the operational amplifier U2B and the operational amplifier U3B work in a signal in-phase comparison state.
Still more preferably, the in-phase comparison state of the signals is as follows,
first reference voltage UreaAfter being stably output by an operational amplifier U1A, the signal U is collectedsapComparing the signals in the operational amplifier U1B to generate a first state signal A;
second reference voltage UrebAfter being stably output by an operational amplifier U2A, the signal U is collectedsapComparing at an operational amplifier U2B to generate a second state signal B;
third reference voltage UrecAfter being stably output by an operational amplifier U3A, the signal U is collectedsapThe comparison is made at operational amplifier U3B to generate a third state signal C.
Preferably, the logic state transition circuit comprises a NAND gate U4A, a NAND gate U4B, a NAND gate U4C, a NAND gate U4D, an inverter U5A, an inverter U5B and an inverter U5C, and the internal state signal generates the corresponding power-on voltage signal V through the logic state transition circuit consisting of a NOT gate and an invertertestA logic state signal of a power-up state change.
Preferably, a voltage regulator tube V1 is arranged on the signal acquisition circuit; collecting signal U generated by voltage regulator tube V1 and input interface circuitsapArranged in parallel for inputting a power-on voltage signal VtestDrift beyond limitAnd fault isolation is performed, so that a rear-stage circuit is protected.
Preferably, the signal acquisition circuit is provided with a capacitor C1, and the capacitor C1 and the acquisition signal U generated by the input interface circuitsapAnd the parallel connection is used for improving the anti-interference capability of the input interface of the system.
Compared with the prior art, the invention has the following beneficial technical effects:
the invention provides a simple and reliable electrifying state detection circuit, which is characterized in that an electrifying voltage signal is acquired through a signal acquisition circuit and generates an acquisition signal, the acquisition signal is compared with a reference voltage formed in a reference circuit and then is converted into an OC interface signal through a logic state conversion circuit, and the OC interface signal is converted into an OC interface signal through a driver, so that a state indicating circuit is conveniently connected; the power-on state detection circuit judges the state by multi-point characteristic voltage subsection detection, and has simple structure and convenient debugging; meanwhile, the power-on state detection circuit has continuous voltage output logic state in a partition mode, and an output interface is high in compatibility and easy to adjust.
Drawings
Fig. 1 is a diagram of a power-on state detection circuit according to the present invention.
Detailed Description
The present invention will now be described in further detail with reference to specific examples, which are intended to be illustrative, but not limiting, of the invention.
The invention provides a simple and reliable power-on state detection circuit, which comprises a signal acquisition circuit, a logic state conversion circuit and a driver U6, wherein the signal acquisition circuit is connected with the logic state conversion circuit; the signal acquisition circuit comprises an input interface circuit and a reference circuit, wherein the input interface circuit is connected with a power-on voltage signal V of an external detection pointtestThe input interface circuit is provided with a first resistance unit, and the voltage division network of the first resistance unit acquires an external detection point VtestVoltage of (3) generating corresponding acquisition signal Usap(ii) a The input port of the reference circuit is connected with a 5V voltage-stabilized power supply Vcc5VThe reference circuit is provided with a second resistance unit, and the second resistance unit voltage division network generates a section reference voltage; the reference voltages of the sections are respectively transmitted through a first stageCalculating a unit gain buffer arranged in an amplifier unit and then comparing the unit gain buffer with a collected signal UsapThe internal state signals are input into the logic state conversion circuit to generate logic state signals, and the logic state signals are input into the driver U6 to form low-level effective OC driving signals which can be connected with a power-on state indication or alarm circuit (the logic state signals can also be directly connected with a digital interface acquisition circuit).
The first resistor unit comprises a resistor R1 and a resistor R2, and the resistor R1 and the resistor R2 are connected with a voltage division network to acquire an external detection point VtestVoltage of generating acquisition signal Usap(ii) a The second resistance unit comprises a resistor R3, a resistor R4, a resistor R5 and a resistor R6; voltage-stabilized power supply Vcc5VThe first reference voltage U is generated after the voltage division network of the resistor R3, the resistor R4, the resistor R5 and the resistor R6 respectivelyreaA second reference voltage UrebAnd a third reference voltage Urec。
The first stage operational amplifier unit comprises an operational amplifier U1A, an operational amplifier U2A and an operational amplifier U3A which are respectively designed to be in a unit gain buffer state, and the operational amplifier U1A is used for setting a first reference voltage U1reaThe operational amplifier U2A converts the second reference voltage UrebAnd the operational amplifier U3A applies the third reference voltage UrecThe stable output is sent to a post-stage circuit;
the second stage operational amplifier unit comprises an operational amplifier U1B, an operational amplifier U2B and an operational amplifier U3B, wherein the operational amplifier U1B, the operational amplifier U2B and the operational amplifier U3B work in a signal in-phase comparison state.
The in-phase comparison state of the signals in the invention is as follows,
first reference voltage UreaAfter being stably output by an operational amplifier U1A, the signal U is collectedsapComparing the signals in the operational amplifier U1B to generate a first state signal A;
second reference voltage UrebAfter being stably output by an operational amplifier U2A, the signal U is collectedsapComparing at an operational amplifier U2B to generate a second state signal B;
third reference voltage UrecAfter being stably output by an operational amplifier U3A, the signal U is collectedsapThe comparison is made at operational amplifier U3B to generate a third state signal C.
The logic state conversion circuit comprises a NAND gate U4A, a NAND gate U4B, a NAND gate U4C, a NAND gate U4D, an inverter U5A, an inverter U5B and an inverter U5C, wherein the internal state signal generates a corresponding power-on voltage signal V through a logic state conversion circuit consisting of a NOT gate and the invertertestA logic state signal of a power-up state change.
A voltage regulator tube V1 is arranged on the signal acquisition circuit; collecting signal U generated by voltage regulator tube V1 and input interface circuitsapArranged in parallel for inputting a power-on voltage signal VtestAnd the fault isolation of the over-limit drift plays a role in protecting a rear-stage circuit.
The signal acquisition circuit is provided with a capacitor C1, and the capacitor C1 and an acquisition signal U generated by the input interface circuitsapAnd the parallel connection is used for improving the anti-interference capability of the input interface of the system.
Examples
Firstly, the collection of the actual electricity characteristic voltage parameters of the product is realized by a resistor R1 and a resistor R2 voltage division network. Collecting an electrifying voltage signal VtestVoltage of generating acquisition signal Usap；
Meanwhile, the change trend point of the power-on characteristic voltage parameter is determined according to the design characteristic analysis of the product. The first reference voltage U is generated after the voltage division network is respectively generated through a resistor R3, a resistor R4, a resistor R5 and a resistor R6reaA second reference voltage UrebAnd a third reference voltage UrecThe first stage operational amplifier unit comprises an operational amplifier U1A, an operational amplifier U2A and an operational amplifier U3A which are respectively designed to be in a unit gain buffer state, and the operational amplifier U1A is used for setting a first reference voltage U1reaThe operational amplifier U2A converts the second reference voltage UrebAnd the operational amplifier U3A applies the third reference voltage UrecThe stable output is sent to the post-stage circuit. The second stage operational amplifier unit comprises an operational amplifier U1B, an operational amplifier U2B and an operational amplifier U3B, wherein the operational amplifier U1B, the operational amplifierU2B and operational amplifier U3B work in the signal in-phase comparison state; acquisition signal UsapRespectively connected with a first reference voltage UreaA second reference voltage UrebAnd a third reference voltage UrecGenerating a first state signal A, a second state signal B and a third state signal C after comparison; wherein the first state signal A, the second state signal B and the third state signal C correspond to the power-on voltage signal VtestThreshold voltage U of each sectionA、UBAnd UCAre respectively provided with a first reference voltage UreaA second reference voltage UrebAnd a third reference voltage UrecAnd collecting signal UsapDetermining the attenuation coefficient of, acquiring signal UsapThe signal attenuation coefficient of (2) is R2/(R1+ R2).
Secondly, the actual power-on characteristic voltage parameters of the product and the variation trend of the power-on characteristic voltage parameters are input into a post-stage logic state conversion circuit for processing. The logic state conversion circuit comprises a NAND gate U4A, a NAND gate U4B, a NAND gate U4C, a NAND gate U4D, an inverter U5A, an inverter U5B and an inverter U5C, wherein the first state signal A, the second state signal B and the third state signal C are simultaneously input into the logic state conversion circuit to generate a first bit logic state signal K1 ', a second bit logic state signal K2' and a third bit logic state signal K3 ', wherein the first logic state signal K1', the second logic state signal K2 'and the third logic state signal K3' correspond to the power-on voltage signal V3testThe voltage change trend in the power-on state is realized, and the state maintaining function is realized.
Finally, the first bit logic state signal K1 ', the second bit logic state signal K2 ' and the third bit logic state signal K3 ' are all amplified by the output interface of the driver U6, so as to obtain driving signals for the actuator; the driver U6 converts the first bit logic state signal K1 ', the second bit logic state signal K2 ' and the third bit logic state signal K3 ' into the first bit active low OC signal K1, the second bit active low OC signal K2 and the third bit active low OC signal K3, which facilitates connection of status indication circuits such as leds. Voltage signal V on detected end signaltestIn relation to the design of the output signalIs shown in table 1 below.
TABLE 1 Voltage supply signal VtestDesign relation table with output signal
| Status of state | Vtest | K1 | K2 | K3 |
| 1 | Vtest≤UC | 1 | 1 | 1 |
| 2 | UC＜Vtest≤UB | 0 | 1 | 1 |
| 3 | UB＜Vtest≤UA | 0 | 0 | 1 |
| 4 | Vtest＞UA | 0 | 0 | 0 |
In the invention, signal definition and acquisition:
acquisition signal Usap: upper voltage signal VtestThe sampling point (signal attenuation coefficient: R2/(R1+ R2));
first reference voltage Urea: upper voltage signal VtestThe signal changes to the threshold voltage UAComparing the time with a reference, and outputting a first state signal A after comparison;
second reference voltage Ureb: upper voltage signal VtestThe signal changes to the threshold voltage UBComparing the time with a reference, and outputting a second state signal B after comparison;
third reference voltage Urec: upper voltage signal VtestThe signal changes to the threshold voltage UCAnd comparing the time reference to output a third state signal C.
In the logic state conversion circuit of the invention VtestThe logical truth table analysis of physical state changes versus output states is as follows (note:
as well as K1 ', K2 ', K3 ');
TABLE 2VtestLogical truth table of physical state change and output state
The three status signals A, B, C correspond to a total of 8 binary status combinations, combined with the power-on voltage signal V designed in Table 1testThe four consecutive operating states of (1) are listed as four associated with the logic state signal bits K1 ', K2 ', K3 ' (i.e. three non-logic quantities corresponding to K1, K2, K3, respectively)The valid corresponding combinations with consecutive bit number holds are stripped of the invalid corresponding combinations, as described in table 2 above.
The logic state conversion circuit of the present invention utilizes a Carnot diagram to resolve a logic truth table, such as the first bit logic state signal of Table 3
Carnot diagram, table 4 second bit second logic state signal
Carnot diagram of (c) and table 5 third bit logic state signal
(ii) analysis of the carnot diagram;
TABLE 3 first bit logic State signals
Carnot diagram of
TABLE 4 second bit logic State signals
Carnot diagram of
TABLE 5 third logic State signals
Carnot diagram of
The logic function expressions of the first bit logic state signal K1 ', the second bit logic state signal K2 ' and the third bit logic state signal K3 ' are solved through table 3, table 4 and table 5, respectively:
and converting the solved logic function expression into a logic circuit diagram, designing 3 NAND gates U4A, U4C, U4D and 1 not gate U5C logic circuits according to K1 ' logic function expression to realize the logic circuit, designing 1 NAND gate U4A and 1 not gate U5A logic circuits according to K2 ' logic function expression to realize the logic circuit, designing 2 NAND gates U4A, U4B and 2 not gates U5A and U5B circuits according to K3 ' logic function expression to realize the logic state conversion circuit part design by 4 NAND gates U4A, U4B, U4C, U4D and 3 not gates U5A, U5B and U5C through logic circuit multiplexing.
Claims (8)
1. A simple and reliable power-on state detection circuit is characterized by comprising a signal acquisition circuit, a logic state conversion circuit and a driver U6; the signal acquisition circuit comprises an input interface circuit and a reference circuit, wherein the input interface circuit is connected with a power-on voltage signal V of an external detection pointtestThe input interface circuit is provided with a first resistance unit, and the voltage division network of the first resistance unit acquires an external detection point VtestVoltage of (3) generating corresponding acquisition signal Usap(ii) a The input port of the reference circuit is connected with a 5V voltage-stabilized power supply Vcc5VThe reference circuit is provided with a second resistance unit, and the second resistance unit voltage division network generates a section reference voltage; the reference voltage of the section respectively passes through a unit gain buffer arranged in the first-stage operational amplifier unit and then is connected with the acquisition signal UsapThe internal state signals are input into the logic state conversion circuit to generate logic state signals, and the logic state signals are input into a driver U6 to form low-level effective OC driving signals which are used for connecting a power-on state indicating or alarming circuit and a direct butt joint digital interface acquisition circuit.
2. The simple and reliable power-on state detection circuit as claimed in claim 1, wherein the first resistor unit comprises a resistor R1 and a resistor R2, and the resistor R1 and the resistor R2 divide the voltage network to collect the external detection point VtestVoltage of generating acquisition signal Usap(ii) a The second resistance unit comprises a resistor R3, a resistor R4, a resistor R5 and a resistor R6; voltage-stabilized power supply Vcc5VThe first reference voltage U is generated after the voltage division network of the resistor R3, the resistor R4, the resistor R5 and the resistor R6 respectivelyreaA second reference voltage UrebAnd a third reference voltage Urec。
3. A simple and reliable power-on state detection circuit according to claim 2, characterized in that the acquisition signal U issapThe signal attenuation coefficient of (2) is R2/(R1+ R2).
4. The simple and reliable power-on state detection circuit as claimed in claim 2, wherein the first stage operational amplifier unit comprises an operational amplifier U1A, an operational amplifier U2A and an operational amplifier U3A, wherein the operational amplifier U1A, the operational amplifier U2A and the operational amplifier U3A are respectively designed to be in a unity gain buffer state, and the operational amplifier U1A is used for providing the first reference voltage U1AreaThe stable output is sent to a post-stage circuit; the operational amplifier U2A converts the second reference voltage UrebThe stable output is sent to a post-stage circuit; the operational amplifier U3A converts the third reference voltage UrecThe stable output is sent to a post-stage circuit;
the second stage operational amplifier unit comprises an operational amplifier U1B, an operational amplifier U2B and an operational amplifier U3B, wherein the operational amplifier U1B, the operational amplifier U2B and the operational amplifier U3B work in a signal in-phase comparison state.
5. A simple and reliable power-on state detection circuit according to claim 4, wherein the signal in-phase comparison state is as follows,
first reference voltage UreaAfter being stably output by an operational amplifier U1A, the signal U is collectedsapComparing the signals in the operational amplifier U1B to generate a first state signal A;
second reference voltage UrebAfter being stably output by an operational amplifier U2A, the signal U is collectedsapComparing at an operational amplifier U2B to generate a second state signal B;
third reference voltage UrecAfter being stably output by an operational amplifier U3A, the signal U is collectedsapThe comparison is made at operational amplifier U3B to generate a third state signal C.
6. The simple and reliable power-on state detection circuit as claimed in claim 1, wherein the logic state transition circuit comprises nand gate U4A, nand gate U4B, nand gate U4C, nand gate U4D and inverter U5A, inverter U5B and inverter U5C, and the internal state signal generates the corresponding power-on voltage signal V through the logic state transition circuit comprising not gate and invertertestA logic state signal of a power-up state change.
7. The simple and reliable power-on state detection circuit according to claim 1, wherein a voltage regulator tube V1 is arranged on the signal acquisition circuit; collecting signal U generated by voltage regulator tube V1 and input interface circuitsapArranged in parallel for inputting a power-on voltage signal VtestAnd the fault isolation of the over-limit drift plays a role in protecting a rear-stage circuit.
8. The simple and reliable power-on state detection circuit as claimed in claim 1, wherein a capacitor C1 is provided on the signal acquisition circuit, and the capacitor C1 is connected to the inputAcquisition signal U generated by port circuitsapAnd the parallel connection is used for improving the anti-interference capability of the input interface of the system.
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Cited By (1)
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| CN116436446A (en) * | 2023-06-12 | 2023-07-14 | 深圳市赛元微电子股份有限公司 | Integrated circuit logic failure monitoring circuit and isolation circuit |
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