CN100428248C - Carry generating circuit for CMOS power-consumption balance delay-sensitive less adder - Google Patents

Carry generating circuit for CMOS power-consumption balance delay-sensitive less adder Download PDF

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CN100428248C
CN100428248C CN 200410101820 CN200410101820A CN100428248C CN 100428248 C CN100428248 C CN 100428248C CN 200410101820 CN200410101820 CN 200410101820 CN 200410101820 A CN200410101820 A CN 200410101820A CN 100428248 C CN100428248 C CN 100428248C
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carry
tube
drain
signal
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CN1641649A (en )
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孙义和
李翔宇
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清华大学
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CMOS功耗平衡延时不敏感超前进位加法器用的进位产生电路和进位控制的进位产生电路属于密码芯片设计中的抗功耗分析工具领域,进位产生电路的特征在于:它含有一对交叉耦合的PMOS管,其漏极作为输出端;一对由时钟信号控制的PMOS管作充电开关;一对由时钟信号控制的NMOS管作放电开关;在放电开关和地之间有一个求值网络,它含有进位消除、进位传递、进位产生、输入信号控制的管子及相应的平衡管、复位管,共同构成一个动态差分求值电路,以保证得到一个对称的充放电结构。 CMOS power balance delay insensitive ultra carry lookahead adder Used for generating a carry circuit and a carry control generating circuits belonging to the anti-power field analysis tool cryptographic chip design, wherein the carry generation circuit in that: it comprises a pair of cross coupled the PMOS transistor, its drain as an output terminal; a pair of control by a clock signal for charge switch PMOS transistor; a pair of control by a clock signal for discharging switch NMOS transistor; between the discharge switch and the network has a request value, it contains eliminate carry, carry propagation, carry generation, and the corresponding tubes balanced input signal control tube, the return pipe, together constitute a differential dynamic evaluation circuit, which guarantees a symmetrical charge and discharge structure. 本发明从而构成一个动态交叉耦合差分电路。 The present invention thus constituting a dynamic cross-coupled differential circuit. 用本发明电路制作的功耗平衡加法器与一般加法器相比,其功率信号的信噪比升高了9倍。 Compared with the circuit of the present invention made with the general power balance adder adder, which increases the power signal to noise ratio of 9 times.

Description

CMOS功耗平衡延时不敏感加法器用的进位产生电路 CMOS delay insensitive power balance Used adder carry generating circuit

技术领域 FIELD

本发明属于密码芯片设计中的抗功耗分析攻击领域。 The present invention belongs to the field analysis attack power anti cryptographic chip design. 背景技术 Background technique

1999年,Kocher,P.首次提出了通过功耗分析攻击密码芯片的办法。 In 1999, Kocher, P. For the first time suggested a way out by power analysis attack code chip. 这种办法就是利用集成电路芯片处理不同数据所产生的功耗曲线不同,透过芯片瞬态功耗变化的差别提取芯片内部密钥信息的攻击方法。 This approach is the use of an integrated circuit chip to handle different power curves generated by the different data through the chip attack transient power change in the difference extract the key information inside the chip. 使电路计算不同数据时的功耗差异非常小——即功耗平衡——是抵抗功耗分析的一种根本途径。 Differences in the power consumption of the circuit is calculated different data is very small - i.e. power balance - a fundamental way to resist power analysis. 在Simon Moore 1999年的论文"Balanced Self-Checking Asynchronous Logic for Smart Card Applications,,(《用于智能卡的平衡自检査异步逻辑》)中首先提到了采用双轨编码的DI (Delay-Insensitive,延时不敏感)电路可以达到平衡功耗的效果。文中给出了由基本逻辑门搭成的DI逻辑门。 Simon Moore in the 1999 paper "Balanced Self-Checking Asynchronous Logic for Smart Card Applications ,, (" smart card for the balance of self-checking asynchronous logic ") was first mentioned in the DI (Delay-Insensitive, using dual-rail encoding delay insensitive) circuit can achieve power balance. paper presents the cairn of basic logic gates logic gates DI.

"Fu-Chiang, Cheng, Unger, SH, Theobald, M., and Wen-Chung, Cho,"Delay-insensitive carry-lookahead adders"(《延时不敏感超前进位加法器》),Proceedings. Tenth International Conference on VLSI Design (Cat. No.97TB100095),IEEE Comput. Soc. Press,322-328,Hyderabad, India,1997"—文描述了一种快速的DI超前进位加法器(简记为DICLA),适用于一般领域,不具有功耗平衡的特性。 "Fu-Chiang, Cheng, Unger, SH, Theobald, M., and Wen-Chung, Cho," Delay-insensitive carry-lookahead adders "(" delay insensitive lookahead adder "), Proceedings. Tenth International .. Conference on VLSI Design (. Cat No.97TB100095), IEEE Comput Soc Press, 322-328, Hyderabad, India, 1997 "- described a fast DI lookahead adder (abbreviated as DICLA), generally applicable to the field, it does not have a balance of power consumption characteristics. 其电路结构如图1 (8位加法器)。 The circuit structure shown in Figure 1 (8-bit adder). A,B是输入的加数,C0是进位输入,S是和,C8是进位输出,C1一C7分别表示各位的内部进位信号,上述信号均采用双轨编码(参见附录"双轨编码与DI电路"),即每比特用两个信号表示,所以A的第i位Ai-l对应Ai^0, A?-l, Ai-0对应于AiQ=l, A?-0, B 的第i位Bj用BiGB卩两个信号表示,类似的,C?Ci1, S^S?表示Ci和S的第i位。 A, B is an addend input, C0 is the carry input, S is and, C8 is a carry output, a C1 a C7 respectively for your internal carry signal, the signal are two-track code (see Appendix "dual-rail encoding to DI circuit" ), i.e., each bit represents two signals, so the first bit Ai-l a i corresponding to Ai ^ 0, a? -l, Ai-0 corresponds to AiQ = l, a? -0, the i-th bit Bj B BiGB two signals represented by Jie, similar, C? Ci1, S ^ S? i represents the position Ci and S.

超前进位加法器的工作原理: Ultra works ahead adder of:

对于(第i位),和的第i位S产Aj6Bi④Ci。 For the (i-th bit), and the i-th bit S produced Aj6Bi④Ci. '第i位对髙位(第i+l位)的进位Cw取值分三种情况: 'I-th bit carry value of Cw Gao bit (bit i + l) of three cases:

若AiB产"U",贝iJCw-l,这种情况我们称为进位产生(carrygenerate); If AiB yield "U", Tony iJCw-l, which we referred to as the carry generation (carrygenerate);

若A3产"00",则Cw-0,这种情况我们称为进位消除(carrykill); If A3 production, "00", the Cw-0, in which case we called carry eliminate (carrykill);

若Ai和Bi不同,则Ci+,《i,这种情况我们称为进位传递(carrypass〉。 If Ai and Bi are different, Ci +, "i, which we referred to as a carry propagation (carrypass>.

加法的关键路径是进位从低位到高位的逐级传递,根据前面分析,如果加数的某一位相同,则不必等待低位的进位信号(Ci)就可以得到本级的进位(Ci+1)。 Critical path addition is from low to high stepwise transfer, according to the above analysis, if the addend bit in a same binary, it is not necessary to wait for the lower carry signal (Ci) can be obtained according to the present stage of carry (Ci + 1) . 超前进位加法器就是利用这点来提高运算速度。 Lookahead adder is to use this point to improve the operation speed. 用gi,pi信号分别标识进位产生、进位传递两种情况,即& By gi, pi carry identification signals generated carry propagation in both cases, i.e., &

忠符号表示异或运算为高表示进位产生,Pi为高表示进位传递。 Zhong symbols represent exclusive-OR operation is represented by a high carry generation, Pi represents a carry propagation is high.

则有如下公式:<formula>formula see original document page 5</formula>上式中将与Ci.k.,无关的项合并为两个变量Gu.k.!和Pi,ik!, Gi,iw由gi〜gi.k和pi〜p"得出, Then the following equation: <formula> formula see original document page 5 </ formula> in the above formula and Ci.k., consolidated into two independent variables Gu.k. items and Pi, ik !, Gi, iw! "derived from gi~gi.k and pi~p,

Pi,ik"由Pi〜Pi-k得出。此式说明任意两位的进位之间可以通过局部的G和P信号建立函数关系。 为了叙述方便,我们把一组G/P信号合称为进位控制信号,记为I。例如,Gi,ik,, Pi,k.,记为<formula>formula see original document page 5</formula> Pi, ik "derived from Pi~Pi-k. This formula can be established functional relationship described by localized P G, and carry signals between any two bits. For convenience, we have a set of G / P signal are collectively referred to carry control signals, denoted as I. For example, Gi, ik ,, Pi, k., referred to as <formula> formula see original document page 5 </ formula>

文献中提到的DICLA的超前进位链是一种树状结构(由图1中的8个D单元组成), 就是利用上述关系按段计算进位。 Chain is a lookahead tree DICLA mentioned literature (in FIG. 1 consists of eight D units) is calculated according to the carry section by using the above relationship. 在树根部的D单元由Co产生Cg,其输入的进位控制信号是17,0;根D单元的孩子(即它的上一级D单元)由Co产生C4,同时由17,4和Iw产生I7,o; 这个节点的左孩子由Ct产生C7,右孩子由Q产生C3,......最上面一级D单元分别完成 D units root portion produced by Co Cg, the carry control signal at its input is 17,0; children (i.e. on one of its D units) root D units derived from the C4 Co, and Iw is generated simultaneously from 17,4 I7, o; the left child node is generated by the C7 Ct, generated by the right child Q C3, ......, respectively, a top unit D is completed

Co-d,C2-C3,C4-Cs,C5 — C6, C6-C7的计箅,它们各自的进位控制信号就是对应高位的g/p信 Co-d, C2-C3, C4-Cs, C5 - C6, C6-C7 meter grate, each of which carry a control signal is high corresponding to the g / p channel

号。 number. 同时这些单元又产生进位控制信号送给它们的父节点。 While the control unit in turn generates a carry signal to their parent node. 在DICLA中增加一个表示仅为消除的信号K,则对于某个D单元,假设其由Ck产生Cj,完成的计算有两部分,分别是计算进位控制信号,如式(l)-(3);计算进位,如式(4) In DICLA increase represents only a cancellation signal K, the unit D for some, it is assumed that generates a Cj Ck, calculation is complete has two parts, namely the carry control signal is calculated as shown in formula (l) - (3) ; calculated carry as formula (4)

<formula>formula see original document page 5</formula> <Formula> formula see original document page 5 </ formula>

在实际电路实现中,采用双轨编码,对每一个信号分别计算,上述的第4式改写为: <formula>formula see original document page 5</formula> (6) In a practical circuit implementation, using dual-rail encoding, were calculated for each signal, said fourth formula is rewritten as: <formula> formula see original document page 5 </ formula> (6)

C单元包含求和和计算本位的进位控制信号两个功能,实际的逻辑表达式如下: 进位控制信号产生: C summation unit comprises a carry signal and calculating two standard control functions, the actual logical expressions as follows: a control signal generating carry:

<formula>formula see original document page 5</formula>求和:<formula>formula see original document page 5</formula>Si1 = Aj'Bi1 C?+A^Bi0 Ci0+Ai0 B卩Cj。 <Formula> formula see original document page 5 </ formula> sum: <formula> formula see original document page 5 </ formula> Si1 = Aj'Bi1 C + A ^ Bi0 Ci0 + Ai0 B Jie Cj?. 十Ai0^0 C人(11) Ten people Ai0 ^ 0 C (11)

我们对DICLA进行了改动,实现了一个具有功耗平衡性质的加法器单元。 We DICLA made changes to achieve a power consumption of the adder unit having a balance of properties. 在"Power-balanced delay-insensitive carry-lookahead adders (《功耗平衡的延时不敏感超前进位加'法器》),Xiangyu Li; Yihe San;ASIC, 2003. Proceedings. 5th International Conference, Volume: 2,21-24 Oct. 2003, Pages:1289 - 1292"—文中公布了加法器的结构如图5,并公布了部分基本单元的CMOS实现作为示例以说明DI功耗平衡逻辑。 In the "Power-balanced delay-insensitive carry-lookahead adders (" balanced power lookahead delay insensitive plus "adder"), Xiangyu Li; Yihe San; ASIC, 2003. Proceedings 5th International Conference, Volume:. 2,21-24 Oct. 2003, Pages: 1289 - 1292 "- published paper structure adder 5, and published CMOS implemented as part of the basic unit of an example to illustrate DI power balancing logic.

为了说明PBDICLA的结构,我们首先对DICLA的工作时序进行分析: 分析前我们定义关键信号:对一个运算模块,如果有多个输入数据,每个输入到达的时间可能不同,必须等待所有数据都到达它才能开始计算。 To illustrate the structure PBDICLA, we first work on the timing of DICLA analysis: analysis before we define the key signal: operation of a module, if there are multiple input data, each input arrival time may be different, we must wait for all the data arrives it can be counted. 定义最晚到达的信号为关键信号。 The latest arriving signal is defined as a critical signal. 一个运算模块工作的时刻是由关键信号的到达时刻决定的。 A time calculation module is determined by the working key signal arrival time.

则由图l和式(l)一式(ll)定义的数据依赖关系知:1o — l7的关键信号是加数A, B; (LL) defined by formula a and formula Figure l (l) known data dependencies: 1o - it is critical signals l7 addend A, B;

对于D单元的进位控制信号产生电路的关键信号是Iij和Ij-uc。 The key for the carry signal of the D control signal generation circuit means is Iij and Ij-uc. 对于产生C,、 C2、 Q的D 单元中的进位产生电路,因为它的进位输入总是先有效,所以关键信号是进位控制信号。 For the production of C ,, C2, D units carry generating circuit of Q, because its input is always to carry valid, so the key signal is a binary control signal. 其他D单元中的进位产生电路的关键信号则与进位控制信号的取值有关。 Other key D units carry signal generating circuit is related to the value of the carry control signal. 如果KRk或G ju 为l,则不用等待Ck,关键信号是Ij.u;如果是Pj.Uc尸l,则要等待Ck,进位输入是关键信号。 If KRk or G ju is l, the without waiting Ck, the key signal is Ij.u; if Pj.Uc dead l, will have to wait Ck, the key input is a carry signal.

以8位加法器为例,考虑两种极端情况的时序: 8-bit adder as an example, consider the timing of the two extremes:

A. 两个输入完全相同的情况:对每个D模块当算出Ij-uc (Pj-uKHk,Gj.u),后就可以得出Cj(C/,Cj1),则可列出如图2的计箅顺序。 A. Enter identical two cases: when the module is calculated for each of the D Ij-uc (Pj-uKHk, Gj.u), can be derived after Cj (C /, Cj1), may be listed as shown in FIG 2 the grate meter order. 图2中每列代表一个工作步,从左到右按时间顺序标为1〜5,每列列出了在这一个工作步里求值的信号,同一列的信号是同时产生的,各个工作步的功耗就是该工作步求值的数据所消耗的功耗的叠加。 In FIG. 2 and each column represents a working step, in chronological order from left to right labeled ~ 5, each column lists the signal evaluated in this work step, the same column signal are produced simultaneously, each work power step is the data of the working step of evaluating the power consumed by the stack. 对于双轨编码,数据产生就意味着一根信号线的翻转,所以只要每个时间步内产生的信号是固定的,且每个信号产生的功耗不随数据不同而不同就可以保证功耗平衡。 For the dual-rail encoding, a data generating means inverting the signal line, so long as a signal in each time step is fixed, and the power consumption of each signal with the data generated does not differ power balance can be ensured.

B. 再考虑两个加数各位均相反的情况。 B. Consider two addends and then you have the opposite situation. 这时每个进位信号的产生必须在D模块的输入进位到达后产生。 Generating each time the carry signal must be generated when the carry input reaches D module. 则信号产生的顺序就如图3: On the order of the signals generated in Figure 3:

上面给出了两种极端情况,各个信号翻转发生的时刻就在这两种极端情况所给出的边界之间变化。 Two extreme cases given above, the boundary in time between the change in each signal inversion occurs in these two extremes given. 显然,若进位控制信号、进位信号的翻转功耗和数据无关,在任何情况下, 图2-图3中粗体部分的功耗总是一样的,当考虑功耗对输入的差分时,只需考虑各工作步中引起功耗变化的部分——图中斜体部分所示(由上面两个图可知,Cj一Sj总是作为整体在图中出现,因此我们下面仅考察C信号的产生时刻分布情况。) Obviously, if the carry control signal, the inverted carry signal and power independent of the data, in any case, the power consumption in bold in FIG. 2 to FIG. 3 is always the same, when considering the power consumption of the differential inputs, only should be considered part of the power consumption due to changes in the working step - as shown in the drawing taper portion (seen from the above two graphs, a Cj of Sj always appear in the figures as a whole, so we investigated the following signal is generated only time C Distribution.)

由图2-图3,因为进位控制信号的产生时刻是固定的,而d、 C2、 Q的关键信号是进位控制信号,所以它们的产生时刻是固定的。 Of Figures 2-3, since the carry generating timing control signals is fixed, and d, C2, Q bits into the key signal is a control signal, the generation timing thereof is fixed. 为了使图中左子树的进位产生电路也以进位 In order to carry FIG left subtree also carry generating circuit

控制信号为关键信号,采用"进位选择"结构。 The control signal is a key signal, a "carry select" structure. 即将C5《7的产生电路变成相同的两个,分别计算C4输入"o"和"r,时的各进位信号,产生的进位信号经C4选择送到c单元,计算Ss〜S7。 Coming C5 "generating circuit 7 becomes the same two inputs are calculated C4 'each carry signal o" and "R & lt, when the carry signal generated through C4 to c selection unit, calculates Ss~S7.

由于对两组C5C6产生电路都是进位输入先于进位控制信号有效,所以它们的进位控制 Because two groups are C5C6 generation circuit prior to the carry input bits into a control signal effective, they carry control

信号就成为了关键信号而不再受进位控制信号取值的影响。 Signal has become a key signal without affecting longer carry the value of the control signal. 实现了进位产生时序固定。 Achieved carry generation timing is fixed. 为了实现所有进位产生电路的关进信号都是进位控制信号,我们可以在每个节点的左 In order to achieve all the carry signal generating circuit is put into the carry control signal, we left on each node

子树计算采用进位选择结构,这样就形成了一个多层进位选择递归的结构。 Subtree calculated using the carry select structure, thus forming a multilayer structure carry select recursion.

因为左右子树2的进位输出都是早于1信号有效的,又左、右子树的级数相同,所以右 Because the left and right subtrees into 2-bit output signal are active earlier than 1, and the left and right subtree of the same series, so that the right

子树的进位送入根节点的同时左子树的进位链也刚好计算完。 Carry Carry Chain subtree root into the left subtree is also calculated just finished. 根节点的输出进位产生后, After the root node output carry generation,

再作为选择信号,把正确的进位结果送到相应的c模块,计算该位的和。 Then as the selection signal, the correct result to carry respective module c, and calculates the bit.

显然,在这样的结构中C3, C7也应该采用进位选择结构,但是这样会带来面积的大幅 Obviously, in such a structure C3, C7 also carry select architecture should be used, but it will bring a significant area

增加,如图3所示,C3最晚产生在第4步,而加法器最快的情况也需要5步完成所有进位 Increase, shown in Figure 3, C3 latest generated in step 4, the adder 5 also require the fastest case carry complete all steps

的计算,所以,我们可以通过改变进位产生电路的方法强制C3的关键信号为C2,这样,它 The method of calculation, therefore, we can generate a carry circuit by varying the key signal is forced C3 C2, such that it

就固定在第4步产生,只相对最好情况增加了一个工作步,而不增加很多电路。 4 is fixed in the generating step, only a relative increase in the best case a working step, without increasing a number of circuits. 类似的, C7也要等到C6有效后再计箅。 Similar, C7 C6 effectively have to wait until after the meter grate. 这样的单元称为进位控制单元记作Dc。 Such a unit is called the carry controlling unit referred to as Dc.

综合以上方案,PBDICLA最终采用了图5所示的结构,图中的MUX表示多路选择器, C单元和D单元实现了与DICLA中相同的功能,Dc单元实现的功能与D单元相似,其中也有一个进位控制信号产生电路(与D单元的相同),还有一个进位控制的进位产生电路, 记为CGc。 Based on the above scheme, PBDICLA finally adopted a configuration shown in Figure 5, the figure represents a multiplexer MUX, C, and D means a unit implements the same function DICLA, the functional unit D and Dc implemented similar unit, wherein also carry a control signal generation circuit (D units of the same), there is a control bit into the carry generation circuit, referred to as CGc. 逻辑功能如下- Logic functions are as follows -

Cj、Kj.Lk(CkO+(V)+Pw,kCk0 (12) Cj, Kj.Lk (CkO + (V) + Pw, kCk0 (12)

C—Gj-Lk(CkO+CkVPw,kCk1. (13) C-Gj-Lk (CkO + CkVPw, kCk1. (13)

也就是必须在Ck有效后,才计算Cj。 That is, to be effective after Ck, was calculated Cj.

PBDICLA最终的运算顺序图如图6: PBDICLA final operation sequence shown in Figure 6:

其中进位信号的脚标"0"或"1"分别表示按C4取"O"和'T'时得到的结果,无脚标的表示最终经过选择得到的实际进位信号。 Wherein the subscript carry signal "0" or "1" respectively represent the results obtained when taking "O" and 'T' by C4, no subscript is the carry signal representing the actual chosen finally obtained. 新结构的运算顺序是不随数据变化的,需要6个工作步完成。 The new sequence of operations with the data structure is not changed, the work requires six steps to complete. 从而整体的功耗也是不随数据变化的。 Thus the overall power consumption is not with the data change.

发明内容 SUMMARY

本发明是上述8位的CMOS功耗平衡延时不敏感(DI)加法器(Power-Balanced The present invention provides the balance of power CMOS 8-bit delay insensitive (DI) of the adder (Power-Balanced

进位产生电路: Carry generating circuit:

本发明所述的进位产生电路,其特征在于:它是一种N型求值网络的动态交叉耦合差分电路,它含有: Carry generating circuit according to the present invention, which is characterized in that: it is an N-type evaluation of the dynamic cross-coupled differential network circuits, comprising:

—对交叉耦合的PMOS管用Ml、 M2表示,它们的源端接电源,栅极分别接到对 - Ml tube of cross-coupled PMOS, M2 said power source end thereof, to the gates of

以某个节点的左(右)孩子节点为根的子树定义为这个节点的左(右)子树.方的漏极,它们的漏极同时也是本方的输出端,依次分别输出用双轨编码表示的进位信号C/, C/的反信号巧,巧,反信号巧,巧再依次分别经反相器后输出进位信号CjG, Cj'; A node of the left (right) child node is defined as a subtree rooted at the left (right) subtree of this node. The drain side, but also their drain output of this side, are successively output two-track C represents a carry signal of the encoding /, C / inverted signal Qiao, Qiao, Qiao inverted signal, respectively, after skillfully in turn outputs a carry signal of the inverter CjG, Cj ';

两个分别由同一时钟信号4>控制的PMOS管,用PM1、 PM2表示,它们的源极接电源,栅极接上述时钟信号4),它们是上述动态交叉耦合差分电路,即DCCD电路的 Two are from the same clock signal 4> controlled PMOS transistor, with PM1, PM2 expressed, their sources connected to the power supply, a gate connected to the clock signal 4), which are the moving cross-coupled differential circuit, i.e. the circuit DCCD

充电开关; A charging switch;

两个由上述时钟信号4>控制的NMOS管,用NM1、 NM2表示,它们的漏极依次分别和上述充电开关PM1、 PM2的漏极相连后再和上述交叉耦合管Ml、 M2的漏极相连,这两个NM0S管NM1、 NM2是上述动态交叉耦合差分电路的放电开关; Clock signal by the two 4> control NMOS transistor, with NM1, NM2 expressed, their drain and said charge switch PMl, PM2 of the drain pipe and said cross-coupling of Ml, M2 are connected to the drain respectively connected sequentially after , these two tubes NM0S NM1, NM2 is the moving cross-coupled differential circuit discharge switch;

八个它们的栅极依次分别受信号KKk、 Pj.u、 Gj.u、 Gj.!,k、 PRk、 Kj.u、输入进位信号CkQ 、 (V控制的NMOS管,他们依次分别用NMJd,NMp,,NMg,, NMk2,NMp2,NMg2,NMco,NMd管表示,其中,Ky,k是加法器的进位链中第k位到第j-1 位的进位消除信号,Pj.u是加法器的进位链中第k位到第jl位的进位传递信号,Gj.u 是加法器的进位链中第k位到第j-1位的进位产生信号; Eight their gates respectively receiving signals sequentially KKk, Pj.u, Gj.u, Gj.!, K, PRk, Kj.u, the input carry signal CkQ, (V control NMOS transistor, they are sequentially with NMJd, NMp ,, NMg ,, NMk2, NMp2, NMg2, NMco, nMd tube, where, Ky, k is the carry chain adders k-th bit to the j-1 th bit of the cancellation signal, Pj.u adder carry chain bit to the k-th jl bit of the transfer signal, Gj.u adder carry chain is the k-th bit to the j-1 th bit carry generation signal;

平衡用的NMOS管,用NMb表示,它是一种要得到对称的充放电结构而在求值时导通的平衡管,它的栅极接上述的时钟信号4>,它的漏极同时与上述NMld管、NMg2 管的源极相连,它的源极接地; Balancing the NMOS transistor, represented by NMb, which is a charge-discharge to obtain a symmetrical structure when evaluated balancing pipe conductive, its gate connected to the above-described clock signal 4>, and its drain while above NMld tube, source tube NMg2 electrode connected to its source electrode grounded;

共四个它们的栅极都受上述时钟信号4»的反信号^控制的复位管依次分别用Mpl、 Mp2、 Mp3、 Mp4表示,在上述动态交叉耦合差分电路的初态这些管子导通,把内部上述八个NMk,、 NMPl、 NMgb NMk2,NMp2,NMg2,NMco,NMc! An inverted signal thereof a total of four gates are subject to the clock signal 4 »^ control the return pipe respectively successively Mpl, Mp2, Mp3, Mp4 said initial state in the above-described dynamic cross-coupled differential circuit conducting tubes, the the inside of the eight NMk ,, NMPl, NMgb NMk2, NMp2, NMg2, NMco, NMc! 管子的漏极置0;其中, Mpl的漏极同时接NMk!、 NMPl、 NMg,管的漏极和NM1管的源极,Mp2管的漏极同时接NMg2、 NMp2、 NMk2管的漏极和NM2管的源极,Mp4、 Mp3管的漏极依次分别同时接NMp2管的源极和NMc,管的漏极、NN^管的源极和NMco管的漏极,Mpl、 Mp2、 Mp3、 Mp4管的源极共同接地; 0 opposing the drain pipe; wherein, while the Mpl a drain connected to the source NMk !, NMPl, NMg, the drain tube and NM1 tube, a drain tube Mp2 NMG2 simultaneous access, the drain NMp2, NMk2 tube and NM2 source transistor is the drain, Mp4, Mp3 drain tube are simultaneously connected sequentially NMp2 source and NMC tube, a drain tube, source tube, and NN ^ NMco tube, Mpl, Mp2, Mp3, Mp4 common source transistor is grounded;

栅极受上述时钟信号4>的反信号^控制的用M-表示的NMOS管,它在求值时截止以便得到对称的充放电结构,该N^管的漏极同时连接NMg!、 NMk2的源极,而N^管的源极接地。 A gate receiving an inverted signal of the clock signal 4> M- ^ NMOS control represented by a tube, which is turned off when evaluated so as to obtain a symmetrical charge and discharge structure, the drain electrode of the N ^ pipe connecting the NMg !, NMk2 source, and the source is grounded N ^ tube.

3.本发明所述的进位控制的进位产生电路,其特征在于:它是一种进位控制的进位产生电路,即它的进位产生部分必须在用双轨表示的输入进位信号Ck有效,即(V5, (V有一个为1后才开始计算用双轨编码表示的输出进位信号Cj;所述的进位产生电路是一种N型求值网络的动态交叉耦合差分电路,它含有: Carry control carry claim 3. The present invention generating circuit, characterized in that: it is a carry control carry generating circuit that its carry generating section must be valid at the input carry signal Ck with the two-track indicated, i.e., (V5 , (V 1 after the start of a calculation of the output carry signal Cj by dual-rail encoded representation; the carry generating circuit is an N-type evaluation of the dynamic cross-coupled differential network circuits, comprising:

一对交叉耦合的PMOS管,用CM1、 CM2表示,它们的源端接电源,各自的栅极 A pair of cross-coupled PMOS transistor, with the CM1, CM2, said power source end thereof, respective gate

分别接到对方的漏极,它们的漏,同时也是本方的输出端,依次分别输出用双轨编码表示的进位信号CjO, C/的反信号巧,巧,反信号再依次分别经反相器后输出进位信号C/,两个分别由同一时钟信号4)控制的PMOS管,用PM1、 PM2表示,它们的源极接电源,栅极接上述时钟信号(D,它们是上述动态交叉耦合差分电路,即DCCD电路的 A drain respectively connected to each other, their drains, but also the side of the output terminal, respectively, are sequentially outputs a carry signal of the dual-rail encoded representation CjO, C / inverted signal Qiao, Qiao, in turn, respectively, the inverted signal via an inverter the output carry signal C /, respectively, two) controlled by the same clock signal 4 PMOS tube, with PM1, PM2 expressed, their sources connected to the power supply, a gate connected to the clock signal (D, which are the moving cross-coupled differential circuit, i.e. the circuit DCCD

充电开关; A charging switch;

两个由上述时钟信号4>控制的NMOS管,用NM1、 NM2表示,它们的漏极依次分别和上述充电开关PM1、 PM2的漏极相连后再和上述交叉耦合管CM1、 CM2的漏极相连,这两个NMOS管NMl、 NM2是上述动态交叉耦合差分电路的放电开关; Clock signal by the two 4> control NMOS transistor, with NM1, NM2 expressed, their drain and said charge switch PMl, PM2 of the drain pipe and said cross-coupling the CM1, CM2 is connected to the drain respectively connected sequentially after these two NMOS transistors NMl, NM2 is a discharge switch the moving cross-coupled differential circuit;

共八个它们的栅极依次分别受信号Ck1、 Ck1、 CkQ、 CkQ、 (V、 (V、 Cj、 C?控制的NMOS管依次分别用Mc卜Ml、 M2、 M4、 M5、 McQ、 M7、 M8表示; Eight co their gates are sequentially receiving signal Ck1, Ck1, CkQ, CkQ, (V, (V, Cj, C? NMOS transistor controlled by Mc are successively Bu Ml, M2, M4, M5, McQ, M7, M8 representation;

共三个它们的栅极依次分别受信号Kj.u、 Pj.,,k、 Gj.w控制的NMOS管,依次分别用管M3、 M6、 M9表示,其中,Kj.,,k是加法器的进位链中第k位到第jl位的进位消除信号,Pw,k是加法器的进位链中第k位到第jl位的进位传递信号,Gj.gc是加法器的进位链中第k位到第jl位的进位产生信号;上述管M3的漏极同时和上述管M1、 M2 的源极相连,上述管M6的漏极同时和上述管M4、 M5的源极相连,上述管M9的漏极同时和上述管M7、 M8的源极相连,M3、 M6、 M9管的源极共同接地; A total of three gates thereof are sequentially receiving signal Kj.u, Pj. ,, k, Gj.w control NMOS transistor, each tube successively M3, M6, M9, where, Kj. ,, k is an adder the carry chain of the k-th bit to the jl bit of the cancellation signal, Pw, k is the carry propagation signal carry chain adders of the k-th bit to the jl position, Gj.gc a carry chain adders in the k jl bit to bit carry generation signal; while the drain of the transistor M3 and the tube M1, M2 is connected to the source, while the drain of the transistor M6 and the tube M4, M5 is connected to the source of the transistor M9 while the drain and source of the pipe M7, M8 is connected to the source, the source M3 M6, M9 tube, are commonly grounded;

共六个它们的栅极都受上述时钟信号4>的反信号》控制的复位管,依次分别用Mpl、 Mp2、 Mp3、 Mp4、 Mp5、 Mp6表示;其中Mpl、 Mp2、 Mp3、 Mp4、 Mp5、 Mp6 管的源极共同接地;Mpl管的漏极同时和Md、 Ml、 M2、 M4管的漏极以及NM1管的源极相连,Mp2管的漏极同时和M5、 Mco、 M7、 M8管的漏极以及NM2管的源极相连, Mp3管的漏极同时和Ml、 M2管的源极以及M3管的漏极相连,Mp4管的漏极同时和M4、 M5管的源极以及M6管的漏极相连,Mp5管的漏极同时和MC(j、 Md管的源极相连,Mp6管的漏极同时和M7、 M8管的源极以及M9管的漏极相连;上述各个复位管在电路预充时导通,泄放所连节点的电荷。 Inverted signal of a total of six are their gates receiving the clock signal 4> "control the return pipe, respectively successively Mpl, Mp2, Mp3, Mp4, Mp5, Mp6 representation; wherein Mpl, Mp2, Mp3, Mp4, Mp5, Mp6 common source transistor is grounded; the drain pipe while the Mpl and Md, Ml, M2, M4 drain tube and a source electrode connected to the tube NM1, and the drain of Mp2, while the tube M5, Mco, M7, M8 tube NM2 drain and a source electrode connected to the tube, a drain tube Mp3 and simultaneously, a source and a drain pipe M2 Ml M3 tube is connected to the drain pipe simultaneously Mp4 and M4, the source of M5 and M6 tubular pipe a drain connected to the drain and the source of Mp5 tube while MC (j, Md transistor is connected to the drain pipe simultaneously Mp6 and source and drain tube M9 M7, M8 is connected to the tube; and the return pipe in each circuit when the pre-charge is turned on, the connected nodes to bleed charge.

我们采用中芯国际0.18微米CMOS工艺设计实现了使用上述两种进位产生电路的功耗平衡的延时不敏感加法器和前面提到的非功耗平衡的延时不敏感加法器,并采用hspice对电路进行仿真。 We SMIC 0.18 micron CMOS process designed to achieve a delay using either the carry generation circuit insensitive to power balance and the non-power adder equilibrium delay insensitive to the aforementioned adder, and using hspice circuit simulation.

a) 图10是2种加法器的功耗波形:每幅图中的3条曲线分别是计算00+00+r, FF+FF+0, 00+FF+1时的功率曲线,分别代表了三种典型的情况。 a) of FIG. 10 is a waveform of two kinds of power adder: in each of the figures are calculated three curves 00 + 00 + r, FF + FF + 0, 00 + FF + 1 when power curve, representing the three typical situations. 为了更好地描述电路功耗差分特征,本文定义下面两项指标。 In order to better describe the power differential circuit features, the following two indicators defined herein.

绝对差分:如果定义输入(或电路状态)为i的情况下,平均功耗曲线为Pi(t),总体样本,即各种输入(或状态)下的总分布的样本的均值功耗曲线为P(t),定义i的差分曲线 Absolute Difference: If the input is defined (or circuit state) in the case of i, the average power consumption curve Pi (t), the total mean power distribution curve of the sample under the overall sample, i.e., various input (or state) P (t), defines the difference curve i

十六进制表示,前两项为加数,第三项是进位.Di(t)-Pi(t)-P(t),差分曲线的峰值max(IDi(t)l)定义为i的绝对差分PD(i)。 In hexadecimal notation, the first two addend, a third carry .Di (t) -Pi (t) -P (t), the differential curve peak max (IDi (t) l) is defined as the i absolute difference PD (i). 绝对差分表明了各种情况下功耗差分的绝对规模,当绝对差分小于分析系统可以检测的阈值时我们就认为电路是功耗平衡的。 Absolute difference shows the absolute size of the power differential in each case, when the absolute difference is smaller than analysis system can detect threshold we consider power circuit is balanced.

相对差分:定义某个采样点t上所有输入i的差分绝对值的最大值与该时刻的总体平均功耗的比为 Relative difference: the definition of a sample point t i for all input difference than the maximum absolute value of the average power consumption of the overall time is

加x争.(,)卩 Plus x dispute. (,) Jie

Z)Affi (0 = ~^~!-!~。 Z) Affi (0 = ~ ^ ~ -!! ~.

尸(O Corpse (O

我们关心的是DMR曲线的峰值,max{DMR(T)},我们定义它为电路的相对差分。 We are concerned DMR peak curve, max {DMR (T)}, we define it as a relative differential circuit. 这个差分反应了差分相对于功耗水平的显著程度。 This difference reflects the difference with respect to the power level of a significant degree. 对于一定量化精度的数据采集系统,而言意味着更小的差别。 For a given quantization precision data acquisition systems, in terms it means a smaller difference.

通过对105组随机样本的计算进行仿真得到了本发明所述电路和两种加法器的绝对功耗差分和相对功耗差分,列于表1表2。 By calculating the random sample 105 was set to simulate the absolute power differential circuit according to the present invention and two types of adders and relative power differential listed in Table 1. Table 2. 其中器件数包括各单元内部产生反相时钟的电路和输出反相器。 Wherein the number of each unit include an internal clock generating circuit and the inverting output of the inverter.

表1功耗平衡模块与非功耗平衡模块的功耗差分<table>table see original document page 10</column></row> <table> Table 1 Differential Power consumption power balancing module and the non-equilibrium modules <table> table see original document page 10 </ column> </ row> <table>

表2两种DICLA (8位)功耗差分数据<table>table see original document page 10</column></row> <table> Table 2 two kinds DICLA (8 bits) power differential data <table> table see original document page 10 </ column> </ row> <table>

上述两种加法器分别被嵌入于单级的异步流水线之中,进行流片,得到芯片的最终测 Both adders are embedded in a single stage in an asynchronous pipeline, taped, to give a final test chip

试结果是:相同工艺下的DICLA的最大功率差分是2.16mW, PBDICLA的功率差分是0.66mW。 The test results are: the maximum power difference DICLA under the same process is 2.16mW, differential PBDICLA power is 0.66mW. 相同测试条件下得到的功率信号的信噪比(差分与估计的测量噪声之比),前者比后者提离了9倍左右。 Ratio (ratio of the difference to the estimated measurement noise) power signal obtained under the same test conditions, the former than the latter liftoff about 9 times.

为了检验加法器的功耗平衡情况,我们对加法器不同输入情况下的功耗差分进行了统计分析。 To test the power balance of the adder, we adder under different input power differential conducted a statistical analysis. 试验共采集了4528个功率波形样本。 Test were collected 4528 power waveform samples. 这些样本根据它们对应的输入先后按照下面 These samples according to their corresponding input has the following

三种分组方式被划分成两或三组。 Three groupings embodiment is divided into two or three. (组号后列出的是输入数据需要满足的条件),并计算出每组的平均功率曲线: (Group number listed after the input data is a condition to be satisfied), and calculates an average power curves of each group:

1)组Al:AoB(H)O,其它位随机选取;组A2: AoBfll,其它位随机选取:组A3:A0B()=01,其它位随机选取; 1) Group Al: AoB (H) O, the other bits randomly selected; Group A2: AoBfll, other bits randomly: Group A3: A0B () = 01, the other bits randomly selected;

2) 组B1: I(uk(g)3,其它位随机选取;组B2: 1。,,=?,其它位随机选取; 2) Group B1: I (uk (g) 3, other bits randomly selected; Group B2:. 1 ,, = ?, other randomly selected bits;

3) 组C1: I«u=k(g),其它位随机选取;组C2: I。 3) Group C1: I «u = k (g), other bits are randomly selected; Group C2: I. ,3=p,其它位随机选取; , 3 = p, the other bits randomly selected;

组l)考察的是C模块输入数据不同对功耗的影响;组2)考察的是进位信号C2的产生控制信号不同对功耗的影响;组3)则是考察C4的产生控制信号不同对功耗的影响。 Group l) was examined influence of the input data C modules of different power consumption; group 2) examined the impact of different power consumption of the carry signal C2 to generate a control signal; group 3) produced is different from a control signal C4 Investigation influence power consumption.

功率的测量采用在芯片与电源间串联采样电阻,测量电阻两端电压在转换为工作电流的方法。 Power measurement sampling resistor in series between the chip and the power supply, the voltage across the resistor is converted to work in the method of measuring the current. 数据采集设备是带宽500MHz的数字采样示波器。 Data acquisition device is 500MHz bandwidth digital sampling oscilloscope. 芯片的工作电压被降低到1.4 伏,以降低翻转速度。 The operating voltage of the chip is reduced to 1.4 volts, to reduce the turning speed. 得到的功率数据经过软件分析,统计结果如下。 Power data obtained through software analysis, statistical results are as follows.

两个芯片的主要指标列于表3中。 Two main indicators of the chip are listed in Table 3. 其中Dwa2 , Da2A3, DA1A3, Dwb2和DdC2分别表 Wherein Dwa2, Da2A3, DA1A3, Dwb2 table, respectively, and DdC2

示脚标所指的两个组间的功率差分曲线的最大值。 The maximum value of the power difference between the two groups of curves illustrating the subscript refers. 表中所列的差分是在存在噪声的情况下得到的,如果假设噪声带来的标准偏差为A,则差分信号中的噪声为V?A,如果实际测量值用D表示,则在给定的测量条件和样本空间下可以近似求出差分的信噪比(SNR),计算式如下: Differential listed in the table are obtained in the presence of noise, assuming the standard deviation of the noise is caused by A, then the differential noise in the signal is V? A, if the actual measurement value is represented by D, the given under the measurement conditions and the sample space may be approximately determined SNR difference (SNR), the formula is calculated as follows:

柳,< Liu <

在分析中,以在电路不工作时测得功率的标准偏差的平均值近似噪声△(表3中的噪 In the analysis, and the average standard deviation of the measured power circuit does not operate at approximately △ noise (noise Table 3

声一栏),考察电路最大差分的情况,即D取Da,a2 , Da2a3, DA1A3, DB啦和DdC2的最大 Acoustic column), the maximum difference inspection circuit, i.e. D taken Da, the maximum a2, Da2a3, DA1A3, DB and friends of DdC2

值,得到两种加法器的最大信噪比,列于表3最后一项。 Value to give two maximum SNR adder, the last item listed in Table 3.

表3 DICLA与PBDICLA的功耗差分与信噪比<table>table see original document page 11</column></row> <table> Table 3 DICLA PBDICLA and the power differential and SNR <table> table see original document page 11 </ column> </ row> <table>

从表中可以看出,PBDICLA在考察的3种数据特征上的差分都小于DICLA,信噪比将近是DICAL的1/10,有效地降低了信息的泄漏。 As can be seen from the table, PBDICLA differential data on three kinds of feature inspection is less than DICLA, signal to noise ratio is nearly DICAL 1/10, effectively reduces the leakage of information. 通过本发明电路仿真和实际流片的测量结 By the present invention circuit simulation measurement results and the actual flow sheet

果说明: Fruit Description:

1. 在器件层次进行功耗平衡设计,可以降低器件级差异带来的功耗差分; 1. Power balancing device design level, the device can reduce the difference in level caused by power differential;

2. 对电路内部节点增加了复位电路,降低了数据变化信息的泄露; 2. The internal circuit node reset circuit increases, reducing the leak data change information;

3. 本发明有效降低了电路功耗的差分; 附图说明 3. The present invention effectively reduces the power consumption of the differential circuit; BRIEF DESCRIPTION OF DRAWINGS

图1为DICLA结构图。 1 is a configuration diagram of FIG. DICLA.

图2为DICLA工作时序示意图(两加数所有位相同的情况)。 FIG 2 is a schematic DICLA operation timing (two addends all bits the same conditions). 3 I,,k表示Kifl,Gij和~均为0的情况。 3 I ,, k represents Kifl, Gij and are ~ 0. Iij-g, Iu=p与此类似,图3为DICLA工作时序示意图(两加数所有位都不同的情况)。 Iij-g, Iu = p Similarly, FIG. 3 is a timing diagram of the working DICLA (all bits addends two different situations).

图4为DICLA进位产生电路图。 FIG 4 is a circuit diagram of a generating DICLA carry.

图5为PBDICLA结构图。 FIG 5 is a configuration diagram PBDICLA.

图6为PBDICLA工作时序示意图。 FIG 6 is a schematic PBDICLA operation sequence.

图7为D单元结构图。 7 is a configuration diagram of a D unit.

图8为PBDICLAD单元进位产生电路CMOS实现。 FIG 8 is a circuit generating a carry unit PBDICLAD CMOS implementation.

图9为PBDICLAD单元进位产生电路(进位控制)CMOS实现。 FIG generating circuit 9 (carry control) units to carry PBDICLAD CMOS implementation.

图10为DICLA和PBDICLA对典型数值求和的功率曲线。 FIG 10 is a typical value PBDICLA DICLA and summed power curve.

图11为三种进位产生电路不同输入情况下的充放电结构,其中:(1)为DICLA进位产生电路;(2)为PBDICLA进位产生电路;(3)为PBDICLA进位产生(进位控制)电路; 各行从左到右依次为Kw,kl, GHk=l, P的情况。 FIG 11 generates three kinds of carry charge and discharge structures under different input the circuit, wherein: (1) generating circuit DICLA carry; (2) generating circuit PBDICLA carry; (3) generating (binary control) circuit PBDICLA carry; each row from left to right Kw, kl, GHk = situation l, P a. 具体实施方式 detailed description

电路的CMOS实现采用了N型求值网络的动态交叉耦合差分电路(DCCD电路)。 CMOS circuit implemented using the dynamic cross-coupled N-type differential circuit evaluation network (DCCD circuit). 动态交叉耦合差分电路可以很好地实现双轨编码的DI异步电路逻辑,由此电路构成的数据通道可以没有全局时钟更高的硬件安全性。 Dynamic cross-coupled differential circuit can realize the dual-rail encoding DI asynchronous logic circuit, whereby the circuit configuration of the data channel can no higher global clock hardware security. N型动态电路由充电开关(一个PMOS)、求值网络(NMOS组成)和一个放电开关管(一个NMOS)组成。 N-type dynamic circuit by a charging switch (a PMOS), the network evaluation (NMOS composition) and a discharge switch (a NMOS) composition. 充电开关和放电开关都由时钟控制。 Charging switch and the discharging switch controlled by the clock.

动态电路的工作方式是:分为预充和求值两步,第一步预充:时钟为低将PMOS打开, 放电开关截止,输出节点电容被充电至高电平;第二步求值:时钟为高,PMOS关闭,放电开关导通,如果输入组合使求值网络导通,则存在放电通路,输出节点电容放电至低电平,如果输入组合使求值网络借止,则无放电通路,输出节点电容的电荷维持。 Work dynamic circuits are: pre-charge and evaluation is divided into two steps, the first step precharge: the clock is low PMOS open, the discharge switch is turned off, the output node capacitance is charged to a high level; Step evaluated: Clock is high, the PMOS closed, the discharge switch is turned on, if the input network is evaluated in combination of conduction, there is a discharge path, the output node capacitor discharges to a low level, if the input network is evaluated in combination by the stop, no discharge path, capacitor charge output node maintains. 由于动态电路的充电电流是个固定值,相对于受输入数据控制的充电网络有更少的信息泄漏。 Since the dynamic charge current circuit is a fixed value, with respect to the charging network controlled by the input data has less information leakage.

C单元的电路在论文"Power-bal咖ed delay-insensitive carry-lookahead adders (《功耗平衡的延时不敏感超前进位加法器》),Xiangyu Li; Yihe Sun;ASIC, 2003. Proceedings. 5th International Conference on , Volume: 2 , 21-24 Oct. 2003, Pages:1289 - 1292"中己经公布在此不再赘述。 C circuit elements in the paper "Power-bal coffee ed delay-insensitive carry-lookahead adders (" balanced power delay insensitive lookahead adder "), Xiangyu Li; Yihe Sun;. ASIC, 2003. Proceedings 5th International Conference on, Volume: 2, 21-24 Oct. 2003, Pages: 1289 - 1292 "has been published in this will not repeat them. 其产生的进位控制信号输入到D单元中。 Carry it generates a control signal input to the D unit. 根据前面分析,进位控制信号只可能取进位消除、进位产生或进位传递一种情况,且必居其一。 According to the foregoing analysis, it may carry only a control signal taken to eliminate carry, carry is generated or carry propagation situation, and will be one. 所以组成I的K/P/G三个信号具有对称性质,即或者同时为0,或者其中一个为1其它皆为0。 Therefore, the composition I of the K / P / G signal having a symmetric three properties, i.e., simultaneously or 0, wherein a is 1 or 0 are both other.

下面介绍D单元的电路实现: The following describes a circuit implementation of D units:

如前所述,D单元有两部分电路组成(如图8)。 As described above, D unit circuit of two parts (Figure 8). 其中进位控制产生电路实现公式(1)-(3) 的功能,图中的Ii,k表示Pi,kKi,kGi,k3个信号,输入的Ij.uc表示PHkKj.,jcGj.u3个信号,同时输入到进位产生电路中。 (3) the function of the figure Ii, k represents Ij.uc Pi, kKi, kGi, k3 signal input representation PHkKj, jcGj.u3 signal, while - (1) wherein the carry generation circuit implementation control formula. is input to the carry generation circuit. 进位控制产生电路的CMOS实现在文献中也已经公布,在此不再赘述。 Carry generating circuit controls a CMOS implementation also been published in the literature, are not repeated here. 下面详细介绍进位产生电路的实现。 The following details the implementation of the carry generating circuit.

a)进位产生电路 a) carry generation circuit

图4是DICLA中的D单元进位产生电路,图8是PBDICLA中的D单元进位产生电路。 FIG 4 is a D unit DICLA carry generating circuit, FIG. 8 is a D unit PBDICLA carry generation circuit. 改进电路同样采用DCCD逻辑电路。 Improved DCCD logic circuit using the same. 两个电路都分成左右两部分,左侧产生CjG,实现公式(5)右侧产生Cj1,实现公式(6)。 Two circuits are divided into left and right parts, the left side is generated CJG, implement equation (5) is generated CJ1 right, to achieve the equation (6).

DICLA中的电路采用的是静态形式:即充电部分也由输入信号控制的。 DICLA circuitry employed in static form: i.e., the charging section also controlled by the input signal. C/c/都经过一级静态反相器输出。 C / c / are output via a static inverter. 对左侧电路,当Kw,k为l时,Ml截止,M4导通,节点^J为低电平,C/为1,这部分对应于(5)式中的Kj.,,k项;当C^和Pj.,,k同时为1时,M2都截止, 同时M3—M7组成的串联支路导通,节点^y放电至低电平,C/为l,对应于(5)式中的PHk(V项,两个放电支路并联,是"或"的关系(即任意一个支路导通,C,都会为1。右侧电路同理,由两个对应于(6)式中Gj+k和Pj-,,kCV两项的两个支路并联,其中Pj.!,kCV相对应的支路与C/电路复用M7管。 On the left side of the circuit, when Kw, k is l, Ml is turned off, M4 is turned on, the node ^ J is low, C / 1, which corresponds to the portion (5) of the item Kj ,, k.; when the C ^ and Pj. ,, k simultaneously is 1, M2 are turned off, while M3-M7 conducting branches consisting of the series, the node is discharged to a low level ^ y, C / L is, corresponding to (5) the PHk (V term, two parallel discharge branch is "oR" relationship (i.e., any one of conducting branches, C, will be for the right side of the circuit 1. Similarly, two corresponding to the formula (6) in Gj + k and Pj - ,, kCV two parallel two branches, wherein Pj, kCV corresponding branch of the C / multiplexing circuit M7 tube.!.

改进的功耗平衡电路如图8所示,图中没有画出输出反相器,输出信号是Cj两个信号的反信号。 Improved power consumption of the balancing circuit shown in Figure 8, not shown in FIG output inverter, the output signal is an inverted signal of the two signals Cj. 它采用的是动态交叉耦合差分电路(DCCD电路)。 It uses a dynamic cross-coupled differential circuit (circuit DCCD). 动态电路前面已经介绍过, 图中的<!>是时钟信号,由它控制的PMOS就是动态电路的充电开关,靠近输出节点端,栅接4>的NMOS是放电开关。 In front of the dynamic circuits have been introduced, in FIG. <!> Is a clock signal, which controls the charge switch is a PMOS dynamic circuit, an output node near the terminal connected to the gate 4> is an NMOS discharge switch. 串联在放电开关和地之间的管子组成了求值网络。 A switch connected in series between the discharge tube and the evaluation form the network. 所谓差分电路是指同时输入输入信号和输入信号的反信号进行运算,输出的结果也是产生正反两个信号。 The so-called differential circuit means is simultaneously input signal and an inverted signal of the input operation of the input signal, generating positive and negative result is two output signals. 显然双轨编码表示数据的电路自然是差分电路,差分电路的特点是对称,正反信号的负载平衡,因此对应的计算功耗也有对称性。 Obviously dual-rail encoding a circuit is a differential circuit NATURAL data, characteristics of the differential circuit is symmetrical, the load balancing positive and negative signals, and therefore power consumption is calculated corresponding to the symmetry. 由于MOS管源漏端节点存在寄生电容,所以当输出节点和该节点之间的NMOS导通时,输出端的电容和内部节点的寄生电容会重新分配电荷,从而导致输出节点电容放电,引起错误。 Since the MOS transistor source-drain parasitic capacitance end node, when the NMOS conduction between the output node and the node, the parasitic capacitance capacitor and an internal node of the output terminal of the charge redistribution, thereby causing the capacitance discharge output node, cause errors. 交叉耦合结构利用输出信号互补的关系(即两个信号在有效时总是相反),用输出信号控制一个PMOS提拉管接在输出节点上, 这样当某位为0时,就会把互补信号节点的提拉管打开,对该节点充电,以弥补由于内部电容分走的电荷,保持互补信号为l。 Cross-coupled complementary relationship using the output signal (i.e., when the two signals are always opposite to active), the output signal of a PMOS pull control tube connected to the output node, so that when someone is 0, the complementary signal will pulling the node to open the tube, charging the node to compensate for internal capacitance of the charge points due to go, holding the complementary signal l. 图9中的M1M2就是一对交叉耦合的PMOS,它们的栅分别接到对方的输出端,漏端接在本方的输出端上,源端与电源相连。 FIG 9 M1M2 is a pair of cross-coupled to the PMOS, the gate thereof are connected to the other output terminal, the drain terminal is terminated on the side of the output, connected to a power source. 一旦对方输出电平足够低就开始为本方输出充电。 Once they output level low enough to start charging outputs based side. 交叉耦合结构可以提高电路的可靠性。 Cross-coupled circuit reliability can be improved.

CMOS电路工作时的电流由输出节点和内部电容充电的充电电流、输出信号反转瞬间的短路电流组成。 A CMOS circuit current from the output node and the charging internal capacitance charging current, the output signal of the anti-short-circuit current instant composition. 电路充电部分的结构和参数影响充电电流,电路放点时输出信号电平下降,其所驱动的下一级电路也随着发生翻转,引起下一级电路的短路电流,短路电流的大小与放电过程中信号电平处于亚稳态区的时间有关,所以输出节点放电的RC参数也会影响电路的工作电流。 Structure and parameters of the charging circuit portion of the impact charging current drops when the output signal level of the discharge point of the circuit, its next-stage circuit is driven along with the inverted, causing a short-circuit current circuit, the size of the short-circuit current and discharge during the time the signal level is at about the metastable region, the output-node discharging RC parameters also affect the operating current of the circuit.

基于以上分析,要得到功耗平衡的特性,电路必须保证在任何数据输入情况下电路的充电部分和放电部分都是一致不变的~~^括结构一致和参数一致。 Based on the above analysis, to obtain a balanced power characteristics, the circuit must be consistent in any portion of the data input charging circuit and the discharge portion are consistent ~~ ^ invariant structure and comprises the same parameters. 下面分析图8电路- The following analysis of the circuit of FIG 8 -

首先我们先说明图8与图4电路在逻辑功能上是等效的:如果我们只看图中由KRk,GKk, Pw乂Ck1和C^信号控制的NMOS,它们组成了与DICLA中进位产生电路NMOS部分功能相同的求值网络。 First, we described the circuit of FIG. 8 and FIG. 4 is logically equivalent to the function: If we look at figures by the KRk, GKk, Pw and C ^ qe Ck1 signal for controlling NMOS, and they constitute a carry generation circuit DICLA NMOS portion functions the same evaluation network. 改进电路中,各支路不再复用同一个Pj.u控制的管子,而且增加了冗余的^.1,1^.1,1<控制的管子,但是由于增加的Kj化Gw,k控制管与M^串联,而I^在求值时(时钟为低)截止,所以不会影响电路逻辑。 Improved circuit, each branch pipe is no longer the same Pj.u multiplexed control, and increased redundancy .1,1 ^ ^ .1,1 <control tube, but due to the increase of the Kj Gw, k M ^ series with the control tube, and I ^ when evaluated (clock low) cut-off, it will not affect the logic circuit.

那么为什么增加这些冗余的结构呢? So why add these redundant structure? 一是为了使Ij.,.k的三个对称信号有相同的负载电容。 First, in order to make Ij.,. K three symmetrical signal have the same load capacitance. 信号反转的功耗与负载电容有关,Ij.u的三个对称信号在行为上是对称的(见第5页), 要使得无论哪个信号反转都产生相同的功耗必须保证三个信号有相同的负载电容。 Inverted signal power on the capacitive load, Ij.u three symmetrical signal is symmetrical in behavior (see page 5), so that regardless of which the inverted signal to produce the same power must ensure that the three signals have the same load capacitance. 而本级与之相连的晶体管的尺寸和数量又决定了该信号的负载电容大小,因此,电路中所有KH,k,qn,k,P^,k控制的管子有相同的尺寸,且个数相同。 The size and number of the present stage transistor connected thereto in turn determines the magnitude of the load capacitance of the signal, therefore, all the circuit KH, k, qn, k, P ^, k control tubes have the same size, and the number of the same.

二是要得到对称的充放电结构。 The second is to obtain a symmetrical charge and discharge structure. 因此在左侧Ky,k和右侧Gj+k下方还串联了一个求值时导通的"平衡"管,使得Kj.!,k或Gj-!,k为高时,电路也是通过两个串联NMOS放电,与Pj.w为高时相同。 Thus Ky the left, right and Gj + k k below the series when a further evaluation is turned "balance" tube, so that of Kj, or k Gj -.! !, k is high, the circuit is through two series NMOS discharge, when the same high Pj.w.

此外,改进电路还对内部节点都增加了复位电路,图8中,每个内部节点都有一个时钟控制的连到地的复位管(Mpl-Mp4)。 In addition, further improvement of the internal circuit nodes increases the reset circuit in FIG. 8, each internal node has a control clock connected to the ground return pipe (Mpl-Mp4). 在电路的预充相位,这些管子导通,将内部节点电位置为0。 In the precharge phase circuit, the tubes conducting, electrically internal node position is 0. 这样可以保证每次运算电路有相同的初始状态,可以避免电路初态不同引起的功耗差分。 This ensures that each operation of the circuits have the same initial state, the initial state of the circuit can be avoided due to the different power differential.

b)进位控制的进位产生电路 Carry b) carry control generating circuit

除了D单元外,在PBDICLA中还有一种进位控制的D单元(Dc单元)。 In addition to unit D, in PBDICLA There is also a control bit D units (Dc unit) into. Dc单元和D 单元的区别在于它的进位产生部分,必须在Ck有效后(即Ck、 C。有一个为1)才开始计算Cj,而普通的进位产生电路,如果Kj.,,k或Gj.ul,就可以立即产生Cj。 Difference Dc units and D units in that it carry generating section, must, after Ck effective (i.e. Ck, C. a 1) only counted Cj of, ordinary carry generating circuit, if Kj. ,, k or Gj .ul, Cj can be generated immediately. 下面介绍进位控制的进位产生电路CMOS实现。 Here Carry Carry generating circuit CMOS implementation of the control.

图9给出了进位控制D单元进位产生电路。 Figure 9 shows the carry control unit D carry generating circuit. 图中同样没有给出输出反相器电路,输出端是3和巧,即进位输出的反信号。 FIG likewise does not give an output of the inverter circuit 3 and the output terminal is clever, i.e. inverse carry output signal. 此电路也是DCCD形式,图中的M1-M9管组成了电路的求值部分。 This circuit also forms DCCD, M1-M9 in FIG tubes the evaluation of the circuit. Ml-M3对应式(12)中的Kj.!,k(CkO+CV)项;M4、 M6管对应式(12)中的Pj-i,kCkfl项;M5-M6管对应式(13)中的Pj-^Ck1项;M7-M9管对应式(13 )中的Gj.^Q^+Ck1) 项。 .! Kj corresponding formula (12) Ml-M3, k (CkO + CV) item; M4, Pj-i in M6 tube corresponding to the formula (12), kCkfl item; of M5-M6 tube corresponding to the formula (13) the term Pj- ^ Ck1;. M7-M9 in the corresponding tube of formula (13) Gj ^ Q item ^ + Ck1). 此处复用了Pj-u控制的NMOS。 Here multiplexed control NMOS Pj-u.

由于Ck有效时C^和C?有且仅有一个为l,所以无论Ck取何值,Ml-M2组成的部分路都是导通的,这样在功能上式(12)和式(5)是等价的,电路与式(5)也是等价的, 同时由于如果Ck无效,贝ij (M1-M2, M4-M5, M7—M8)以及与它们并联的所有晶体管都截止,电路不会开始计算,只有等到Ck有效后,才会有输出节点放电。 Since the valid Ck and C ^ C? And only one of L, so no matter what value Ck, part way Ml-M2 are composed of conductive, so that the formula (12) and (5) functionally are equivalent circuit of formula (5) are equivalent, and because if Ck invalid, shellfish ij (M1-M2, M4-M5, M7-M8), and all transistors are turned off in parallel with them, the circuit will not start calculation, only valid until after Ck, will have output-node discharging. 这就实现了进位控制的目的。 This enables the purpose of the carry control. 图中同时增加了一对C^和CV控制的NMOS与一个反相时钟控制的NMOS。 FIG while increasing a pair of NMOS NMOS and a clocked inverter and CV C ^ control. 这一支路在求值时,反相时钟控制的管子截止,所以不影响电路功能。 This branch when evaluated, the inverted clocked off the tube, it does not affect the circuit function. 它的作用同样是使得各种输入数据对应的充放电等效电路对称。 Its role is to make the same variety of input data corresponding to an equivalent circuit of the charge and discharge of symmetry.

此电路同样在内部节点加了复位NMOS (Mpl-Mp6),在电路预充时导通,把所连节点 Also in this circuit is added to reset internal nodes NMOS (Mpl-Mp6), turned on when the precharge circuit, connected to the node

的电荷泄放掉。 Charges vent let go. 为了平衡电路的充放电结构,进位控制的进位产生电路中也增加了一些冗余结构。 In order to balance the charge and discharge structure of the circuit, the carry bit generating circuit controlled feed was also added to some of the redundant configuration.

图11列出了DICLA中的进位产生电路、PBDICLA的进位产生电路和PBDICLA的进位控制的进位产生电路不同输入情况下的电路的有效结构。 Figure 11 shows the carry DICLA of a carry circuit, PBDICLA of a carry bit carry control circuit and generating a valid configuration PBDICLA circuit in the case where different input circuit. 因为(V和C^是对偶信号,所以Ck的取值对电路充放电网络的结构没有影响,图中就以Ck'C,-"10"为例。将输入情况分成Kj-"Gj.gc,Pj.,,k三个信号分别为l的情况分别列出,依次对应途中的第l-3列。其中: 图中粗线的MOS管在该输入情况下处于导通状态,细线管是截止管。截止管两端可以认为是开路,所以我们只关注加粗管子所组成的电路。 Since (V and C ^ is even signal, the value of Ck is no charge and discharge circuit structure of the network affected, in respect to FIG Ck'C, - "10" as an example where an input into Kj- "Gj.gc. ., Pj ,, k l where three signals are listed separately, sequentially corresponding to the middle column of the l-3 wherein: the bold line in FIG MOS transistor in the oN state in case the input fine line pipe is the cut-off tube cut-off ends of the tube can be considered an open, so we are only concerned with circuit composed of bold tube.

图中的第一行是DICLA即原设计中的进位产生电路。 The first row is DICLA FIG i.e., the original design of the carry generating circuit. 比较第一行的三个等效电路,显 Three equivalent circuit compares a first row, which was

然它们的充电网络和放电网络各不相同,彼此不对称。 However, their charging and discharging network different networks, asymmetrical to each other. 第二行是本发明所述的进位产生电路的等效电路——由于电路的充电部分相同,所以略去它们,同时略去了部分不受输入数据控制的器件。 The second line is an equivalent circuit of the carry generating circuit of the present invention - is the same as the charging portion of the circuit, which is omitted, while omitting the input data from the device control portion. 同样对比三种情况下加粗部分的结构,显然都是一个两管串联的放电支路, —个输出节点到内部节点的NMOS和一个内部节点到地的NMOS三个部分组成。 Similarly the enlarged portion of the comparative structure three cases, two are clearly a discharge branch connected in series, - to the output node of the NMOS internal node and an internal node to the NMOS three part composition. 如果保证这些结构的参数(即寄生电容,等效电阻,节点初始电平)都相同就可以保证功耗平衡。 If these structures to ensure that the parameters (i.e. the parasitic capacitance of the equivalent resistance, initial level nodes) are the same power balance can be ensured. 本发明所述进位控制的进位产生电路不同输入情况下的有效电路列在了图11中第3行。 The present invention is a control bit to enter the active circuit in the circuit generates different input column 11 in the third row in FIG. 显然,在每种情况下,有效电路都是一个输出节点连接一个两管串联的支路,另有一个输出节点连接两个连通内部节点的NMOS。 Obviously, in each case, the active circuit is an output node connected to a branch of two series, one output node connected to another NMOS two communicating internal nodes. 只要保证这些结构对应的参数相同就可以功耗平衡。 As long as these structures are the same as the corresponding parameters of the power consumption can be balanced.

Claims (2)

  1. 1.CMOS功耗平衡延时不敏感加法器用的进位产生电路,其特征在于,它是一种N型求值网络的动态交叉耦合差分电路,它含有: 一对交叉耦合的PMOS管用M1、M2表示,它们的源端接电源,栅极分别接到对方的漏极,它们的漏极同时也是本方的输出端,依次分别输出用双轨编码表示的进位信号Cj0,Cj1的反信号<overscore>Cj0</overscore>,<overscore>Cj1</overscore>,反信号<overscore>Cj0</overscore>,<overscore>Cj1</overscore>再依次分别经反相器后输出进位信号Cj0,Cj1; 两个分别由同一时钟信号φ控制的PMOS管,用PM1、PM2表示,它们的源极接电源,栅极接上述时钟信号φ,它们是上述动态交叉耦合差分电路,即DCCD电路的充电开关; 两个由上述时钟信号φ控制的NMOS管,用NM1、NM2表示,它们的漏极依次分别和上述充电开关PM1、PM2的漏极相连后再和上述交叉耦合管M1、(M2)的漏极相连这两个NM 1.CMOS power balance carry adder delay insensitive Used generation circuit, characterized in that it is dynamically cross-coupled differential circuit for evaluating the N-type network, comprising: a pair of cross-coupled PMOS tube M1, M2 said power source end thereof, the other side of the drain respectively connected to a gate, a drain thereof is also the output of the side sequentially carry signal Cj0 represented by dual-rail encoding are output, an inverted signal of CJ1 <overscore> Cj0 </ overscore>, <overscore> Cj1 </ overscore>, the inverted signal <overscore> Cj0 </ overscore>, <overscore> Cj1 </ overscore> in turn respectively after the inverter output carry signal Cj0, Cj1; two a separately controlled by the same clock signal φ PMOS tube, with PM1, PM2 expressed, their sources connected to the power supply, a gate connected to the clock signal [Phi], which is the moving cross-coupled differential circuit, i.e. the charge switch circuit DCCD; two control by the clock signal φ NMOS tube, with NM1, NM2 represents, respectively, are sequentially connected to their drain and said charge switch PMl, PM2 are connected to the drain and the intersection after the coupling tube M1, (M2) of the drain both NM OS管NM1、NM2是上述动态交叉耦合差分电路的放电开关; 八个它们的栅极依次分别受信号Kj-1,k、Pj-1,k、Gj-1,k、Gj-1,k、Pj-1,k、Kj-1,k、输入进位信号Ck0、Ck1控制的NMOS管,他们依次分别用NMk1,NMp1,NMg,NMk2,NMp2,NMg2,NMc0,NMc1管表示,其中,Kj-1,k是加法器的进位链中第k位到第j-1位的进位消除信号,Pj-1,k是加法器的进位链中第k位到第j-1位的进位传递信号,Gj-1,k是加法器的进位链中第k位到第j-1位的进位产生信号; 平衡用的NMOS管,用NMb表示,它是一种要得到对称的充放电结构而在求值时导通的平衡管,它的栅极接上述的时钟信号φ,它的漏极同时与上述NMk1管、NMg2管的源极相连,它的源极接地; 共四个它们的栅极都受上述时钟信号φ的反信号<overscore>φ</overscore>控制的复位管依次分别用Mp1、Mp2、Mp3、Mp4表示,在上述动态交叉耦合差分电路的初态这 OS tube NM1, NM2 is a discharge switch the moving cross-coupled differential circuit; eight their gates respectively receiving signals sequentially Kj-1, k, Pj-1, k, Gj-1, k, Gj-1, k, Pj-1, k, Kj-1, k, the input carry signal Ck0, Ck1 control NMOS transistor, they are sequentially respectively NMk1, NMp1, NMg, NMk2, NMp2, NMg2, NMc0, NMc1 tube, where, Kj-1 , k is the carry chain adders in the k-th bit to the j-1 th bit of the cancellation signal, Pj-1, k is the carry propagation signal carry chain adders of the k-th bit to the j-1 bits, Gj -1, k is a carry chain adders in the k-th bit to the j-1 th bit carry generation signal; the NMOS pipe balancing the use NMb expressed, it is a to obtain a symmetrical charge and discharge structure in the evaluation balance pipe when turned on, its gate connected to the aforementioned clock signal [Phi], while its drain electrode is connected to the source of the NMk1 tube NMG2 tube, its source grounded; their gates are a total of four receiving the clock signal inverted signal [Phi] <overscore> φ </ overscore> sequentially controlled return pipe respectively Mp1, Mp2, Mp3, Mp4 said initial state in which the moving cross-coupled differential circuit 管子导通,把内部上述八个NMk1、NMp1、NMg1,NMk2,NMp2,NMg2,NMc0,NMc1管子的漏极置0;其中,Mp1的漏极同时接NMk1、NMp1、NMg1管的漏极和NM1管的源极,Mp2管的漏极同时接NMg2NMp2、NMk2管的漏极和NM2管的源极,Mp4、Mp3管的漏极依次分别同时接NMp2管的源极和NMc1管的漏极、NMp1管的源极和NMc0管的漏极,Mp1、Mp2、Mp3、Mp4管的源极共同接地; 栅极受上述时钟信号φ的反信号<overscore>φ</overscore>控制的用M*表示的NMOS管,它在求值时截止以便得到对称的充放电结构,该M*管的漏极同时连接NMg1、NMk2的源极,而M*管的源极接地。 Conducting tube, the interior of the eight NMk1, NMp1, NMg1, NMk2, NMp2, NMg2, NMc0, opposing the drain pipe NMc1 0; wherein, while a drain contact MpI NMk1, drain NMp1, NMg1 tube and NM1 a source electrode and a drain pipe NMc1 source tube and the drain of Mp2, while the tube contact NMg2NMp2, NMk2 tube drain and source electrode of NM2 tube, Mp4, Mp3 drain tube are simultaneously connected sequentially NMp2 tube, NMp1 source and drain of the transistor is NMc0 tube, Mp1, Mp2, Mp3, Mp4 transistor is commonly grounded; a gate receiving the inverted signal of the clock signal [Phi] <overscore> φ </ overscore> control represented by M * NMOS transistor, which is turned off when evaluated in order to obtain a symmetrical charge and discharge of the drain pipe while the connection M * NMg1, NMk2 source, and the source is grounded tube M *.
  2. 2. CMOS功耗平衡的延时不敏感加法器用的进位产生电路,其特征在于:它是一种进位控制的进位产生电路,即它的进位产生部分必须在用双轨表示的输入进位信号Ck有效,即Cku,C」有一个为1后才开始计箅用双轨编码表示的输出进位信号Cj;所述的进位产生电路是一种N型求值网络的动态交叉耦合差分电路,它含有-一对交叉耦合的PMOS管,用CM1、 CM2表示,它们的源端接电源,各自的栅极分别接到对方的漏极,它们的漏极同时也是本方的输出端,依次分别输出用双轨编码表示的进位信号C/", C/的反信号巧,巧,反信号再依次分别经反相器后输出进位信号C」Q, C/;两个分别由同一时钟信号4>控制的PMOS管,用PM1、 PM2表示,它们的源极接电源,栅极接上述时钟信号4),它们是上述动态交叉耦合差分电路,即DCCD电路的充电开关;两个由上述时钟信号d)控制的NMOS管,用N 2. CMOS power feed Equilibrium delay insensitive adder Used generation circuit, characterized in that: it is a carry control carry generating circuit that its carry generating section must be valid at the input carry signal Ck with the two-track indicated , i.e. Cku, C "has a count of 1 after the start of the grate outputs a carry signal Cj by dual-rail encoded representation; the carry generating circuit is an N-type evaluation of the dynamic cross-coupled differential network circuits, comprising - a of cross-coupled PMOS transistor, with the CM1, CM2, said power source end thereof, the respective gates connected to the drain of the other, but also their drain output of this side, respectively sequentially output dual-rail encoding carry signal C represents the / ", C / inverted signal Qiao, Qiao, the inverted signal in turn were treated with the inverted output carry signal C 'Q, C /; two are from the same clock signal 4> controlled PMOS transistor with PM1, PM2 expressed, their sources connected to the power supply, a gate connected to the clock signal 4), which are the moving cross-coupled differential circuit, i.e. the charge switch circuit DCCD; two by the clock signal d) controlling the NMOS tubes, with N M1、 NM2表示,它们的漏极依次分别和上述充电开关PM1、 PM2的漏极相连后再和上述交叉耦合管CM1、 (CM2)的漏极相连,这两个NM0S管NM1、 NM2是上述动态交叉耦合差分电路的放电开关;共八个它们的栅极依次分别受信号Ck1、 Q1、 CkQ、 CkQ、 Q1、 CkQ、 CkQ、 Ck'控制的NMOS管依次分别用Mc,、 Ml、 M2、 M4、 M5、 McQ、 M7、 M8表示;共三个它们的栅极依次分别受信号Kj.u、 Pj.w、 Gw,k控制的NMOS管,依次分别用管M3、 M6、 M9表示,其中,Kj+k是加法器的进位链中第k位到第jl位的进位消除信号,Pj-u是加法器的进位链中第k位到第jl位的进位传递信号,Gn,k是加法器的进位链中第k位到第jl位的进位产生信号;上述管M3的漏极同时和上述管M1、 M2的源极相连,上述管M6的漏极同时和上述管(M4)、 (M5)的源极相连,上述管M9的漏极同时和上述管M7、 M8的源极相连,M3、 M6、 M9管的源极共 M1, NM2 expressed, their drain and said charge switch PMl, PM2 of the drain pipe and said cross-coupling the CM1, connected (CM2 is) is then in turn connected to the drain, respectively, these two tubes NM0S NM1, NM2 is the moving cross discharge switch coupled differential circuit; a total of eight gates thereof are sequentially receiving signal Ck1, Q1, CkQ, CkQ, Q1, CkQ, CkQ, Ck 'are sequentially controlled by the NMOS transistor Mc ,, Ml, M2, M4 , M5, McQ, M7, M8 represents; a total of three gates thereof are sequentially NMOS transistor receiving signal Kj.u, Pj.w, Gw, k control tube were successively M3, M6, M9, where, kj + k is the carry chain adders of the k-th bit to the jl bit of the cancellation signal, Pj-u is a carry chain adders of the k-th bit to the jl-bit carry propagation signal, Gn, k is an adder the carry chain of the k-th bit to the jl-bit carry generation signal; drain of the transistor M3 at the same time and said pipe M1, M2 is connected to the source, the drain of the transistor M6 simultaneously and said tube (M4), (M5 ) is connected to the source, the drain of the transistor M9 and simultaneously the tube M7, M8 is connected to the source, the source M3 M6, M9 tube, were very 接地:共六个它们的栅极都受上述时钟信号4>的反信号^控制的复位管,依次分别用Mpl、 Mp2、 Mp3、 Mp4、 Mp5、 Mp6表示;其中Mpl、 Mp2、 Mp3、 Mp4、 Mp5、 Mp6管的源极共同接地;Mpl管的漏极同时和MCl、 Ml、 M2、 M4管的漏极以及NM1管的源极相连Mp2管的漏极同时和M5、 Mco、 M7、 M8管的漏极以及NM2管的源极相连,Mp3管的漏极同时和M1、 M2管的源极以及M3管的漏极相连,Mp4管的漏极同时和M4、 M5管的源极以及M6管的漏极相连,Mp5管的漏极同时和Mco、 Md管的源极相连,Mp6管的漏极同时和M7、 M8管的源极以及M9管的漏极相连;上述各个复位管在电路预充时导通,泄放所连节点的电荷。 Ground: trans ^ control signal return pipe are a total of six their gates receiving the clock signal 4> sequentially respectively Mpl, Mp2, Mp3, Mp4, Mp5, Mp6 representation; wherein Mpl, Mp2, Mp3, Mp4, a source electrode common ground Mp5, Mp6 tube; while the drain and source of Mpl tube MCl, Ml, M2, M4 tube and the drain tube NM1 is connected to the source while the drain of Mp2 tube and M5, Mco, M7, M8 tube NM2 source and the drain of transistor is connected to the drain pipe simultaneously with the drain Mp3 M1, M2 tube and the source of M3 is connected to the tube, while the drain tube Mp4 and M4, M5 and M6 source tube pipe a drain connected to the drain pipe simultaneously Mp5 and Mco, Md transistor is connected to the source, while the drain pipe and the drain Mp6 M7, M8 tube, and a source of M9 is connected to the tube; each of the above-described pre-reset circuit tube charging is turned on, the connected nodes to bleed charge.
CN 200410101820 2004-12-24 2004-12-24 Carry generating circuit for CMOS power-consumption balance delay-sensitive less adder CN100428248C (en)

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