CN116418204A - Improved rising time control circuit with wide modulation range - Google Patents
Improved rising time control circuit with wide modulation range Download PDFInfo
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- CN116418204A CN116418204A CN202111675671.4A CN202111675671A CN116418204A CN 116418204 A CN116418204 A CN 116418204A CN 202111675671 A CN202111675671 A CN 202111675671A CN 116418204 A CN116418204 A CN 116418204A
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- tube
- control circuit
- time control
- nmos
- node
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- 230000000630 rising effect Effects 0.000 title claims description 9
- 239000003990 capacitor Substances 0.000 claims description 4
- 230000000694 effects Effects 0.000 abstract description 4
- 230000009286 beneficial effect Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 8
- 230000015556 catabolic process Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000012217 deletion Methods 0.000 description 1
- 230000037430 deletion Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
- H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Amplifiers (AREA)
Abstract
The rise time control circuit with the improved wide modulation range can be beneficial to realizing a wider modulation range by combining a second NMOS tube, a first NMOS tube, an error amplifier and a first PMOS tube which has a modulation effect on the grid voltage of the power tube on the grid node of the power tube.
Description
Technical Field
The invention relates to a voltage rising time control technology, in particular to an improved rising time control circuit with a wide modulation range.
Background
FIG. 3 is a diagram of an original rise time control circuit. Fig. 4 is a waveform diagram of the relevant node in fig. 3. Referring to fig. 3 to 4, the original rise time control circuit includes power transistors MnPWR, drain electrodes of MnPWR are connected to a power voltage terminal IN, source electrodes of MnPWR are voltage output voltage nodes OUT, gate nodes gate of MnPWR are respectively connected to a charge pump and drain electrodes of a second NMOS transistor Mn1, gate electrodes of Mn1 are connected to the power voltage terminal IN, drain electrodes of Mn1 are connected to source electrodes of a first PMOS transistor Mp0, drain electrodes of Mp0 are grounded, gate electrodes of Mp0 are connected to the power voltage terminal IN through a first path of a first PMOS transistor gate node Vramp, and a second path is grounded through a first capacitor C0. As shown IN fig. 4, when vramp=vgs1+|vgsp 0|, when Vramp is low so that both Mp0 and Mn1 can be turned on, the gate voltage gate of MnPWR is modulated by Mp0, vgnpwr=vramp+vgsp 0, and when Vramp rises to IN-vramp=vgs1+|vgsp 0| < vth1+|vthp 0|, that is, vramp is greater than or equal to IN-Vthn1- |vthp 0|=in-1.4V, mn1 and Mp0 are cut off, the path from the MnPWR gate to ground is cut off, and the modulation effect of Mp0 on the MnPWR gate voltage disappears, so that the MnPWR gate voltage exhibits a piecewise phenomenon with inconsistent rising slope as shown IN fig. 4. This is undesirable in applications.
Disclosure of Invention
The invention provides an improved rise time control circuit with wide modulation range, which aims at the defects or shortcomings in the prior art.
The technical scheme of the invention is as follows:
the rising time control circuit is characterized by comprising a power tube grid node, wherein a first path of the power tube grid node is connected with a charge pump, a second path of the power tube grid node is connected with a source electrode of a first PMOS tube, the first path of the first PMOS tube grid node is connected with a power supply voltage end through a second current source, the second path of the first PMOS tube is grounded through a first capacitor, the drain electrode of the first PMOS tube is connected with a drain electrode of a second NMOS tube, the source electrode of the second NMOS tube is connected with the drain electrode of the first NMOS tube through a first node, the source electrode of the first NMOS tube is grounded, the gate electrode of the first NMOS tube is connected with an output end of an error amplifier, a negative input end of the error amplifier is connected with the gate electrode of the first PMOS tube, a positive input end of the error amplifier is connected with the power supply voltage end through a first resistor, and the second path is grounded through the first current source.
And a first diode is connected between the grid sources of the second NMOS tube in a bridging way.
The positive pole of first diode is connected first node, the negative pole of first diode is connected power supply voltage end.
The voltage maximum value of the first node=power supply voltage+forward bias voltage drop of the first diode.
And if the current of the first current source is I0 and the resistance value of the first resistor is R0, I0 and R0 are less than or equal to 50mV.
Let the power voltage be IN and the gate voltage of the first PMOS transistor be Vramp, then IN-I0R 0 > IN-1.4V.
The power tube is an NMOS power tube, the drain electrode of the NMOS power tube is connected with a power supply voltage end, and the source electrode of the NMOS power tube is connected with an output voltage node.
The invention has the following technical effects: according to the improved rising time control circuit with the wide modulation range, the second NMOS tube, the first NMOS tube, the error amplifier and the first PMOS tube which has the modulation function on the grid voltage of the power tube are utilized to be combined on the grid node of the power tube, so that the wider modulation range can be realized.
Drawings
Fig. 1 is a schematic diagram of the structure of a rise time control circuit embodying an improved wide modulation range of the present invention.
Fig. 2 is a schematic waveform diagram of the relevant node in fig. 1. FIG. 2 includes a gate node gate of a power transistor (MnPWR), a gate node Vramp of a first PMOS transistor (MP 0), and a source output voltage node OUT of the power transistor (MnPWR). The gate in FIG. 2 is longer in segment 3 and shorter in segment 4 than the gate in FIG. 4. OUT in fig. 2 is longer in segment 2 and shorter in segment 3 than OUT in fig. 4. IN-I0R 0 > IN-1.4V IN FIG. 2.
FIG. 3 is a diagram of an original rise time control circuit.
Fig. 4 is a waveform diagram of the relevant node in fig. 3. Fig. 4 includes a gate node gate of a power transistor (MnPWR), a gate node Vramp of a first PMOS transistor (Mp 0), and a source output voltage node OUT of the power transistor (MnPWR). The gate in FIG. 4 is shorter in segment 3 and longer in segment 4 than the gate in FIG. 2. OUT in fig. 4 is shorter in segment 2 and longer in segment 3 than OUT in fig. 2. IN-1.4V < IN-I0R 0 IN FIG. 4.
The reference numerals are listed below: an IN-supply voltage terminal or supply voltage (or VIN); mnPWR-NMOS power tube; gate-power tube gate node; an OUT-output voltage node or a power tube output voltage; MP 0-a first PMOS tube; mn 0-Mn 1-a first NMOS tube to a second NMOS tube; a Vramp-first PMOS tube gate node; a-a first node; d0-first diode; c0-a first capacitance; r0-a first resistor; ibias-second current source; i0-a first current source; EA-error amplifier or comparator.
Detailed Description
The invention will be described with reference to the accompanying drawings (fig. 1-2).
Fig. 1 is a schematic diagram of the structure of a rise time control circuit embodying an improved wide modulation range of the present invention. Fig. 2 is a schematic waveform diagram of the relevant node in fig. 1. Referring to fig. 1 to 2, an improved rising time control circuit with a wide modulation range includes a power tube gate node gate, a first path of the power tube gate node gate is connected to a charge pump, a second path of the power tube gate node gate is connected to a source of a first PMOS tube Mp0, a first path of the first PMOS tube gate node Vramp is connected to a power supply voltage terminal IN through a second current source Ibias, a second path of the power tube gate node Vramp is grounded through a first capacitor C0, the first PMOS tube Mp0 is connected to a drain of a second NMOS tube Mn1, a gate of the second NMOS tube Mn1 is connected to a power supply voltage terminal IN, a source of the second NMOS tube Mn1 is connected to a drain of a first NMOS tube Mn0 through a first node a, a source of the first NMOS tube Mn0 is grounded, a gate of the first NMOS tube Mn0 is connected to an output terminal of an error amplifier EA, a negative input terminal (-) of the error amplifier EA is connected to the first PMOS tube gate node Vramp, and a positive input terminal (+) of the error amplifier EA is connected to a first path of the power supply voltage terminal IN through a first resistor R0 and a first current source I is grounded. The gate source of the second NMOS transistor Mn1 is connected across the first diode D0.
The positive pole of the first diode D0 is connected with the first node A, and the negative pole of the first diode D0 is connected with the power supply voltage end IN. The voltage maximum value of the first node a=supply voltage+forward bias voltage drop of the first diode. And if the current of the first current source is I0 and the resistance value of the first resistor is R0, I0 and R0 are less than or equal to 50mV. Let the power voltage be IN and the gate voltage of the first PMOS transistor be Vramp, then IN-I0R 0 > IN-1.4V. The power tube is an NMOS power tube MnPWR, the drain electrode of the NMOS power tube MnPWR is connected with a power supply voltage end IN, and the source electrode of the NMOS power tube MnPWR is connected with an output voltage node OUT.
As shown IN fig. 1, when Mp0 gate voltage Vramp < IN-I0R 0, the comparator outputs high level, so that Mn0 is turned on, and a current path is formed between MnPWR gate and ground through Mp0, mn1, mn0, and MnPWR gate voltage vgnpwr=vramp+vgsp 0. When Vramp is larger than IN-I0R 0, the comparator outputs a low level, so that Mn0 is cut off, a grounding path of the MnPWR gate electrode is cut off, the voltage of the MnPWR gate electrode can be increased to a higher potential under the drive of a charge pump, and the conduction resistance of the MnPWR is reduced. When Mn0 is turned off, if no diode D0 is present, the voltage at point a is pulled up to the MnPWR gate voltage, and IN general, the MnPWR gate voltage will rise to a voltage of 2×vin under the driving of the charge pump, the voltage difference between point a and ground, i.e., the drain-source voltage difference of Mn0 is 2×vin, and when IN is connected to a power supply of 3V or more, the drain-source breakdown of Mn0 will result. Therefore, the diode D0 is led IN to be bridged between the grid sources of Mn1 IN the scheme, and under the protection of D0, the maximum value of the voltage VA at the point A=IN+the forward bias voltage drop of the diode D0, so that the protection effect on the drain electrode of Mn0 is realized when the grid voltage of Mn0 is cut off and the grid voltage of Mn PWR is increased to high voltage. Typically, the design will ensure that the product of I0 and R0 does not exceed 50mV, so that the MnPWR gate voltage is modulated by MP0 as widely as possible. The waveforms of the gate and source voltages of the modified MnPWR are shown in fig. 2, where the 3 rd segment is longer and the 4 th segment is shorter in fig. 2 compared to the gate in fig. 4. OUT in fig. 2 is longer in segment 2 and shorter in segment 3 than OUT in fig. 4. IN-I0R 0 > IN-1.4V IN FIG. 2.
What is not described in detail in the present specification belongs to the prior art known to those skilled in the art. It is noted that the above description is helpful for a person skilled in the art to understand the present invention, but does not limit the scope of the present invention. Any and all such equivalent substitutions, modifications and/or deletions as may be made without departing from the spirit and scope of the invention.
Claims (7)
1. The rising time control circuit is characterized by comprising a power tube grid node, wherein a first path of the power tube grid node is connected with a charge pump, a second path of the power tube grid node is connected with a source electrode of a first PMOS tube, the first path of the first PMOS tube grid node is connected with a power supply voltage end through a second current source, the second path of the first PMOS tube is grounded through a first capacitor, the drain electrode of the first PMOS tube is connected with a drain electrode of a second NMOS tube, the source electrode of the second NMOS tube is connected with the drain electrode of the first NMOS tube through a first node, the source electrode of the first NMOS tube is grounded, the gate electrode of the first NMOS tube is connected with an output end of an error amplifier, a negative input end of the error amplifier is connected with the gate electrode of the first PMOS tube, a positive input end of the error amplifier is connected with the power supply voltage end through a first resistor, and the second path is grounded through the first current source.
2. The improved wide modulation range rise time control circuit of claim 1, wherein a first diode is connected across the gate source of said second NMOS transistor.
3. The improved wide modulation range rise time control circuit of claim 1, wherein a positive electrode of a first diode is connected to said first node and a negative electrode of said first diode is connected to a supply voltage terminal.
4. The improved wide modulation range rise time control circuit of claim 3, wherein the voltage maximum at the first node = supply voltage + forward bias voltage drop of the first diode.
5. The improved wide modulation range rise time control circuit of claim 1, wherein if said first current source current is I0 and said first resistance is R0, I0 x R0 is less than or equal to 50mV.
6. The improved wide modulation range rise time control circuit of claim 5, wherein if the power supply voltage is IN and the first PMOS transistor gate voltage is Vramp, IN-I0R 0 > IN-1.4V.
7. The improved wide modulation range rise time control circuit of claim 1, wherein the power tube is an NMOS power tube, a drain of the NMOS power tube is connected to a supply voltage terminal, and a source of the NMOS power tube is connected to an output node.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111675671.4A CN116418204A (en) | 2021-12-31 | 2021-12-31 | Improved rising time control circuit with wide modulation range |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111675671.4A CN116418204A (en) | 2021-12-31 | 2021-12-31 | Improved rising time control circuit with wide modulation range |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116418204A true CN116418204A (en) | 2023-07-11 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111675671.4A Pending CN116418204A (en) | 2021-12-31 | 2021-12-31 | Improved rising time control circuit with wide modulation range |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116418204A (en) |
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2021
- 2021-12-31 CN CN202111675671.4A patent/CN116418204A/en active Pending
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