CN113552917B

CN113552917B - Voltage reference circuit and method for realizing high-voltage application by using low-voltage process device

Info

Publication number: CN113552917B
Application number: CN202110835711.0A
Authority: CN
Inventors: 张琪; 姜秀彬; 郑志渊; 袁剑涛; 黄凯; 郑丹丹
Original assignee: Hangzhou Shuotian Technology Co ltd
Current assignee: Hangzhou Shuotian Technology Co ltd
Priority date: 2021-07-23
Filing date: 2021-07-23
Publication date: 2022-09-16
Anticipated expiration: 2041-07-23
Also published as: CN113552917A

Abstract

The invention belongs to the field of voltage reference circuits in integrated circuits, and discloses a power supply reference circuit suitable for realizing high voltage resistance of a low-voltage device, which comprises a high-value resistor R1 bearing the high voltage of the circuit, a resistor R2 generating bias, an NMOS device of a low-voltage 3.3V process, bias tubes NM 1-NM 3, an overvoltage circuit protection tube NM4, a feedback tube NM5 stabilizing the power supply voltage to a designed low-voltage value, a high-value resistor R3 and a PMOS feedback tube PM6 of the low-voltage 3.3V process. By the design, the low-voltage technology can be adopted to enable the circuit to generate a low-voltage reference capable of bearing a high-voltage power supply of more than 100V, the high-voltage technology or other special high-voltage resistant devices are not needed, the technological requirement and the cost of the designed circuit are reduced, and the low-voltage circuit has high use value and popularization value.

Description

Voltage reference circuit and method for realizing high-voltage application by using low-voltage process device

Technical Field

The invention belongs to the field of voltage reference circuits in integrated circuits, and particularly relates to a voltage reference circuit and a method for realizing high-voltage application by using low-voltage process devices.

Background

In the circuit design of an integrated circuit, a voltage reduction and stabilization structure is often required for a power supply to reduce and stabilize voltage to generate a voltage value required by the circuit for other circuits. The existing integrated circuit technology is smaller and smaller, the working frequency is higher and higher, and the performance is better and better, but the withstand voltage of the ordinary device is lowered along with the reduction of the technology, so that the withstand voltage value of the whole circuit is lowered.

As shown in fig. 1, is a conventional power independent reference structure. The main principle is to use current self-bias,

is obtained by feedback

From

And

copy and make a copy of

To thereby determine

Will essentially

Is bootstrapped to

. Then adding a constraint resistor

A unique power-independent current value can be determined, and a power-independent reference voltage can be obtained. However, the limitation is that when the circuit adopts a low-voltage process, the circuit is only suitable for the premise of the power supply voltage allowed by the adopted process, but is not suitable for the application scenario of a high-voltage power supply above the voltage of a process device, unless a special high-voltage process is used or a special device is used, so that the requirements of design and process are increased, and the cost is increased. This configuration has significant limitations for high voltage power supply applications.

Disclosure of Invention

The invention aims to provide a voltage reference circuit and a method for realizing high-voltage application by using a low-voltage process device, so as to solve the technical problem of the limitation of the traditional reference structure irrelevant to a power supply.

In order to solve the technical problems, the specific technical scheme of the voltage reference circuit and the method for realizing high-voltage application by using the low-voltage process device is as follows:

a power supply reference circuit suitable for realizing high voltage resistance of a low-voltage device comprises a resistor R1 connected with a high-voltage power supply, wherein the POS end of R1 is connected with the high-voltage power supply, the Neg end of R1 is connected with the drain end of NM1, the drain end of NM4, the Pos end of R3 and the source end of PM 6; the NM1, NM2 and NM3 are connected in a diode mode, the source end of NM1 is connected with the drain end of NM2, the source end of NM2 is connected with the drain end of NM3, the source end of NM3 is connected with the POS end of a resistor R2, and the Neg end of R2 is connected with a common ground end; the gate of the NM4 is connected with the drain of the NM2, the source of the NM4 is connected with the Neg of the R3, the Neg of the R3 is connected with the drain of the NM5, the gate of the NM5 is connected with the drain of the NM3, and the source of the NM5 is connected with the common ground end to serve as a feedback branch; the grid electrode of the PM6 is connected with the drain terminal of the NM5, and the drain terminal is connected with the common ground terminal; the Neg terminal of R1 is used as the VREF signal output terminal.

Further, NM1, NM2, NM3 and NM4 are low-voltage 3.3V process NMOS devices, PM6 is a 3.3V process PMOS device, R1 is a resistor for realizing a voltage withstanding function of the circuit, R2 is a bias resistor, and R3 is a feedback network resistor.

The invention also discloses a method for realizing the high-voltage-resistant power reference circuit suitable for the low-voltage device, which comprises the following steps:

step 1: the voltage VH input from the high-voltage power supply voltage input end VDDH is converted into current through a resistor R1 and is divided into branch currents I1, I2 and I3;

and 2, step: the high-voltage power supply voltage input end VDDH starts to be electrified, voltage drop is generated on R1, voltage VREF is generated, meanwhile, diode-connected Nmos tubes NM1, NM2, NM3 and R3 are conducted to generate current I1, and bias voltages VG4 and VG5 are generated;

and step 3: the bias voltage VG5 rises, is the gate voltage of the Nmos tube NM5, generates a current I2, flows into NM5 through R2 and generates a feedback voltage VP, and is pulled down as VG5 rises;

and 4, step 4: when the power supply is in overvoltage, the NM4 increases the voltage VP to protect the grid of the MOS transistor PM6 from being damaged under the condition of overvoltage of the power supply;

and 5: the feedback voltage VP is used as the grid voltage of the Pmos tube PM6, and as VP decreases, a feedback current I3 is generated in the PM 6;

step 6: the substrate potential of the PM6 is connected with the source end, and the source end of the PM6 is used as VREF for output;

and 7: the value of VREF is adjusted by adjusting the proportion of R1 and R2.

Further, the step 5 comprises the following specific steps:

step 5.1: when VDDH starts to be powered up, a voltage drop is generated on R1, NM1, NM2, NM3 and R3 start to be conducted, and current I1 increases;

step 5.2: the node voltage drop VG4, VG5 increases, VG5 makes NM5 conductive, current I2 is generated, and flows through R2 and NM 5;

step 5.3: as VDDH rises, VREF rises, VG5 rises, I2 increases, node drop VP decreases, PM6 is turned on, and current I3 increases;

step 5.4: the current at node VREF begins to bleed off, keeping the increased VREF drop constant, and the high voltage drop of the circuit is all borne by R1.

Further, the step 4 comprises the following specific steps:

step 4.1, when VDDH continues to rise and reaches the limit of current leakage of PM6, the working voltage limit of the circuit is reached;

step 4.2: when the circuit reaches the working voltage limit, VDDH continues to rise, VREF begins to rise, the node VG4 rises to enable NM4 to be conducted, the node VP rises to form protection, and the grid electrode of PM6 is not broken down by overvoltage.

The voltage reference circuit and the method for realizing high-voltage application by using the low-voltage process device have the following advantages that:

compared with the traditional structure, the voltage reference structure of the high-voltage power supply with the tolerance of more than 100V can be generated, a high-voltage process is not needed, additional special devices are not needed, and the purposes of high-voltage resistance, voltage reduction and voltage stabilization are achieved. The characteristics of low cost and convenient design are met.

The invention has simple structure, easy realization and low process requirement. Therefore, the chip has high use value and application value when applied in a high-voltage scene, and is suitable for popularization.

Drawings

Fig. 1 is a schematic diagram of a conventional power-independent reference voltage circuit.

Fig. 2 is a schematic diagram of a voltage reference circuit for high voltage applications using low voltage process devices in accordance with the present invention.

Fig. 3 is a diagram of VREF and VDDH simulation waveforms for a conventional power-independent reference voltage circuit.

Fig. 4 is a simulation waveform diagram of VREF and high voltage VDDH according to an embodiment of the present invention.

Detailed Description

For a better understanding of the objects, structure and function of the present invention, a voltage reference circuit and method for high voltage applications using low voltage process devices will be described in detail with reference to the accompanying drawings.

As shown in fig. 2, the circuit for realizing a high-voltage tolerant power reference suitable for a low-voltage device of the invention includes a resistor R1 connected to a high-voltage power supply, a POS terminal of R1 connected to the high-voltage power supply, a Neg terminal of R1 connected to a drain terminal of NM1, a drain terminal of NM4, a POS terminal of R3, and a source terminal of PM 6. The NM1 adopts a diode connection method, the source end of the NM1 is connected with the drain end of NM2, the NM2 adopts a diode connection method, the source end of the NM2 is connected with the drain end of NM3, the NM3 adopts a diode connection method, the source end of the NM3 is connected with the POS end of the resistor R2, and the Neg end of the resistor R2 is connected with the common ground end. The grid of NM4 is connected with the drain of NM2, the source is connected with the Neg of R3, and the protective circuit is used as an overvoltage protective tube, so that the protective circuit can not be damaged by high voltage exceeding the upper limit of the circuit design. Neg of the R3 is connected with the drain terminal of the NM5, the grid of the NM5 is connected with the drain terminal of the NM3, and the source terminal of the NM5 is connected with the common ground terminal to serve as a feedback branch. The PM6 is used as the most main current feedback tube, the grid electrode of the PM6 is connected with the drain terminal of the NM5, and the drain terminal is connected with the common ground terminal. The Neg terminal of R1 is used as the VREF signal output terminal.

The voltage stabilizing circuit comprises NM 1-NM 4, PM6, R1 and R3, wherein the NM 1-NM 4 is a low-voltage 3.3V process NMOS device, the PM6 is a 3.3V process PMOS device, the R1 is a resistor for achieving a voltage-resistant function of the circuit, the R2 is a bias resistor, and the R3 is a feedback network resistor.

The invention provides a method for realizing a high-voltage-resistant power reference suitable for a low-voltage device, which comprises the following working steps of:

(1) the voltage VH input from the high-voltage power supply voltage input end VDDH is converted into current through a resistor R1 and is divided into branch currents I1, I2 and I3;

(2) the high-voltage power supply voltage input end VDDH starts to be electrified, voltage drop is generated on R1, voltage VREF is generated, meanwhile diode-connected Nmos tubes NM1, NM2, NM3 and R3 are conducted to generate current I1, and bias voltages VG4 and VG5 are generated;

(3) the bias voltage VG5 rises, is the gate voltage of the Nmos tube NM5, generates a current I2, flows into NM5 through R2 and generates a feedback voltage VP, and is pulled down as VG5 rises.

(4) The NM4 is used as a circuit overvoltage protection tube, which can increase the voltage VP when the power supply is in overvoltage, and protect the grid of the MOS tube PM6 from being damaged under the condition of overvoltage of the power supply.

(5) The feedback voltage VP is used as the gate voltage of the Pmos tube PM6, and as VP decreases, a feedback current I3 is generated in the PM 6. The current makes PM6 become a variable resistance resistor, whose resistance value has a variation trend opposite to that of VREF, and is used as a core device for ensuring VREF to be stable.

(6) The substrate potential of PM6 is connected to the source terminal. The turn-on voltage of PM6 is guaranteed to operate normally without being affected by the substrate bias effect. The source terminal of PM6 connected to R1 is output as VREF.

(7) The value of VREF can be adjusted by adjusting the proportion of R1 and R2.

Specifically, in step (5):

(A1) when VDDH starts to power up, a voltage drop is generated on R1, NM1, NM2, NM3, and R3 start to conduct, and current I1 increases.

(A2) The node voltage drop VG4, VG5 increases, VG5 turns NM5 on, generating a current I2, which flows through R2 and NM 5.

(A3) As VDDH rises, VREF rises, VG5 rises, and I2 increases. The node voltage drop VP decreases, turning PM6 on and increasing current I3.

(A4) The current at node VREF begins to bleed off, keeping the increased VREF drop constant. The high voltage drop of the circuit is borne by the R1. All low-voltage devices, namely MOS tubes, have no high voltage.

Further, in step (4):

(B1) when VDDH continues to rise and the current regulation capability of PM6 is insufficient to continue to lower VREF, the limit of current leakage of PM6 is reached, i.e., the operating voltage limit of the circuit.

(B2) At this time, VDDH continues to rise, VREF starts to rise, the node VG4 rises to turn on NM4, and the node VP rises to form protection, so that the gate of PM6 is not damaged by the over-voltage breakdown.

The invention utilizes the current feedback structure formed by low-voltage 3.3V devices to form a variable impedance structure, clamps high voltage on a resistor device which is not easy to break down, and realizes that all low-voltage devices are used, and the result is shown in figure 4. Comparing the simulation result of the conventional structure shown in fig. 3, it can be seen that VREF can be kept stable when the power voltage is raised to 2.4V, but when the power voltage continues to be raised, the VREF curve has already started to warp, and when the withstand voltage of the present process is exceeded by 3.3V, VREF has already obviously started to follow VDDH, losing the circuit function.

The comparison shows that compared with the traditional structure, the voltage reference structure of the high-voltage power supply with the tolerance of more than 100V can be generated, a high-voltage process is not needed, extra special devices are not needed, and the purposes of high-voltage resistance, voltage reduction and voltage stabilization are achieved. The characteristics of low cost and convenient design are met.

It is to be understood that the present invention has been described with reference to certain embodiments, and that various changes in the features and embodiments, or equivalent substitutions may be made therein by those skilled in the art without departing from the spirit and scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from the essential scope thereof. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed, but that the invention will include all embodiments falling within the scope of the appended claims.

Claims

1. A power supply reference circuit suitable for realizing high voltage resistance of a low-voltage device is characterized by comprising a resistor R1 connected with a high-voltage power supply, wherein the POS end of the R1 is connected with the high-voltage power supply, the Neg end of the R1 is connected with the drain end of NM1, the drain end of NM4, the Pos end of R3 and the source end of PM 6; the NM1, NM2 and NM3 are connected in a diode mode, the source end of NM1 is connected with the drain end of NM2, the source end of NM2 is connected with the drain end of NM3, the source end of NM3 is connected with the POS end of a resistor R2, and the Neg end of R2 is connected with a common ground end; the gate of the NM4 is connected with the drain of the NM2, the source of the NM4 is connected with the Neg of the R3, the Neg of the R3 is connected with the drain of the NM5, the gate of the NM5 is connected with the drain of the NM3, and the source of the NM5 is connected with the common ground end to serve as a feedback branch; the grid electrode of the PM6 is connected with the drain terminal of the NM5, and the drain terminal is connected with the common ground terminal; the Neg terminal of R1 is used as the VREF signal output terminal.

2. The power reference circuit suitable for low voltage devices to realize high voltage endurance as claimed in claim 1, wherein NM1, NM2, NM3, NM4 are low voltage 3.3V process NMOS devices, PM6 is 3.3V process PMOS devices, R1 is a resistor for realizing voltage endurance function of the circuit, R2 is a bias resistor, and R3 is a feedback network resistor.

3. A method for implementing a high voltage tolerant power supply using a circuit according to claim 1 or 2, comprising the steps of:

step 1.1: the high-voltage power supply voltage input end VDDH starts to be electrified, voltage drop is generated on R1, voltage VREF is generated, meanwhile diode-connected Nmos tubes NM1, NM2, NM3 and R3 are conducted to generate current I1, and bias voltages VG4 and VG5 are generated;

step 1.2: the current I1 increases, the bias voltage VG5 increases, the gate voltage of the Nmos transistor NM5 generates the current I2, flows into NM5 through R2 and generates the feedback voltage VP, and is pulled down as VG5 increases;

step 1.3: as VDDH rises, VREF rises, VG5 rises, I2 increases, node drop VP decreases, VP serves as the gate voltage of Pmos pipe PM6, and as VP decreases, feedback current I3 is generated in PM 6;

step 1.4: the current I3 is increased, the current of the node VREF begins to be discharged, the increased VREF is reduced and kept unchanged, and the high-voltage drop of the circuit is borne by the R1;

and 2, step: when the power supply is in overvoltage, the NM4 increases the voltage VP to protect the grid of the MOS transistor PM6 from being damaged under the condition of overvoltage of the power supply;

and step 3: the substrate potential of the PM6 is connected with the source end, and the source end of the PM6 is used as VREF for output;

and 4, step 4: the value of VREF is adjusted by adjusting the proportion of R1 and R2.

4. The method for realizing the high voltage tolerant power supply according to claim 3, wherein the step 2 comprises the following specific steps:

step 2.1: when VDDH continues to rise, the limit of current bleeding of PM6 is reached, i.e. the operating voltage limit of the circuit is reached;

step 2.2: when the circuit reaches the working voltage limit, VDDH continues to rise, VREF begins to rise, the node VG4 rises to enable NM4 to be conducted, the node VP rises to form protection, and the grid electrode of PM6 is not broken down by overvoltage.