CN116417341A - LDMOS device and preparation method thereof - Google Patents

LDMOS device and preparation method thereof Download PDF

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Publication number
CN116417341A
CN116417341A CN202111675159.XA CN202111675159A CN116417341A CN 116417341 A CN116417341 A CN 116417341A CN 202111675159 A CN202111675159 A CN 202111675159A CN 116417341 A CN116417341 A CN 116417341A
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conductivity type
region
forming
drift region
conductivity
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何乃龙
张森
王浩
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CSMC Technologies Fab2 Co Ltd
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CSMC Technologies Fab2 Co Ltd
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Priority to CN202111675159.XA priority Critical patent/CN116417341A/en
Priority to PCT/CN2022/134065 priority patent/WO2023124670A1/en
Publication of CN116417341A publication Critical patent/CN116417341A/en
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623—Buried supplementary region, e.g. buried guard ring
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors

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Abstract

The invention relates to a preparation method of an LDMOS device and the LDMOS device. The preparation method of the LDMOS device comprises the following steps: forming a drift region of a first conductivity type; forming a buried layer of a second conductivity type in the drift region of the first conductivity type; and forming a first-conductivity-type channel region in the first-conductivity-type drift region, wherein the first-conductivity-type channel region is positioned above the second-conductivity-type buried layer and is adjacent to the second-conductivity-type buried layer, and the area of the first-conductivity-type channel region is larger than that of the second-conductivity-type buried layer. By forming the first-conductivity-type channel region and the second-conductivity-type buried layer in the first-conductivity-type drift region and making the area of the first-conductivity-type channel region larger than the area of the second-conductivity-type buried layer, the effect that the on-resistance of the device can be further reduced while the breakdown voltage is improved is achieved.

Description

LDMOS device and preparation method thereof
Technical Field
The application relates to the technical field of integrated circuits, in particular to a preparation method of an LDMOS device and the LDMOS device.
Background
With the development of semiconductor technology, the performance requirements of integrated circuits on semiconductor devices are increasing. For some semiconductor devices, the on-state voltage Vt, the on-state resistance Rdson, the saturation current Idsat, the off-state breakdown voltage BVoff, and the like are key parameters. Wherein the specific on-resistance (Ron, sp) of the drift region has a contradictory relationship with the device breakdown voltage (Breakdown Voltage, BV): ron, sp.alpha.BV.beta. That is, the on-resistance and the device breakdown voltage are a pair of "tees" which are not compatible. How to alleviate the contradiction between the on-resistance and the breakdown voltage of the device, that is, how to effectively improve the withstand voltage and reduce the on-resistance is always a problem to be solved by those skilled in the art.
Disclosure of Invention
Based on this, it is necessary to provide a method for manufacturing an LDMOS device and an LDMOS device for solving the problem that the on-resistance cannot be reduced on the premise of increasing the breakdown voltage in the prior art.
In order to achieve the above object, in one aspect, the present invention provides a method for manufacturing an LDMOS device, including the steps of:
providing a substrate of a second conductivity type;
forming a drift region of a first conductivity type, the drift region of the first conductivity type being formed in a substrate of a second conductivity type;
forming a buried layer of a second conductivity type in the drift region of the first conductivity type;
and forming a first-conductivity-type channel region in the first-conductivity-type drift region, wherein the first-conductivity-type channel region is positioned above the second-conductivity-type buried layer, and the area of the first-conductivity-type channel region is larger than that of the second-conductivity-type buried layer.
According to the preparation method of the LDMOS device, the channel region of the first conductivity type and the buried layer of the second conductivity type are formed in the drift region of the first conductivity type, and the area of the channel region of the first conductivity type is larger than that of the buried layer of the second conductivity type, so that the channel region of the first conductivity type is prevented from being wrapped by the buried layer of the second conductivity type in the heat treatment process, and the effect that the on-resistance of the device can be further reduced while the breakdown voltage of the device is improved is achieved.
In one embodiment, a buried layer of a second conductivity type is formed within the drift region of the first conductivity type; forming a channel region of the first conductivity type within the drift region of the first conductivity type, further comprising:
the sum of the amount of dopant forming the drift region of the first conductivity type and the amount of dopant forming the channel region of the first conductivity type is greater than the amount of dopant forming the buried layer of the second conductivity type.
In one embodiment, after forming the drift region of the first conductivity type, the method further comprises the steps of:
forming a well region of a second conductivity type in the substrate; the well region of the second conductivity type is positioned at one side of the drift region of the first conductivity type and is adjacent to or spaced apart from the drift region of the first conductivity type;
forming a buffer region of a first conductivity type in the substrate, wherein the buffer region of the first conductivity type is positioned on one side of the drift region of the first conductivity type, which is far away from the well region of the second conductivity type, and is adjacent to the drift region of the first conductivity type;
forming a dielectric layer on the substrate, wherein the dielectric layer covers the drift region of the first conductivity type;
forming a grid on the surface of the well region of the second conductivity type and the surface of the dielectric layer, wherein the grid extends from the well region of the second conductivity type to the surface of the dielectric layer;
forming a source region and a body region leading-out region of the second conductivity type in the well region of the second conductivity type, and forming a drain region in the buffer region of the first conductivity type; the source region has a distance from the drift region of the first conductivity type, and the body region lead-out region of the second conductivity type is located on a side of the source region away from the drift region of the first conductivity type and is adjacent to the source region.
In one embodiment, forming a buried layer of a second conductivity type in a drift region of a first conductivity type includes the steps of:
forming a first patterned mask layer on the drift region of the first conductivity type, wherein a first opening is formed in the first patterned mask layer, and the first opening defines the shape and the position of the buried layer of the second conductivity type;
ion implantation of the second conductivity type is performed in the drift region of the first conductivity type based on the first patterned mask layer, so that a buried layer of the second conductivity type is formed in the drift region of the first conductivity type.
In one embodiment, forming a channel region of a first conductivity type within a drift region of the first conductivity type comprises the steps of:
forming a second patterned mask layer on the drift region of the first conductivity type, wherein a second opening is formed in the second patterned mask layer, the second opening defines the shape and the position of the channel region of the first conductivity type, and the area of the second opening is larger than that of the first opening;
performing ion implantation of the first conductivity type in the drift region of the first conductivity type based on the second patterned mask layer to form a channel region of the first conductivity type in the drift region of the first conductivity type;
and removing the second patterned mask layer.
In one embodiment, a second patterned mask layer is formed on the drift region of the first conductivity type, a second opening is formed in the second patterned mask layer, the second opening defines a shape and a position of the channel region of the first conductivity type, and an area of the second opening is larger than an area of the first opening, including:
and thinning the first patterned mask layer, and expanding the first opening to obtain a second patterned mask layer with a second opening.
The invention also provides an LDMOS device, which comprises:
a substrate of a second conductivity type;
a drift region of the first conductivity type within the substrate of the second conductivity type;
a buried layer of a second conductivity type located within the drift region of the first conductivity type;
and a channel region of the first conductivity type located in the drift region above the buried layer of the second conductivity type, the area of the channel region of the first conductivity type being larger than the area of the buried layer of the second conductivity type.
The area of the channel region of the first conductivity type of the LDMOS device is larger than that of the buried layer of the second conductivity type, so that the channel region of the first conductivity type is prevented from being wrapped by the buried layer of the second conductivity type in the heat treatment process, and the effect that the on-resistance of the device can be further reduced while the breakdown voltage of the device is improved is achieved.
In one embodiment, the sum of the amount of dopant forming the drift region of the first conductivity type and the amount of dopant forming the channel region of the first conductivity type is greater than the amount of dopant forming the buried layer of the second conductivity type.
In one embodiment, the semiconductor device further comprises a well region of the second conductivity type, and a source region of the first conductivity type and a body region extraction region of the second conductivity type formed in the well region of the second conductivity type, the source region of the first conductivity type being adjacent to the body region extraction region of the second conductivity type;
a buffer region of the first conductivity type and a drain region of the first conductivity type, the drain region of the first conductivity type being located within the buffer region of the first conductivity type, the buffer region of the first conductivity type being located on the other side of the drift region of the first conductivity type and being contiguous with the drift region of the first conductivity type;
the dielectric layer covers the drift region of the first conductivity type;
and the grid electrode is formed on the surface of the well region of the second conductivity type and the surface of the dielectric layer and extends from the well region of the second conductivity type to the surface of the dielectric layer.
In one embodiment, the channel region of the first conductivity type adjoins the buried layer of the second conductivity type.
Drawings
In order to more clearly illustrate the technical solutions of embodiments or conventional techniques of the present application, the drawings required for the descriptions of the embodiments or conventional techniques will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person of ordinary skill in the art.
Fig. 1 is a first schematic flow chart of a method for manufacturing an LDMOS device provided in an embodiment;
fig. 2 is a second schematic flow chart of a method for fabricating an LDMOS device provided in an embodiment;
fig. 3 is a schematic flow chart of a step of forming a buried layer of a second conductivity type in a drift region of a first conductivity type in an embodiment;
FIG. 4 is a schematic flow chart of a step of forming a channel region of a first conductivity type in a drift region of the first conductivity type in one embodiment;
FIG. 5 is a schematic diagram of a first patterned mask layer defining a buried layer of a second conductivity type according to an embodiment;
FIG. 6 is a schematic diagram of a second patterned mask layer defining a channel region of a first conductivity type according to one embodiment;
fig. 7 is a schematic cross-sectional structure of an LDMOS device provided in an embodiment;
reference numerals illustrate: 60, a first patterned mask layer; 70, a second patterned mask layer; 610 a drift region of a first conductivity type; 620, a buried layer of a second conductivity type; 630, a channel region of the first conductivity type; 640, a substrate of a second conductivity type; 650, a well region of a second conductivity type; 660, a source region of a first conductivity type; 670, a body region lead-out region of a second conductivity type; 680, a buffer region of a first conductivity type; 690, a drain region of the first conductivity type; 700, a dielectric layer; 710, gate.
Detailed Description
In order to facilitate an understanding of the present application, a more complete description of the present application will now be provided with reference to the relevant figures. Examples of the present application are given in the accompanying drawings. This application may, however, be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
It will be understood that when an element or layer is referred to as being "on," abutting, "" within, "or" other elements or layers, it can be directly on, adjacent to, connected to, or coupled to the other elements or layers, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and/or sections, these elements, components, regions, layers, doping types and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or section from another element, component, region, layer, doping type or section. Thus, a first element, component, region, layer, doping type or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention; for example, the first doping type may be made the second doping type, and similarly, the second doping type may be made the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.
Spatially relative terms, such as "under", "below", "beneath", "under", "above", "over" and the like, may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. Furthermore, the device may also include an additional orientation (e.g., rotated 90 degrees or other orientations) and the spatial descriptors used herein interpreted accordingly.
As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," and/or the like, specify the presence of stated features, integers, steps, operations, elements, components, or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof. Also, in this specification, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention, such that variations of the illustrated shapes due to, for example, manufacturing techniques and/or tolerances are to be expected. Thus, embodiments of the present invention should not be limited to the particular shapes of the regions illustrated herein, but rather include deviations in shapes that result, for example, from manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted regions. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface over which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the invention.
The inventors have found that the breakdown voltage of a semiconductor device can be increased by using triple resurf (triple reduced surface electric field) structures. For a triple resurf device, taking an NLDMOS device as an example, the device breakdown voltage can be raised, but the current path is lost, which is unfavorable for the reduction of the on-resistance value. The current mostly goes through the N-type channel above the buried layer, and in order to further reduce the on-resistance of the device, when the triple resurf is performed, an N-type doped top layer is injected into a region after the P-type buried layer is injected, so that the concentration of the surface N-type channel is increased, and the on-resistance is reduced. The inventors have studied again to find that this example still does not effectively reduce the on-resistance of the device while increasing the breakdown voltage.
To this end, the applicant has provided a method of fabricating an LDMOS device to overcome the above-mentioned problems.
Referring to fig. 1, the invention provides a method for manufacturing an LDMOS device, which comprises the following steps:
s100, providing a substrate of a second conductivity type;
in particular, the substrate may be at least one of the following mentioned materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (SSiGeOI), silicon-germanium-on-insulator (SiGeOI), germanium-on-insulator (GeOI), and the like. In one embodiment, the substrate is a silicon substrate having a second conductivity type and is doped with a P-type impurity such as boron ions.
S110, forming a drift region of a first conductivity type, wherein the drift region of the first conductivity type is formed in a substrate of a second conductivity type;
specifically, the drift region may be formed by any means in the art. The drift region of the first conductivity type has dopant ions of the first conductivity type therein, and in one particular example, ion implantation may be performed on the substrate of the second conductivity type to form the drift region of the first conductivity type. Illustratively, the first conductivity type is N-type and the second conductivity type is P-type. Wherein the P-type doping ions include, but are not limited to, boron ions, and the N-type doping ions include, but are not limited to, phosphorus ions or arsenic ions.
S120, forming a buried layer of a second conductivity type in the drift region of the first conductivity type;
specifically, the buried layer of the second conductivity type may be formed by performing implantation or diffusion of dopant ions of the second conductivity type into the drift region. It should be noted that the buried layer of the second conductivity type may be formed by any other means in the art, which is not described herein.
And S130, forming a first-conductivity-type channel region in the first-conductivity-type drift region, wherein the first-conductivity-type channel region is positioned above the second-conductivity-type buried layer, and the area of the first-conductivity-type channel region is larger than that of the second-conductivity-type buried layer.
The first conductive type channel region may be a buried layer located above the second conductive type buried layer, or may be a first conductive type drift region located above the second conductive type buried layer to increase ion concentration to form the first conductive type channel region.
Specifically, the concentration of the ions of the first conductivity type on the surface can be increased through the channel region of the first conductivity type, so that the on-resistance is effectively reduced. Taking the first conductivity type as an N-type example, after the buried layer of the second conductivity type and the channel region of the first conductivity type are implanted, the boron ions can be laterally spread and upwards spread to wrap the surface N-type channel due to quicker thermal diffusion, so that the current channel is narrowed. By making the area of the channel region of the first conductivity type larger than the broadband of the buried layer of the second conductivity type, the channel region of the first conductivity type does not wrap around the channel region of the second conductivity type in the event of thermal diffusion. Optionally, the buried layer of the second conductivity type may be adjacent to the channel region of the first conductivity type, or may be disposed at intervals; in a specific example, the buried layer of the second conductivity type is disposed adjacent to the channel region of the first conductivity type, and by this adjacent disposition, the on-resistance can be reduced to the maximum extent while the breakdown voltage is increased.
Alternatively, the area of the channel region of the first conductivity type is larger than the area of the buried layer of the second conductivity type, and the length of the channel region of the first conductivity type is larger than the length of the buried layer of the second conductivity type, and the width of the channel region of the first conductivity type is larger than the width of the buried layer of the second conductivity type. The dimension of the channel region of the first conductivity type in the device conductive channel length direction may be larger than the dimension of the buried layer of the second conductivity type in the device conductive channel length direction, which is the device source-drain direction.
Further, the area of the channel region of the first conductivity type may be made larger than the area of the buried layer of the second conductivity type by any means in the art, for example, when the shape and position of the buried layer of the second conductivity type are defined by using the first patterned mask layer and the shape and position of the channel region of the first conductivity type are defined by using the second patterned mask layer, the mask layer is processed such that the area of the opening of the first patterned mask layer is larger than the area of the opening of the second patterned mask layer. In one embodiment, a buried layer of a second conductivity type is formed within the drift region of the first conductivity type; forming a channel region of the first conductivity type within the drift region of the first conductivity type, further comprising: the sum of the amount of dopant forming the drift region of the first conductivity type and the amount of dopant forming the channel region of the first conductivity type is greater than the amount of dopant forming the buried layer of the second conductivity type.
According to the preparation method of the LDMOS device, the channel region of the first conductivity type and the buried layer of the second conductivity type are formed in the drift region of the first conductivity type, and the area of the channel region of the first conductivity type is larger than that of the buried layer of the second conductivity type, so that the channel region of the first conductivity type is prevented from being wrapped by the buried layer of the second conductivity type in the heat treatment process, and the effect that the on-resistance of the device can be further reduced while the breakdown voltage of the device is improved is achieved.
In one embodiment, as shown in fig. 2, the step of forming the drift region of the first conductivity type further comprises:
s111, forming a well region of a second conductivity type in the substrate; the well region of the second conductivity type is positioned at one side of the drift region of the first conductivity type and is adjacent to or spaced apart from the drift region of the first conductivity type;
specifically, a well region may be formed on a substrate by ion implantation. It should be noted that, the well region of the second conductivity type is disposed adjacent to the drift region of the first conductivity type, and the on-resistance can be reduced and the device size can be reduced compared to the case where the well region of the second conductivity type is disposed at intervals. The well region of the second conductivity type is spaced apart from the drift region of the first conductivity type, which may increase the absolute breakdown voltage of the device compared to an adjacent arrangement. In one specific example, the well regions of the two conductivity types are spaced apart from the drift region of the first conductivity type.
Further, forming the well region of the second conductivity type in the substrate may include the steps of:
s21: forming an injection blocking layer on the surface of the substrate, wherein the injection blocking layer is provided with an opening, and the opening exposes the substrate;
s22: ion implantation is performed on the substrate based on the implantation barrier layer to form a well region in the substrate.
The step S22 further includes the following steps:
s23: the implantation barrier layer is removed.
The step S22 further includes the following steps:
s24: and annealing the substrate after ion implantation. The annealing treatment can repair lattice loss on the substrate in the ion implantation process and activate doped ions; specifically, the rapid thermal annealing (Rapid thermal Annealing, RTA) process can be adopted to anneal the ion implanted substrate, and compared with the common annealing process, the rapid thermal annealing process has short annealing time, can avoid the diffusion of doped ions caused by long-time high temperature, and can reduce the instant enhancement diffusion of the doped ions.
S113, forming a buffer region of a first conductivity type in the substrate, wherein the buffer region of the first conductivity type is positioned on one side of the drift region of the first conductivity type, which is far away from the well region of the second conductivity type, and is adjacent to the drift region of the first conductivity type;
specifically, the buffer region of the first conductivity type and the well region of the second conductivity type are respectively located at two sides of the drift region, and the buffer region of the first conductivity type and the well region of the second conductivity type are adjacent to the drift region of the first conductivity type.
S115, forming a dielectric layer on the substrate, wherein the dielectric layer covers the drift region of the first conductivity type;
in one specific example, the dielectric layer may be a field oxide layer, which may be an oxide of silicon.
S117, forming a grid on the surface of the well region of the second conductivity type and the surface of the dielectric layer, wherein the grid extends from the well region of the second conductivity type to the surface of the dielectric layer;
s119, forming a source region and a body region leading-out region of the second conductivity type in the well region of the second conductivity type, and forming a drain region in the buffer region of the first conductivity type; the source region has a distance from the drift region of the first conductivity type, and the body region lead-out region of the second conductivity type is located on a side of the source region away from the drift region of the first conductivity type and is adjacent to the source region.
Specifically, a dielectric layer is disposed over the drift region of the first conductivity type, the dielectric layer separating the source region and the drain region. The drain region and the drift region of the first conductivity type may be disposed adjacent to each other or may be disposed at intervals. In one specific example, the drain region is disposed adjacent to the drift region of the first conductivity type. It should be noted that, unless explicitly stated herein, the steps are not strictly limited to the order of execution, and the steps may be executed in other orders.
In one embodiment, as shown in fig. 3, forming a buried layer of a second conductivity type in a drift region of a first conductivity type, includes the steps of:
s310, forming a first patterned mask layer on the drift region of the first conductivity type, wherein a first opening is formed in the first patterned mask layer, and the first opening defines the shape and the position of the buried layer of the second conductivity type;
the size and the position of the first opening of the first patterned mask layer may be designed according to the buried layer of the second conductivity type of the actual LDMOS device.
S320, performing ion implantation of the second conductivity type in the drift region of the first conductivity type based on the first patterned mask layer to form a buried layer of the second conductivity type in the drift region of the first conductivity type.
In one embodiment, as shown in fig. 4, forming a channel region of a first conductivity type within a drift region of the first conductivity type, comprises:
s410, forming a second patterned mask layer on the drift region of the first conductivity type, wherein a second opening is formed in the second patterned mask layer, the second opening defines the shape and the position of the channel region of the first conductivity type, and the area of the second opening is larger than that of the first opening;
s420, performing ion implantation of the first conductivity type in the drift region of the first conductivity type based on the second patterned mask layer to form a channel region of the first conductivity type in the drift region of the first conductivity type;
s430, removing the second patterned mask layer.
Specifically, the second image mask layer may be obtained by exposing and developing the first patterned mask layer, or may be formed again after removing the first patterned mask layer. In a specific example, as shown in fig. 5 and fig. 6 (in which fig. 5 is a schematic view of the first patterned mask layer 60 defining the buried layer 620 of the second conductivity type, and fig. 6 is a schematic view of the second patterned mask layer 70 defining the channel region 630 of the first conductivity type), the second patterned mask layer 70 is obtained by thinning the first patterned mask layer 60, so that the area of the second opening is larger than that of the first opening, and in fig. 5 and fig. 6, the width of the second opening is larger than that of the second opening. In one embodiment, a second patterned mask layer is formed on the drift region of the first conductivity type, a second opening is formed in the second patterned mask layer, the second opening defines a shape and a position of the channel region of the first conductivity type, and an area of the second opening is larger than an area of the first opening, including: and thinning the first patterned mask layer, and expanding the first opening to obtain a second patterned mask layer with a second opening. By the mode, on the premise that the area of the channel region of the first conductivity type is larger than that of the buried layer of the second conductivity type, the process cost is saved.
The area of the second opening is larger than that of the first opening, so that the area of the channel region of the first conductivity type after ion implantation is larger than that of the buried layer of the second conductivity type. And the first graphical and second graphical mask layers are made of photoresist, and after ion implantation is completed, the mask layers are removed by adopting a wet photoresist removing or ashing process.
It should be understood that, although the steps in the flowcharts of fig. 1-4 are shown in order as indicated by the arrows, these steps are not necessarily performed in order as indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least some of the steps in FIGS. 1-4 may include multiple steps or stages that are not necessarily performed at the same time, but may be performed at different times, nor do the order in which the steps or stages are performed necessarily performed in sequence, but may be performed alternately or alternately with at least a portion of the steps or stages in other steps or other steps.
In one embodiment, referring to fig. 7 (fig. 7 is an example of an NLDMOS device), an LDMOS device is provided, comprising:
a substrate 640 of a second conductivity type;
a drift region 610 of the first conductivity type within a substrate 640 of the second conductivity type;
a buried layer 620 of the second conductivity type; a buried layer 620 of the second conductivity type is located within the drift region 610 of the first conductivity type;
a channel region 630 of the first conductivity type; the channel region 630 of the first conductivity type is located in the drift region above the buried layer 620 of the second conductivity type; the area of the channel region 630 of the first conductivity type is larger than the area of the buried layer 620 of the second conductivity type.
Specifically, the concentration of the ions of the first conductivity type on the surface can be increased through the channel region of the first conductivity type, so that the on-resistance is effectively reduced. Taking the first conductivity type as an N-type example, after the buried layer of the second conductivity type and the channel region of the first conductivity type are implanted, the boron ions can be laterally spread and upwards spread to wrap the surface N-type channel due to quicker thermal diffusion, so that the current channel is narrowed. By making the area of the channel region of the first conductivity type larger than the broadband of the buried layer of the second conductivity type, the channel region of the first conductivity type does not encase the channel region of the second conductivity type in the event of thermal diffusion. It should be noted that, when the LDMOS device is a PLDMOS device, the first conductivity type is P-type, and the second conductivity type is N-type.
The channel region of the first conductivity type may be a buried layer located above the buried layer of the second conductivity type, or the first conductivity type drift region located on the buried layer of the second conductivity type may be increased in ion concentration to form the channel region of the first conductivity type. Optionally, the buried layer of the second conductivity type may be adjacent to the channel region of the first conductivity type, or may be disposed at intervals; in a specific example, the buried layer of the second conductivity type is disposed adjacent to the channel region of the first conductivity type, and by this adjacent disposition, the on-resistance can be reduced to the maximum extent while the breakdown voltage is increased. In one embodiment, the channel region of the first conductivity type adjoins the buried layer of the second conductivity type.
In a specific example, the sum of the amount of dopant forming the drift region of the first conductivity type and the amount of dopant forming the channel region of the first conductivity type is greater than the amount of dopant forming the buried layer of the second conductivity type.
According to the LDMOS device, the area of the channel region of the first conductivity type is larger than that of the buried layer of the second conductivity type, so that the channel region of the first conductivity type is prevented from being wrapped by the buried layer of the second conductivity type in the heat treatment process, and the effect that the on-resistance of the device can be further reduced while the breakdown voltage of the device is improved is achieved.
In one embodiment, please continue to refer to fig. 7, further comprising a well region 650 of the second conductivity type, and a source region 660 of the first conductivity type and a body region extraction region 670 of the second conductivity type formed in the well region 650 of the second conductivity type; the source region 660 of the first conductivity type adjoins the body region lead-out region 670 of the second conductivity type;
a buffer region 680 of the first conductivity type and a drain region 690 of the first conductivity type; a drain region 690 of the first conductivity type is located within the buffer region 680 of the first conductivity type;
the buffer region 680 of the first conductivity type is located at the other side of the drift region 610 of the first conductivity type and is adjacent to the drift region 610 of the first conductivity type;
a dielectric layer 700, the dielectric layer 700 covering the drift region 610 of the first conductivity type;
a gate electrode 710, wherein the gate electrode 710 is formed on the surface of the well region 650 of the second conductivity type and the surface of the dielectric layer 700, and extends from the well region 650 of the second conductivity type to the surface of the dielectric layer 700;
specifically, the body region lead-out region may be located on a side of the source region away from the gate electrode, or may be juxtaposed with the source region in the width direction of the device conductive channel and adjacent to the gate electrode.
In one specific example, a dielectric layer is disposed over the drift region of the first conductivity type, the dielectric layer separating the source region and the drain region.
In one specific example, the dielectric layer may be a field oxide layer, which may be an oxide of silicon.
In the description of the present specification, reference to the terms "some embodiments," "other embodiments," "desired embodiments," and the like, means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.
The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features of the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The foregoing examples represent only a few embodiments of the present application, which are described in more detail and are not thereby to be construed as limiting the scope of the claims. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application is to be determined by the claims appended hereto.

Claims (10)

1. The preparation method of the LDMOS device is characterized by comprising the following steps:
providing a substrate of a second conductivity type;
forming a drift region of a first conductivity type, the drift region of the first conductivity type being formed within the substrate of the second conductivity type;
forming a buried layer of a second conductivity type in the drift region of the first conductivity type;
and forming a first-conductivity-type channel region in the first-conductivity-type drift region, wherein the first-conductivity-type channel region is positioned above the second-conductivity-type buried layer, and the area of the first-conductivity-type channel region is larger than that of the second-conductivity-type buried layer.
2. The method of manufacturing an LDMOS device according to claim 1, wherein a buried layer of a second conductivity type is formed in the drift region of the first conductivity type; forming a channel region of the first conductivity type in the drift region of the first conductivity type, further comprising:
the sum of the amount of dopant forming the drift region of the first conductivity type and the amount of dopant forming the channel region of the first conductivity type is greater than the amount of dopant forming the buried layer of the second conductivity type.
3. The method of manufacturing an LDMOS device according to claim 1, wherein after forming the drift region of the first conductivity type, further comprises the steps of:
forming a well region of a second conductivity type in the substrate; the well region of the second conductivity type is positioned at one side of the drift region of the first conductivity type and is adjacent to or spaced from the drift region of the first conductivity type;
forming a buffer region of a first conductivity type in the substrate, wherein the buffer region of the first conductivity type is positioned on one side of the drift region of the first conductivity type, which is far away from the well region of the second conductivity type, and is adjacent to the drift region of the first conductivity type; forming a dielectric layer on the substrate, wherein the dielectric layer covers the drift region of the first conductivity type;
forming a grid on the surface of the well region of the second conductivity type and the surface of the dielectric layer, wherein the grid extends from the well region of the second conductivity type to the surface of the dielectric layer;
forming a source region and a body region leading-out region of the second conductivity type in the well region of the second conductivity type, and forming a drain region in the buffer region of the first conductivity type; the source region has a spacing from the drift region of the first conductivity type, and the body region lead-out region of the second conductivity type is located on a side of the source region remote from the drift region of the first conductivity type and is contiguous with the source region.
4. The method for manufacturing the LDMOS device according to claim 1, wherein forming the buried layer of the second conductivity type in the drift region of the first conductivity type comprises the steps of:
forming a first patterned mask layer on the drift region of the first conductivity type, wherein a first opening is formed in the first patterned mask layer, and the first opening defines the shape and the position of the buried layer of the second conductivity type;
and performing ion implantation of a second conductivity type in the drift region of the first conductivity type based on the first patterned mask layer so as to form a buried layer of the second conductivity type in the drift region of the first conductivity type.
5. The method of manufacturing an LDMOS device according to claim 4, wherein forming a channel region of the first conductivity type in the drift region of the first conductivity type comprises:
forming a second patterned mask layer on the drift region of the first conductivity type, wherein a second opening is formed in the second patterned mask layer, the second opening defines the shape and the position of the channel region of the first conductivity type, and the area of the second opening is larger than that of the first opening;
performing ion implantation of a first conductivity type in the drift region of the first conductivity type based on the second patterned mask layer to form a channel region of the first conductivity type in the drift region of the first conductivity type;
and removing the second patterned mask layer.
6. The method of manufacturing an LDMOS device according to claim 5, wherein forming a second patterned mask layer on the drift region of the first conductivity type, wherein forming a second opening in the second patterned mask layer, wherein the second opening defines a shape and a position of the channel region of the first conductivity type, wherein an area of the second opening is larger than an area of the first opening, comprises:
and thinning the first patterned mask layer, and expanding the first opening to obtain the second patterned mask layer with the second opening.
7. An LDMOS device, comprising:
a substrate of a second conductivity type;
a drift region of a first conductivity type within the second conductivity type substrate;
a buried layer of a second conductivity type located within the drift region of the first conductivity type;
a channel region of a first conductivity type located within the drift region over the buried layer of the second conductivity type, the area of the channel region of the first conductivity type being greater than the area of the buried layer of the second conductivity type.
8. The LDMOS device of claim 7, wherein a sum of a dopant amount forming the drift region of the first conductivity type and a dopant amount forming the channel region of the first conductivity type is greater than a dopant amount forming the buried layer of the second conductivity type.
9. The LDMOS device of claim 7, further comprising a well region of a second conductivity type, and a source region of a first conductivity type and a body region of a second conductivity type formed in the well region of the second conductivity type, the source region of the first conductivity type being contiguous with the body region of the second conductivity type;
a buffer region of a first conductivity type and a drain region of the first conductivity type, the drain region of the first conductivity type being located within the buffer region of the first conductivity type, the buffer region of the first conductivity type being located on the other side of the drift region of the first conductivity type and being contiguous with the drift region of the first conductivity type;
a dielectric layer covering the drift region of the first conductivity type;
and the grid electrode is formed on the surface of the well region of the second conductivity type and the surface of the dielectric layer and extends from the well region of the second conductivity type to the surface of the dielectric layer.
10. The LDMOS device of claim 7, wherein the channel region of the first conductivity type abuts the buried layer of the second conductivity type.
CN202111675159.XA 2021-12-31 2021-12-31 LDMOS device and preparation method thereof Pending CN116417341A (en)

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