CN103730495A - Metal oxide semiconductor device and manufacturing method thereof - Google Patents
Metal oxide semiconductor device and manufacturing method thereof Download PDFInfo
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- CN103730495A CN103730495A CN201210387057.2A CN201210387057A CN103730495A CN 103730495 A CN103730495 A CN 103730495A CN 201210387057 A CN201210387057 A CN 201210387057A CN 103730495 A CN103730495 A CN 103730495A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 229910044991 metal oxide Inorganic materials 0.000 title claims abstract description 12
- 150000004706 metal oxides Chemical class 0.000 title claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 45
- 238000000034 method Methods 0.000 claims description 36
- 238000002955 isolation Methods 0.000 claims description 30
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 12
- 229920005591 polysilicon Polymers 0.000 claims description 12
- 238000009792 diffusion process Methods 0.000 abstract description 4
- 238000000926 separation method Methods 0.000 abstract 2
- 239000010410 layer Substances 0.000 description 77
- 230000012447 hatching Effects 0.000 description 36
- 229910052751 metal Inorganic materials 0.000 description 20
- 239000002184 metal Substances 0.000 description 20
- 230000015572 biosynthetic process Effects 0.000 description 17
- 239000011229 interlayer Substances 0.000 description 17
- 150000002500 ions Chemical class 0.000 description 12
- 229920002120 photoresistant polymer Polymers 0.000 description 12
- 238000000059 patterning Methods 0.000 description 10
- 238000000151 deposition Methods 0.000 description 9
- 230000006872 improvement Effects 0.000 description 9
- INQLNSVYIFCUML-QZTLEVGFSA-N [[(2r,3s,4r,5r)-5-(6-aminopurin-9-yl)-3,4-dihydroxyoxolan-2-yl]methoxy-hydroxyphosphoryl] [(2r,3s,4r,5r)-5-(4-carbamoyl-1,3-thiazol-2-yl)-3,4-dihydroxyoxolan-2-yl]methyl hydrogen phosphate Chemical compound NC(=O)C1=CSC([C@H]2[C@@H]([C@H](O)[C@@H](COP(O)(=O)OP(O)(=O)OC[C@@H]3[C@H]([C@@H](O)[C@@H](O3)N3C4=NC=NC(N)=C4N=C3)O)O2)O)=N1 INQLNSVYIFCUML-QZTLEVGFSA-N 0.000 description 8
- 230000003647 oxidation Effects 0.000 description 8
- 238000007254 oxidation reaction Methods 0.000 description 8
- 238000002513 implantation Methods 0.000 description 6
- 238000004140 cleaning Methods 0.000 description 5
- 230000008021 deposition Effects 0.000 description 5
- 238000001259 photo etching Methods 0.000 description 5
- 230000008859 change Effects 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 238000005381 potential energy Methods 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 230000000630 rising effect Effects 0.000 description 4
- 238000011161 development Methods 0.000 description 3
- 230000018109 developmental process Effects 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- NHDHVHZZCFYRSB-UHFFFAOYSA-N pyriproxyfen Chemical compound C=1C=CC=NC=1OC(C)COC(C=C1)=CC=C1OC1=CC=CC=C1 NHDHVHZZCFYRSB-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000000737 periodic effect Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- UGFAIRIUMAVXCW-UHFFFAOYSA-N Carbon monoxide Chemical compound [O+]#[C-] UGFAIRIUMAVXCW-UHFFFAOYSA-N 0.000 description 1
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 238000010420 art technique Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000002452 interceptive effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 239000002243 precursor Substances 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
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- General Physics & Mathematics (AREA)
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- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses a metal oxide semiconductor device and a manufacturing method thereof. The improved metal oxide semiconductor device comprises a p-substrate, a high-voltage n-well, a first p-well, a second p-well, a disperse p top region and an n-grade region, wherein the high-voltage n-well is arranged in the p-substrate, the first p-well is formed in the p-substrate provided with a first p+ doped region, the second p-well is formed in the HVNW provided with a second p+ doped region adjacent to an n+ doped source electrode region, the disperse p top region is provided with a plurality of p top sections arranged in the HVNW, and the n-grade region is arranged on the disperse p top region; each p top section has a certain distance from the n-grade region so that the distances can be defined, each p top section has a with so that the width can be defined, and each p top section has a separation distance from one adjacent p top section so that the separation distances can be defined. Thus, a p top layer is defined by a series of p-type top diffusion regions which are arranged dispersedly. The invention further provides the manufacturing method for the MOS device.
Description
Technical field
Embodiments of the invention generally relate to a kind of semiconductor device, and particularly relevant for a kind of metal-oxide semiconductor (MOS) (Metal Oxide Semiconductor, MOS) device and manufacture method thereof.
Background technology
Diffused metal oxide emiconductor (DMOS) device be characterized as one source pole district and the back gate region being simultaneously diffused.Transistor channels is by the difference of two diffusions but not a separate type injection forms, and it causes the passage length reducing.Compared with jitty, allow low power consumption and high speed capability.
The surface that Laterally Diffused Metal Oxide Semiconductor (LDMOS) is installed on wafer has its source electrode and a drain electrode, uses and causes a transverse current.Two important parameters on design LDMOS device are puncture voltage and conducting resistance.There is a high-breakdown-voltage and a low on-resistance is preferably, for a kind of device with quite low power consumption is provided during by operation under high voltage.In addition, a low on-resistance provides a higher drain current at this device when saturated, and it is easy to improve the service speed of device.
Fig. 1 shows a kind of plan view of a drift region of known LDMOS device.The LDMOS device 1 of Fig. 1 has one as the LDMOS district 10 of being called by circle showing.LDMOS device 1 is defined by one source pole side 20 and a drain side 30.
Fig. 2 is presented at the plan view in the LDMOS district 10 of being called in Fig. 1.LDMOS district 10 has a plurality of p type diffused layer or p top zone 40 that extend to continuously in fact drain side 30 from source side 20, and a plurality of p top zone 40 is configured in a high voltage N-type well (HVNW).Therefore, known LDMOS district 10 is defined by being configured in N-type rank on a plurality of p top zone 40 (its n rank district 50 not being configured in above any p top layer separates) or the section in n rank district 50.
Fig. 3 A is the profile along Fig. 2 of AA ' hatching.This performance of a kind of known LDMOS has a p substrate 60, in wherein having disposed a HVNW 70.One the one p trap 80 is formed in p substrate 60, and one the 2nd p trap 90 is formed in HVNW 70, and a p trap 80 has a p+ doped region 100, and the 2nd p trap 90 has the p+ doped region 110 of another contiguous n+ doping source region 120.One n+ doped drain region 130 has been formed in HVNW 70.This cross section in LDMOS district 10 is that the n rank district 50 being configured in one of them of a plurality of p top zone 40 represents.The one separated in fact doped region 100,110,120,130, field oxide isolation region 140 that is etched.
The known control gate electrode structure 150 of any known skill may be used in LDMOS device.For example, control gate electrode structure 150 can comprise a conductive layer being configured on a dielectric layer.Control gate electrode structure 150 can comprise a plurality of dielectric side walls clearance walls in addition.One interlayer dielectric (ILD) layer 160 that is etched is to be configured in above defined structure.One first metal level 170 that is etched is provided with one by the contact net (network of contacts) of ILD layer 160.The illustrative known LDMOS of Fig. 2 shows that intermetallic dielectric (IMD) layer 180, one second metal level 190 that is etched is configured on it, uses and provides one by the contact net of IMD layer 180 in addition.
Fig. 3 B is the profile along BB ' hatching of Fig. 2.Except a p top layer is not configured in HVNW 70, this profile of known LDMOS has determined same structure in Fig. 3 A.
High voltage LDMOS device has various uses on semiconductor.For example, LDMOS device may be for becoming quite high voltage transitions quite low voltage or as the power switched transistor that is designed for driving a load.Yet because n rank district and the interactive result of adulterating completely between p type island region, the specific on-resistance of known high voltage LDMOS still may be too high.In known skill, for the LDMOS device of improvement, particularly there is the high voltage LDMOS device of an even lower specific on-resistance, still there is a demand.
Summary of the invention
Embodiments of the invention provide semiconductor device, particularly MOS device.
Of the present invention one implements sample state comprises a mos device, and it comprises: a p substrate; One high voltage n trap (HVNW), is configured in p substrate; One the one p trap, is formed in the p substrate with one the one p+ doped region; One the 2nd p trap, is formed in the HVNW of one the 2nd p+ doped region with a contiguous n+ doping source region; One discrete p top zone, has the p top section in a plurality of HVNW of being configured in; And a n rank district, be configured on discrete p top zone.A plurality of p top section has one section of distance from n rank district to define a plurality of distances, has a width to define a plurality of width, and has one section and one separating distance that is close to p top section to define a plurality of separating distances.In certain embodiments of the present invention, a plurality of distances may be identical, and in some other embodiment of the present invention, a plurality of distances increase gradually.
In one embodiment of this invention, mos device is a LDMOS device, and HVNW has a n+ doped drain region.
At some embodiment of the present invention, the number of p top section, each segment distance between each p top section and n rank district, the width of each p top section, and the separating distance between the section of p top be can there is a continuous p top zone with another LDMOS device comparatively speaking, make conducting resistance aspect have at least about 15% minimizing under a drain voltage of about 1 volt.In certain embodiments of the present invention, a puncture voltage of LDMOS device is approximately identical with the puncture voltage of LDMOS device with a continuous p top zone.
Mos device can comprise a field oxide isolation region in addition, so that a p+ doped region and the 2nd p+ doped region of contiguous n+ doping source region and the isolation of the doped region of HVNW.For example, LDMOS device in field oxide isolation region makes a p+ doped region and the 2nd p+ doped region of contiguous n+ doping source region and the isolation of the n+ doped drain region of HVNW.
MOS structure can comprise that one is disposed at the N+ doping source region of HVNW and the grid structure between doped region in addition.For example, LDMOS device comprises that one is disposed at the n+ doping source region of HVNW and the grid structure between n+ doped drain region.
In certain embodiments of the present invention, mos device may be a kind of insulated gate double carrier transistor, and wherein one the 3rd p+ doped region is to be configured in HVNW.In certain embodiments of the present invention, mos device may be a kind of diode, and wherein a n+ doped drain region is to be configured in HVNW.
Of the present invention one implements sample state also provides a kind of method for the manufacture of a mos device, comprises the following steps: a p substrate is provided; Forming a high voltage n trap (HVNW) enters in p substrate; Form one the one p trap in p substrate; Form one the 2nd p trap in HVNW; Form a discrete p top zone in HVNW, discrete p top zone has a plurality of p top section; And configuration one n rank district is in the HVNW of top, discrete p top zone.A plurality of p top section has one section of distance from n rank district to define a plurality of distances, has a width to define a plurality of width, and has one section and one separating distance that is close to p top section to define a plurality of separating distances.In certain embodiments of the present invention, a plurality of distances may be identical, and in some other embodiment of the present invention, a plurality of distances increase gradually.
A kind of manufacture mos device method can comprise formation one field oxide isolation region in addition.Field oxide isolation region has one by a p trap and overlapping the first field oxide structure of the 2nd p trap, and one by the second field oxide structure of n rank area overlapping.
A kind of manufacture mos device method can comprise formation one grid structure in addition.For example, a grid structure may form by carrying out a gate oxide, formation one polysilicon layer and forming around a clearance wall of grid structure.
A kind of manufacture mos device method can comprise the steps: to form a n+ doping source region in addition in the 2nd p trap of adjacent gate structures; Form one the one p+ doped region in a p trap; Form one the 2nd p+ doped region in the 2nd p trap; And the doped region that forms a vicinity second field oxide structure is in HVNW.
At some embodiment of the present invention, doped region may be a n+ doped drain region, and mos device may be LDMOS device or a diode.In some other embodiment of the present invention, doped region may be another p+ doped region, and mos device may be an insulated gate double carrier transistor.
The in the situation that of LDMOS device, the width of the number of p top section, p top section, each p top section are from distance and the separating distance between the section of p top in n rank district, be can with another LDMOS device with a continuous p top zone comparatively speaking, make to have at least about 15% minimizing under a drain voltage of about 1 volt.
Of the present invention another implemented sample state and more comprised a kind of product by method manufacturing of the present invention.
These embodiment of the present invention and of the present invention other implement sample states and embodiment look back coordinate accompanying drawing following explanation time will be more aobvious clear.But, the present invention particularly defines by the claim scope of enclosing.
Accompanying drawing explanation
Fig. 1 shows the plan view of LDMOS device;
Fig. 2 shows the plan view in LDMOS district;
Fig. 3 A is presented in Fig. 2 the profile along the shown LDMOS district of hatching AA ';
Fig. 3 B is presented in Fig. 2 the profile along the shown LDMOS district of hatching BB ';
Fig. 4 shows the plan view according to the LDMOS district of one embodiment of the invention;
Fig. 5 A show according to one embodiment of the invention in Fig. 4 along the profile in the shown LDMOS district of hatching AA ';
Fig. 5 B show according to one embodiment of the invention in Fig. 4 along the profile in the shown LDMOS district of hatching BB ';
Fig. 6 A and Fig. 6 B for according to one embodiment of the invention after high voltage n trap has been formed and has entered p substrate, respectively along the AA ' of Fig. 4 and the profile of BB ' hatching;
Fig. 7 A and Fig. 7 B for the 2nd p trap in a p trap is formed at p substrate according to one embodiment of the invention be formed at HVNW in after, respectively along the AA ' of Fig. 4 and the profile of BB ' hatching;
Fig. 8 A and Fig. 8 B for according to one embodiment of the invention make discrete p top zone be formed at HVNW in after, respectively along the AA ' of Fig. 4 and the profile of BB ' hatching;
Fig. 9 A and Fig. 9 B for according to one embodiment of the invention after n rank district is configured within HVNW, respectively along the AA ' of Fig. 4 and the profile of BB ' hatching;
Figure 10 A and Figure 10 B be according to one embodiment of the invention after forming field oxide isolation region, respectively along the AA ' of Fig. 4 and the profile of BB ' hatching;
Figure 11 A and Figure 11 B be according to one embodiment of the invention after carrying out gate oxidation process, respectively along the AA ' of Fig. 4 and the profile of BB ' hatching;
Figure 12 A and Figure 12 B be according to one embodiment of the invention after the polysilicon layer of formation control grid structure, respectively along the profile of Fig. 4 of AA ' and BB ' hatching;
Figure 13 A and Figure 13 B are forming after the clearance wall of control gate electrode structure, respectively along the AA ' of Fig. 4 and the profile of BB ' hatching according to one embodiment of the invention;
Figure 14 A and Figure 14 B for according to one embodiment of the invention n+ doping source region be formed in the 2nd p trap n+ doped drain region be formed at HVNW in after, respectively along the AA ' of Fig. 4 and the profile of BB ' hatching;
Figure 15 A and Figure 15 B for according to one embodiment of the invention p+ doped region be formed in a p trap another p+ doped region be formed at the 2nd p trap in after, respectively along the AA ' of Fig. 4 and the profile of BB ' hatching;
Figure 16 A and Figure 16 B for according to one embodiment of the invention after interlayer dielectric layer is provided, respectively along the AA ' of Fig. 4 and the profile of BB ' hatching;
Figure 17 A and Figure 17 B for according to one embodiment of the invention after the first metal layer is provided, respectively along the AA ' of Fig. 4 and the profile of BB ' hatching;
Figure 18 A and Figure 18 B are for showing TCAD emulation graphic that is installed on the impact generation speed puncturing under about known LDMOS;
Figure 19 A and Figure 19 B are installed on TCAD emulation graphic of impact generation speed puncture under according to one embodiment of the invention about LDMOS for showing;
Figure 20 A and Figure 20 B are installed on for showing about known LDMOS graphic that the TCAD of the potential energy figure puncturing under simulates;
Figure 21 A and Figure 21 B are installed on about LDMOS graphic that the TCAD of the potential energy figure puncturing under simulates according to one embodiment of the invention for showing;
Figure 22 A is graphic to drain current according to the drain voltage about known LDMOS device and illustrative LDMOS device of one embodiment of the invention;
Figure 22 B is graphic to the another kind of drain current according to the drain voltage about known LDMOS device and illustrative LDMOS device of one embodiment of the invention;
Figure 23 shows the plan view according to the LDMOS device of one embodiment of the invention;
Figure 24 shows the detailed plan view according to a part for the LDMOS device of Figure 23 of one embodiment of the invention, and it shows four discrete p top sections;
Figure 25 shows the detailed plan view according to a part for the LDMOS device of Figure 23 of one embodiment of the invention, and it shows four discrete p top sections;
Figure 26 A shows the profile that is shown in the LDMOS device in Fig. 5 A completely according to one embodiment of the invention;
Figure 26 B shows the more detailed profile that is shown in the LDMOS device in Figure 26 A according to one embodiment of the invention;
Figure 27 A shows the profile according to the N channel mos device of the discrete p of having of one embodiment of the invention top zone;
Figure 27 B shows the profile according to the N rank section of the N channel mos device without discrete p top zone of one embodiment of the invention;
Figure 28 A shows the profile according to the insulated gate double carrier transistor device of the discrete p of having of one embodiment of the invention top zone;
Figure 28 B shows the profile according to the N rank section of the insulated gate double carrier transistor device without discrete p top zone of one embodiment of the invention;
Figure 29 A shows the profile according to the diode of the discrete p of having of one embodiment of the invention top zone;
Figure 29 B shows the profile of the N rank section of the diode without discrete p top zone; And
Figure 30 is for showing the flow chart according to the technique for the manufacture of LDMOS device of one embodiment of the invention.
[main element symbol description]
AA ': hatching
BB ': hatching
D1, d2, d3, d4, d5: distance
W1, W2, W3, W4: width
1:LDMOS device
10:LDMOS district
20: source side
30: drain side
40:p top zone
50:n rank district
60:p substrate
70：HVNW
80: the p traps
90: the two p traps
100:p+ doped region
110:p+ doped region
120:n+ doping source region
130:n+ doped drain region
140: field oxide isolation region
150: control gate electrode structure
160: the interlayer dielectric that is etched (ILD) layer
Metal level is etched at 170: the first
180: intermetallic dielectric (IMD) layer
Metal level is etched at 190: the second
210:LDMOS district
220: source side
230: drain side
240:p top zone
250:n rank district
260:p substrate
270: high voltage n trap (HVNW)
280: the p traps
290: the two p traps
300:p+ doped region
310:p+ doped region
320:n+ doping source region
330:n+ doped drain region
340: field oxide isolation region
345: grid oxic horizon
350: control gate electrode structure
355: clearance wall
360: interlayer dielectric (ILD) layer
365: the first core spaces
370: the first metal layer
375: isolated area
380: intermetallic dielectric (IMD) layer
390: the second metal levels
400: dielectric layer
410: part
420: point
430: part
440: point
450: part
460: line
470: part
480: line
510:LDMOS device
520:LDMOS device
530: puncture voltage
540:LDMOS device
550:LDMOS device
560: conducting resistance
600:LDMOS device
620: source side
630: drain side
640:p top section
650: distance S1, S2, S3, S4, S5
660: section
670:p top section
700:p substrate
710：HVNW
720: the p traps
725: the two p traps
730: the p+ doped regions
735: the two p+ doped regions
740:n+ doping source region
745:n+ doped drain region
750:n rank district
760: discrete p top zone
770: field oxide isolation region
780: control gate electrode structure
785: interlayer dielectric layer
790: conductive layer
800:p substrate
810：HVNW
820: the p traps
825: the two p traps
830: the p+ doped regions
835: the two p+ doped regions
840:n+ doped region
845: the three p+ doped regions
850:n rank district
860: discrete p top zone
870: field oxide isolation region
880: control gate electrode structure
885: interlayer dielectric layer
890: conductive layer
900:p substrate
910：HVNW
920: the p traps
925: the two p traps
930: the p+ doped regions
935: the two p+ doped regions
940:n+ doping source region
945:n+ doped drain region
950:n rank district
960: discrete p top zone
970: field oxide isolation region
980: control gate electrode structure
985: interlayer dielectric layer
990: conductive layer
1000:LDMOS device
1010:p substrate
1020:p substrate
1030：HVNW
1040：HVNW
1050：HVNW
1060: field oxide isolation region
1070: gate oxide
1080: control gate electrode structure
1090: control gate electrode structure
1100：HVNW
1110: the two p traps
1120: interlayer dielectric layer
1130: interlayer dielectric layer
Embodiment
The present invention is illustrated by blanket, referring now to the accompanying drawing that may not draw in proportion, explains.
Referring now to accompanying drawing illustrate more completely some embodiment of the present invention under, in accompanying drawing, show some embodiment of the present invention but not all embodiment.Really, various embodiment of the present invention may be specific with the different pattern of majority, and should not be construed as being limited to the embodiment proposing in this; On the contrary, providing of these embodiment is to make this specification meet the proper demand being applicable to.
As at specification and enclosing and using in claim scope, unless context clearly represent, otherwise singulative comprises plural words and phrases.For example, mentioning of " grid structure " comprises a plurality of this grid structures.
Although adopt specific term in this, they are used with a kind of common and descriptive meaning, rather than the object in order to limit only.As all buzz words of the technology that comprises in this used and science buzz word have with the present invention under one of them identical meaning of conventionally understanding of haveing the knack of this skill person, unless a buzz word is otherwise defined.But we will further understand, for example defined those buzz words of general dictionary should be construed as having and as having, have the knack of the meaning that this skill person under the present invention understands conventionally.We will further understand, for example defined those buzz words of general dictionary should be construed as having the meaning conforming to they meanings in the context of related art techniques and this specification.Unless this specification is in this clear and definite so definition, otherwise this general buzz word will can not explained with meaning Utopian or exceedingly form.
As used in this, " mos device " represents a kind of MOS device.Each example that Laterally Diffused Metal Oxide Semiconductor (LDMOS), N channel mos (NMOS), insulated gate double carrier transistor (IGBT) and diode are mos device.This device may be designed to coordinate and is equivalent to the high voltage of other semiconductor devices or extra-high pressure even.
As used in this, " LDMOS device " represents to have the metal oxide field-effect transistor (MOSFET) of coplanar source electrode and drain region.According to some embodiment, LDMOS device of the present invention be characterized as high-breakdown-voltage and low on-resistance.That is LDMOS device of the present invention and the method for manufacturing this device cause having the LDMOS device of quite high puncture voltage.In addition, with the known LDMOS device of known skill comparatively speaking, LDMOS device of the present invention and the method for manufacturing this device cause having the LDMOS device of quite low conducting resistance.
Fig. 4 shows the plan view according to the LDMOS district 210 of an illustrative embodiments of the present invention.LDMOS district 210 has p type diffused layer or the p top layer of a plurality of discrete settings, each p top layer has P type top zone or the discrete p top zone 240 that extends to a series of discrete setting of drain side 230 from source side 220, and discrete p top zone 240 is configured in a high voltage N-type well (HVNW).Therefore, according to one embodiment of the invention, LDMOS district 210 is defined by being configured in N-type rank on a plurality of discrete p top zone 240 (the N rank district 250 not being configured in above any p top layer is isolated) or the section of n rank district (n-type grade or n-grade region) 250.
Fig. 5 A is the profile according to the AA ' hatching along Fig. 4 of one embodiment of the invention.According to one embodiment of the invention, this illustration performance of a LDMOS device has P type semiconductor substrate or a p substrate 260, and it may all or part of formation enter a P type epitaxial loayer, in wherein having disposed a HVNW 270.One the one p trap 280 is formed in p substrate 260, and one the 2nd p trap 290 is formed in HVNW 270, and a p trap 280 has a p+ doped region 300, and the 2nd p trap 290 has another p+ doped region 310 of a contiguous n+ doping source region 320.One n+ doped drain region 330 has been formed in HVNW 270.This section in LDMOS district 210 is that the n rank district 250 being configured in one of them of a plurality of discrete p top zone 240 represents.One separated in fact doped region 300,310, field oxide isolation region 340 and 320,330.
The known any control gate electrode structure 350 of known skill may be used in LDMOS device.For example, control gate electrode structure 350 can comprise a conductive layer being configured on a dielectric layer.Control gate electrode structure 350 can comprise dielectric side walls clearance wall in addition.One interlayer dielectric (ILD) layer 360 is to be configured in above the structure of definition.One the first metal layer 370 is equipped with one by the contact net (network of contacts) of ILD layer 360.The illustrative embodiments of a LDMOS device of Fig. 4 shows that intermetallic dielectric (IMD) layer 380, one second metal level 390 that is etched is configured thereon, and the contact net providing by IMD layer 380 is provided in addition.
Fig. 5 B is the profile along BB ' hatching of Fig. 4.According to one embodiment of the invention, this profile of LDMOS device has determined same structure in Fig. 5 A, except a discrete p top layer is not configured in HVNW 270.Therefore,, according to this illustrative embodiments of the present invention, the cross section of the cross section of known structure as shown in Figure 3 B and LDMOS device of the present invention as shown in Figure 5 B may be in fact similar.Certainly, the cross section of known structure is as shown in Figure 3A different from the cross section of LDMOS device of the present invention as shown in Figure 5A.
Fig. 6 A to Figure 17 B is in manufacturing LDMOS device of the present invention, the profile of the LDMOS device after the step that completes an explanation.With each figure of one " A " ending be explanation along the section of the LDMOS device of AA ' hatching of Fig. 4 (that is, show p top zone 240), and be explanation along the section of the LDMOS device of BB ' hatching of Fig. 4 (that is, only show n rank district 250) with each figure of one " B " ending.
Fig. 6 A and Fig. 6 B be for after high voltage n trap (HVNW) 270 has been formed and has entered p substrate 260, respectively along the profile of Fig. 4 of AA ' and BB ' hatching.HVNW 270 starts to downward-extension on p substrate 260.The technique that forms HVNW 270 generally can relate to deposition one photoresist and will be formed the region that enters p substrate 260 to define HVNW 270, then desired pattern and the position of patterning the HVNW 270 that develops.Then can carry out an injection by the mask of patterning and development and enter a for example epitaxial loayer of p substrate 260.In certain embodiments of the present invention, inject below a then n trap and drive in step.Drive in and betide a rising temperature as step 1 and continue certain period.In certain embodiments of the present invention, the rising temperature that drives in step is approximately in the scope of about 1,000 ℃ to about 1,150 ℃, continues one section approximately from the time in the scope of about 20 minutes to about 2 hours.In certain embodiments of the present invention, injection process has the temperature of about 1,150 ℃ and continues about 1 hour.Any residual photoresist generally may utilize the technique of HVNW 270 and proportionately be removed or after the technique that completes HVNW 270, be removed subsequently.
Fig. 7 A and Fig. 7 B for one the 2nd p trap 290 in a p trap 280 is formed at p substrate 260 be formed at HVNW 270 in after, respectively along the AA ' of Fig. 4 and the profile of BB ' hatching.One P type trap is by using a photoetching technique and a p-type foreign ion being injected to be inserted into and expect that layer forms.In certain embodiments of the present invention, may follow a p trap after Implantation step and drive in step, accordingly, drive in the condition of step as being illustrated in advance this.This technique also can comprise removing of any residual photoresist.The one p trap 280 and the 2nd p trap 290 can form the step that maybe may separate by use in fact simultaneously and form, if separately the ion of pattern is that the latter's technology is preferably for being infused in respectively p substrate 260 and HVNW 270.
Fig. 8 A and Fig. 8 B for make discrete p top zone 240 be formed at HVNW 270 in after, respectively along the AA ' of Fig. 4 and the profile of BB ' hatching.Discrete p top zone 240 is a diffusion region, P type top, and its p top section with more than one discrete formation is to define whole discrete p top zone 240.In certain embodiments of the present invention, discrete p top zone 240 comprises two, three, four, five, six, seven, eight, nine, or ten or how discrete p top section.
Do not intend in the situation of bound by theory, discrete p top zone 240 is to be designed to improve charge balance and for reducing the specific on-resistance of LDMOS device.Do not intend in the situation of bound by theory further, discrete p top zone 240 be designed to allow to enter downward consume in the drain region of extension of HVNW 270 in conjunction with from p substrate 260 upwards consume with uninfluenced in fact, use provide one in fact similarly puncture voltage to known LDMOS device.Then the doping of HVNW 270 by so that a lower specific on-resistance may be reached.
In certain embodiments of the present invention, discrete p top zone is to be configured to approach most the 2nd p trap 290.For example, the number of discrete p top section, the location of each the p top section within HVNW 270, each p top section location relative to each other, with as illustrate further in this other parameters and will affect the minimizing degree of the specific on-resistance of LDMOS device.
One p top section of discrete p top zone 240 may will be formed the region that enters HVNW 270 to define p top section by depositing a photoresist, then the desired pattern of patterning the p top section of developing and position and form.Then can carry out one of p-type ion and inject by the mask of patterning and development, use deposition p top section and enter in HVNW 270.According to some embodiment of the present invention, may select for example the P type ion from any one or more elements, any one or more elements are from an IIIA family element of periodic table, and for example conventionally select boron according to some embodiment of the present invention.In certain embodiments of the present invention, the p-type ion of expectation may be formed by having from least one element of IIIA family and the compound of at least one element from IVA family.For example, according to one embodiment of the invention, P type ion can have formula S i
xb
y.
Certainly, for injecting the processing of p top section, may remove any photoresist surpassing and finish with device from then on.Each p top section of discrete p top zone 240 may form in forming discrete p top zone 240 simultaneously, or even sees through plural photoetching and implantation step and form.When formation has the variable depth within HVNW 270 for example and/or in a discrete p top zone 240 of the variable concentrations of the p-type ion between the section of p top and/or even at another during the part or all of shape layer of the p top section above the section of p top, two more steps may be particularly useful, and such section can be combined and or separated within discrete p top zone 240.Finally, as shown in Figure 8 B, a discrete p top zone is not configured in this region of LDMOS device.
Fig. 9 A and Fig. 9 B are for after being configured within HVNW 270 by n rank district 250, respectively along the AA ' of Fig. 4 and the profile of BB ' hatching.N rank district 250 will be formed the region that enters HVNW 270 by depositing a photoresist to define n rank district 250, then patterning and develop to confirm n rank district 250 position desired pattern and be infused in HVNW 270.Then can carry out one of N-shaped formula ion and inject by the mask of patterning and development, use deposition n rank district 250 and enter in HVNW 270.According to some embodiment of the present invention, may select for example from the N-type ion of any one or more elements, any one or more elements, from the YiVA family element of periodic table, for example, are phosphorus according to some embodiment of the present invention.In certain embodiments of the present invention, the N-shaped formula ion of expectation may be by having from least one element of VA family and at least one element (Si for example with common pattern from IVA family
xp
y) compound form.
According to some embodiment of the present invention, n rank district 250 is on the region being directly infused in the HVNW 270 that forms discrete p top zone 240.In certain embodiments of the present invention, n rank district 250 is injected into so that it covers in fact discrete p top zone 240.In other embodiment again of the present invention, n rank district is injected into so that it just covers discrete p top zone 250, and it is the illustrative embodiments that is similar to Fig. 9 A.In other more common embodiment of the present invention, n rank district 250 does not fully cover discrete p top zone 240.
Figure 10 A and Figure 10 B are after forming field oxide isolation region 340, respectively along the AA ' of Fig. 4 and the profile of BB ' hatching.According to one embodiment of the invention, field oxide isolation region 340 comprises a plurality of field oxide isolation structures in the various regions of separated LDMOS device.For example, in the illustrative embodiments of Figure 10 A and Figure 10 B, field oxide isolation region 340 comprises the field oxide isolation structure of separated various doped region (finally will be formed in a p trap 280, the 2nd p trap 290 and HVNW 270).
According to one embodiment of the invention, first field oxide isolation region 340 may be by providing quite thick field oxide layer (for example 1 micron or larger) to form according to some embodiment of the present invention, along the upper surface of LDMOS device and grow up, then crested be etched to define some part of upper surface, as represented in Figure 10 A and Figure 10 B.
In some other embodiment of the present invention, field oxide isolation region 340 is around to grow up in some region of LDMOS device, is then etched to isolate some region of LDMOS device.For example, may be by using a field oxide diffusion that one uniform in fact field oxide layer is provided.One photoresist may be provided to the field oxide layer of growth, is then patterned and develops to confirm the region that some part of field oxide isolation layer may be etched away.After etching technics, any residual photoresist may be removed, and a plurality of field oxide structure is residual to define field oxide isolation region 340.In some other embodiment of the present invention, for example a precursor material of a pad oxide and/or a silicon nitride may similarly be provided, and a field oxide oxidation technology is based upon the field oxide in defined these structures of etching.
Figure 11 A and Figure 11 B are for carrying out a gate oxidation process with after forming a grid oxic horizon 345, respectively along the AA ' of Fig. 4 and the profile of BB ' hatching.Gate oxidation process comprises the oxidation step of a sacrifice, and by this, monoxide is to grow into a silicon face by making silicon face be exposed to oxygen in certain a period of time under some condition.Generally speaking, the oxidation technology of sacrifice is to be implemented at the temperature raising temperature or the even higher temperature of the scope of about 800 ℃ to about 1,000 ℃ (for example, from).In certain embodiments of the present invention, the temperature of rising is within the scope from about 850 ℃ to about 950 ℃.In other embodiment again of the present invention, the temperature of rising is approximately 900 ℃.
After the oxidation technology of sacrificing, may follow a grid cleaning procedure or more suitable grid cleaning procedure in advance, with from removing native oxide by providing the surface of controlling grid.May use the known any cleaning procedure of grid in advance of known skill.For example, grid cleaning procedure can adopt making for cleaning the desired regions of a gate oxide to be formed of HF, HCl or ozone in advance.Finally, adopt a gate oxidation step to form a grid oxic horizon 345.
Figure 12 A and Figure 12 B are after a polysilicon layer of formation control grid structure 350, respectively along the AA ' of Fig. 4 and the profile of BB ' hatching.The technique that forms polysilicon layer comprises generally by using a chemical vapor deposition method to deposit a polysilicon on grid oxic horizon 345.After polysilicon deposition, then deposit a tungsten silicide (WSi
x), it is combined with polysilicon layer and is called as multi-crystal silicification metal.One lithographic process steps by multi-crystal silicification metal level after being used for being defined in etching by residual region.Complete in etching, the polysilicon layer of definition control gate electrode structure 350 can be residual.
Figure 13 A and Figure 13 B are forming after a clearance wall 355 of the polysilicon layer of control gate electrode structure 350, respectively along the AA ' of Fig. 4 and the profile of BB ' hatching.In one embodiment of this invention, a conformal layer of the adjacent silicomethane of tetraethyl (tetraethylorthosilane, TEOS) is the surface that is deposited to LDMOS device.Photoetching may be for defining the residual clearance wall 355 around control gate electrode structure 350.Cover surface and be then etched to form the clearance wall 355 around control gate electrode structure 350.(more eligibly, clearance wall 355 also can be regarded as a part for control gate electrode structure 350)
Figure 14 A and Figure 14 B at n+ doping source region 320, be formed in the 2nd p trap 290 n+ doped drain region 330 be formed at HVNW 270 in after, respectively along the AA ' of Fig. 4 and the profile of BB ' hatching.Where each of n+ doped region 320,330 may will form to define n+ doped region 320,330 by depositing a photoresist, then the desired pattern of patterning the position of confirming n+ doped region 320,330 of developing and being injected in their regions separately.Then, N+ ion can be injected into or be injected in the defined region of mask, for n+ doping source region 320 is formed, enters the 2nd p trap 290 and n+ doped drain region 330 is formed and enters HVNW 270.In certain embodiments of the present invention, each of these n+ doped regions 320,330 may have the separable programming that is similar to those steps defined above by use and forms.
Figure 15 A and Figure 15 B are for being formed in p+ doped region 300 in a p trap 280 after p+ doped region 310 is formed in the 2nd p trap 290, respectively along the AA ' of Fig. 4 and the profile of BB ' hatching.In certain embodiments of the present invention, the N+ doping source region 320 of p+ doped region 310 contiguous the 2nd p traps 290 of the 2nd p trap 290.
Where each of p+ district 300,310 may will form to define p+ district 300,310 by depositing a photoresist, then the desired pattern of patterning the position of confirming p+ district 300,310 of developing and being injected in their regions separately.Then, P+ ion can be injected into or be injected in the defined region of mask, enters a p Jing280Bing Jiang p+ district 310 formation enter the 2nd p trap 290 for 300 formation of Jiangp+ district.In certain embodiments of the present invention, each of these p+ districts 300,310 may have the separable programming that is similar to those steps defined above by use and forms.
Figure 16 A and Figure 16 B are for after providing an interlayer dielectric (ILD) layer 360, respectively along the AA ' of Fig. 4 and the profile of BB ' hatching.First ILD layer 360 may be by making an interlayer dielectric deposition to LDMOS device be provided.Then can use photoetching to set up the photoresist of a patterning, for defining, will provide the first core space 365 of an electric conducting material.Finally, the first core space 365 will be etched to determine the structure of ILD layer 360.
Figure 17 A and Figure 17 B are for after providing a first metal layer 370, respectively along the AA ' of Fig. 4 and the profile of BB ' hatching.One first metal of the first metal layer 370 is to deposit along ILD layer 360, uses and fills up in fact the first core space 365 being defined within ILD layer 360.Then can use photoetching to set up the photoresist of a patterning, for defining, will provide the isolated area 375 of a dielectric material of intermetallic dielectric (IMD) layer 380.Finally, isolated area 375 will be etched to determine the structure of the first metal layer 370.
Layer afterwards can similarly be provided.For example, as shown in the embodiment illustrating represented in Fig. 5 A and Fig. 5 B, an IMD layer 380 may be provided to the first metal layer 370.One second metal level 390 with the second isolated area then can be provided to IMD layer 380.For example, another kind of dielectric layer 400 may be provided to the second metal level 390.
Figure 18 A is for showing TCAD emulation graphic that is installed on the impact generation speed puncturing under about known LDMOS.Figure 18 B is the performance more in detail of determined part 410 in Figure 18 A.Figure 18 B shows point 420, and it produces speed about where experience maximum impact in device.Figure 19 A is for showing TCAD emulation graphic that is installed on the impact generation speed puncturing under about an illustrative LDMOS of the present invention.Figure 19 B is the performance more in detail of determined part 430 in Figure 19 A.Figure 19 B shows point 440, and it produces speed relevant for where experience maximum impact in device.Figure 18 A-Figure 19 B shows that the impact being installed under puncturing with respect to known LDMOS produces speed, and the impact under puncturing produces speed and not affected by the discrete p apex structure of LDMOS device of the present invention.Therefore, LDMOS device proof of the present invention is similar to the depression ability of known devices, and maximum puncture voltage is in fact also uninfluenced.
Figure 20 A is installed on for showing about known LDMOS graphic that the TCAD of the current potential puncturing under simulates.Figure 20 B is the performance more in detail of determined part 450 in Figure 18 A.Figure 20 B is presented at the line 460 of the maximum potential experiencing in device.Figure 21 A is installed on for showing about illustrative LDMOS of the present invention graphic that the TCAD of the current potential puncturing under simulates.Figure 21 B is the performance more in detail of determined part 470 in Figure 21 A.Figure 21 B is presented at the line 480 of the maximum potential experiencing in device.Figure 20 A-Figure 21 B be presented at known LDMOS device and LDMOS device of the present invention between, the Potential distribution under puncturing is in fact also uninfluenced.Therefore, LDMOS device of the present invention proves the potential energy figure (being similar to the potential energy figure of known device) under puncturing, and maximum puncture voltage is in fact also uninfluenced.
Figure 22 A is graphic to drain current about the drain voltage of known LDMOS device 510 and illustrative LDMOS device 520 of the present invention.Figure 22 A be presented at known LDMOS device and LDMOS device of the present invention between, maximum puncture voltage 530 is approximately identical.
Figure 22 B is graphic to the another kind of drain current about the drain voltage of known LDMOS device 540 and illustrative LDMOS device 550 of the present invention.Figure 22 B shows illustrative LDMOS device of the present invention, and it surpasses the conducting resistance of the known LDMOS device with continuous p top zone in the improvement that provides 15.6% aspect conducting resistance 560 under the drain voltage of 1 volt.
Figure 23 is the plan view of the illustrative LDMOS device 600 with one source pole side 620 and a drain side 630 according to one embodiment of the invention.Figure 24 shows the detailed view of a part of the illustrative LDMOS device 600 of Figure 23, and it shows that four discrete p top sections 640 have width W 1, W2, W3 and W4.As being provided in this, discrete p top zone can have many p top section, but for illustration purpose, Figure 24 represents an embodiment with four p top sections.In one embodiment of this invention, width W 1, W2, W3 and the W4 of p top section 640 in fact may be approximately identical.In some other embodiment, width W 1, W2, W3 and the W4 of p top section 640 may change the minimizing that is issued to the expectation of conducting resistance with the situation of the puncture voltage not needing to have the greatest impact in fact.In certain embodiments of the present invention, even if the width of p top section 640 is different, for the implantation concentration of p top section 640 and the spacing of p top section 640, may change to reach vague and general state completely.In certain embodiments of the present invention, in the time of the implantation concentration of p top section 640 and spacing, adjust the conducting resistance that allows improvement, and still maintain in fact high-breakdown-voltage simultaneously.
Figure 25 shows the detailed view of a part of the illustrative LDMOS device 600 of Figure 23, and it shows that four discrete p top sections 640 have distance S1, S2, S3, S4 and S5650.As being provided in this, discrete p top zone can have many p top section, but for illustration purpose, Figure 25 represents an embodiment with four p top sections.In one embodiment of this invention, distance S1, S2, S3, S4 and the S5650 between p top section 640 in fact may be approximately identical.In some other embodiment of the present invention, distance S1, S2, S3, S4 and S5650 between p top section 640 may change, and are issued to the minimizing of the expectation of conducting resistance with the situation of the puncture voltage not needing to have the greatest impact in fact.At some embodiment of the present invention, even if the spacing of p top section 640 is different, for the implantation concentration of p top section 640 and the width of p top section 640, may change to reach vague and general state completely.In certain embodiments of the present invention, in the time of the implantation concentration of p top section 640 and width, adjust the conducting resistance that allows improvement, and still maintain in fact high-breakdown-voltage simultaneously.
Figure 26 A shows the profile according to the LDMOS device of one embodiment of the invention, as the complete legend in Fig. 5 A.Figure 26 B shows the more detailed cross sectional view according to the section 660 of the shown LDMOS device of Figure 26 A of one embodiment of the invention.Discrete top zone 240 has five p top sections 670, and it has distance d1, d2, d3, d4 and the d5 separately apart from n rank district 250.As being provided in this, discrete p top zone 240 can have many p top section, but for illustration purpose, Figure 26 A and Figure 26 B represent an embodiment with five p top sections.According to one embodiment of the invention, p top section 670 may be in fact approximately identical apart from distance d1, d2, d3, d4 and the d5 in n rank district 250.In some other embodiment of the present invention, p top section 670 may be different apart from distance d1, d2, d3, d4 and the d5 in n rank district 250.For example, in one embodiment of this invention, p top section 670 may increase to cause p top section 670 to connect and more go deep in HVNW 270 progressively apart from distance d1, d2, d3, d4 and the d5 in n rank district 250 gradually.
Really, any one variable is roughly expressed as Wi, Si and the di of a p top section i, compared to the known LDMOS device with a p top zone configuring in fact continuously, any one of discrete p top zone, any combination or even all p top section may be designed to provide at least about 5% improvement aspect conducting resistance, at least about 10% improvement, at least about 15% improvement, at least about 20% improvement, or at least about 25% improvement.
Figure 27 A shows the profile according to N channel mos (NMOS) device (particularly extra-high pressure NMOS device) of the discrete p of having of one embodiment of the invention top zone.The shown illustrative embodiments of Figure 27 A shows a p substrate 700, and it may all or part of formation enter a P type epitaxial loayer, in wherein having disposed a HVNW 710.One the one p trap 720 is formed in p substrate 700, and one the 2nd p trap 725 is formed in HVNW 710, and a p trap 720 has one the one p+ doped region 730, and the 2nd p trap 725 has the 2nd p+ doped region 735 of a vicinity one n+ doping source region 740.One n+ doped drain region 745 is formed in HVNW 710.This section of NMOS device is to represent with a n rank district 750, and the upper n rank district 750 that is configured in a discrete p top zone 760 has a plurality of p top section.One separated in fact doped region 730,735 & 740,745 in field oxide isolation region 770.NMOS also has a control gate electrode structure 780, an interlayer dielectric layer 785 and a conductive layer 790.
Figure 27 B shows the profile of the N rank section of a NMOS device without discrete p top zone.
Figure 28 A shows the profile according to insulated gate double carrier transistor (IGBT) device (particularly extra-high pressure IGBT device) of the discrete p of having of one embodiment of the invention top zone.The shown illustrative embodiments of Figure 28 A shows a p substrate 800, and it may all or part of formation enter a P type epitaxial loayer, in wherein having disposed a HVNW 810.One the one p trap 820 is formed in p substrate 800, and one the 2nd p trap 825 is formed in HVNW 810, and a p trap 820 has one the one p+ doped region 830, and the 2nd p trap 825 has the 2nd p+ doped region 835 of a vicinity one n+ doped region 840.One the 3rd p+ doped region 845 is formed in HVNW 810.This section of NMOS is to represent with a n rank district 850, and the n rank district 850 being configured on a discrete p top zone 860 has a plurality of p top section.One separated in fact doped region 830,835,840,845, field oxide isolation region 870.IGBT device also has a control gate electrode structure 880, an interlayer dielectric layer 885 and a conductive layer 890.
Figure 28 B shows the profile of the N rank section of an IGBT device without discrete p top zone.
Figure 29 A shows a profile with the diode (particularly extra-high pressure diode) of a discrete p top zone according to one embodiment of the invention.The shown illustrative embodiments of Figure 29 A shows a p substrate 900, and it may all or part of formation enter a P type epitaxial loayer, in wherein having disposed a HVNW 910.One the one p trap 920 is formed in p substrate 900, and one the 2nd p trap 925 is formed in HVNW 910, and a p trap 920 has one the one p+ doped region 930, and the 2nd p trap 925 has the 2nd p+ doped region 935 of a vicinity one n+ doping source region 940.One n+ doped drain region 945 is formed in HVNW 910.This section of NMOS is to represent with a n rank district 950, and the n rank district 950 being configured on a discrete p top zone 960 has a plurality of p top section.One separated in fact doped region 930,935,940,945, field oxide isolation region 970.IGBT device also has a control gate electrode structure 980, an interlayer dielectric layer 985 and a conductive layer 990.
Figure 29 B shows the profile of the N rank section of a diode without discrete p top zone.
Figure 30 is for showing the flow chart according to the technique for the manufacture of LDMOS device of one embodiment of the invention.Technique for the manufacture of a LDMOS device 1000 comprises the steps: to provide a p substrate 1010; Form a high voltage n trap and enter p substrate 1020; P trap is formed in p substrate and HVNW 1030; Discrete p top zone is formed in HVNW 1040; One n rank district is configured in HVNW 1050; Form a field oxide isolation region 1060 and formation control grid structure.The step of formation control grid structure can comprise the steps: to carry out a gate oxide 1070; One polysilicon layer of formation control grid structure 1080; An and clearance wall around the polysilicon layer of control gate electrode structure 1090 of formation.
Technique for the manufacture of a LDMOS device 1000 can comprise the steps: to make n+ doped region to be formed in the 2nd p trap and HVNW 1100 in addition; P+ doped region is formed in a p trap and the 2nd p trap 1110; One interlayer dielectric layer 1120 is provided; And provide a first metal layer to interlayer dielectric layer 1130.Technique for the manufacture of a LDMOS device 1000 can comprise additional step, for example, for example, forms an IMD layer and/or one second metal level.
Of the present invention one implements the LDMOS device that sample state provides the method manufacturing of the present invention of a kind of foundation.
At above-mentioned explanation and correlative type, propose being benefited of instruction under, have the knack of this skill person and will appreciate that of the present invention most the modification and other embodiment proposing in this.Therefore, we it will be appreciated that the present invention is not limited to disclosed specific embodiment, and revise and other embodiment are within intention is included in the category of the claim scope of enclosing.In addition, although above-mentioned explanation and correlative type understand illustrative embodiments some illustration combination of element and/or function, we should recognize that the various combination of element and/or function may be provided by alternate embodiment under the category that does not deviate from the claim scope of enclosing.In this, for example, be different from above-mentioned at length those element and/or the combination of function and be also considered to be and may in the claim scope of enclosing, be suggested.Although adopt specific term in this, they are used with common and descriptive meaning, rather than the object in order to limit only.
Claims (19)
1. a metal-oxide semiconductor (MOS) (MOS) installs, and comprising:
One p substrate;
One high voltage n trap (HVNW), is configured in this p substrate;
One the one p trap, is formed in this p substrate with one the one p+ doped region;
One the 2nd p trap, is formed in this HVNW of one the 2nd p+ doped region with a contiguous n+ doping source region;
One discrete p top zone, has a plurality of p top sections that are configured in this HVNW; And
One n rank district (n-grage region), are configured on this discrete p top zone,
Wherein, each of the plurality of p top section has one section of distance from this n rank district to define a plurality of distances, has a width to define a plurality of width, and has one section and one separating distance that is close to p top section to define a plurality of separating distances.
2. MOS device according to claim 1, wherein this mos device is a Laterally Diffused Metal Oxide Semiconductor (LDMOS) device, this HVNW has a n+ doped drain region.
3. MOS device according to claim 2, wherein respectively this distance of the plurality of distance is identical.
4. MOS device according to claim 2, wherein the plurality of distance of the plurality of distance increases.
5. MOS device according to claim 2, some in the plurality of p top section, the plurality of distance, the plurality of width and the plurality of separating distance wherein, be with another LDMOS device with a continuous p top zone comparatively speaking, can make under a drain voltage of 1 volt, having at least 15% minimizing aspect conducting resistance.
6. MOS device according to claim 5, wherein a puncture voltage of this LDMOS device is identical with a puncture voltage of this another LDMOS device.
7. MOS device according to claim 2, more comprises a field oxide isolation region, and it is configured to isolate the 2nd p+ doped region and this n+ doped drain region of a p+ doped region, contiguous this n+ doping source region.
8. MOS device according to claim 7, more comprises a grid structure being disposed between this n+ doping source region and this n+ doped drain region.
9. MOS device according to claim 1, wherein this mos device is an insulated gate double carrier transistor, this HVNW has one the 3rd p+ doped region.
10. MOS device according to claim 1, wherein this mos device is a diode, this HVNW has a n+ doped drain region.
11. 1 kinds of methods for the manufacture of a metal-oxide semiconductor (MOS) (MOS) device, comprising:
One p substrate layer is provided;
Form a high voltage n trap (HVNW) and enter this p substrate;
Form one the one p trap in this p substrate;
Form one the 2nd p trap in this HVNW;
Form a discrete p top zone in this HVNW, this discrete p top zone has a plurality of p top section; And
One n rank district is configured in this HVNW of this top, discrete p top zone,
Wherein, each of the plurality of p top section has one section of distance from this n rank district to define a plurality of distances, has a width to define a plurality of width, and has one section and one separating distance that is close to p top section to define a plurality of separating distances.
12. method according to claim 11, more comprises and form a field oxide isolation region, it is by with a p trap and the overlapping one first field oxide structure of the 2nd p trap and defined with one second field oxide structure of this n rank area overlapping.
13. methods according to claim 12, more comprise and form a grid structure.
14. methods according to claim 13, wherein form this grid structure and comprise:
Carry out a gate oxide;
Form a polysilicon layer; And
Form a clearance wall with around this grid structure.
15. methods according to claim 13, more comprise:
Form a n+ doping source region in the 2nd p trap of contiguous this grid structure;
Form one the one p+ doped region in a p trap;
Form one the 2nd p+ doped region in the 2nd p trap; And
In this HVNW, form a doped region, its contiguous this second field oxide structure.
16. methods according to claim 15, wherein this mos device is a LDMOS device, this doped region is a n+ doped drain region.
17. methods according to claim 16, some in the plurality of p top section, the plurality of distance, the plurality of width and the plurality of separating distance wherein, be with another LDMOS device with a continuous p top zone comparatively speaking, can make under a drain voltage of 1 volt, having at least 15% minimizing aspect conducting resistance.
18. methods according to claim 17, wherein a puncture voltage of another LDMOS device of a puncture voltage and this of this LDMOS device is identical.
19. methods according to claim 15, wherein this mos device is an insulated gate double carrier transistor, and this doped region is one the 3rd p+ doped region.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105576008A (en) * | 2014-10-11 | 2016-05-11 | 北大方正集团有限公司 | Semiconductor device |
| CN105576011A (en) * | 2014-10-16 | 2016-05-11 | 立锜科技股份有限公司 | Semiconductor component possessing low current pathway |
| CN106206717A (en) * | 2015-03-13 | 2016-12-07 | 旺宏电子股份有限公司 | There is semiconductor device and the manufacture method thereof of metal level |
| WO2023124670A1 (en) * | 2021-12-31 | 2023-07-06 | 无锡华润上华科技有限公司 | Method for preparing ldmos device, and ldmos device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100019318A1 (en) * | 2008-07-23 | 2010-01-28 | United Microelectronics Corp. | Device for esd protection circuit |
| CN101752421A (en) * | 2008-12-04 | 2010-06-23 | 东部高科股份有限公司 | Semiconductor device and method for manufacturing the same |
| US20110140201A1 (en) * | 2009-12-16 | 2011-06-16 | Cheng-Chi Lin | Lateral power mosfet structure and method of manufacture |
-
2012
- 2012-10-12 CN CN201210387057.2A patent/CN103730495A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100019318A1 (en) * | 2008-07-23 | 2010-01-28 | United Microelectronics Corp. | Device for esd protection circuit |
| CN101752421A (en) * | 2008-12-04 | 2010-06-23 | 东部高科股份有限公司 | Semiconductor device and method for manufacturing the same |
| US20110140201A1 (en) * | 2009-12-16 | 2011-06-16 | Cheng-Chi Lin | Lateral power mosfet structure and method of manufacture |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105576008A (en) * | 2014-10-11 | 2016-05-11 | 北大方正集团有限公司 | Semiconductor device |
| CN105576008B (en) * | 2014-10-11 | 2019-08-06 | 北大方正集团有限公司 | Semiconductor devices |
| CN105576011A (en) * | 2014-10-16 | 2016-05-11 | 立锜科技股份有限公司 | Semiconductor component possessing low current pathway |
| CN105576011B (en) * | 2014-10-16 | 2019-01-29 | 立锜科技股份有限公司 | Semiconductor element with light current logical circulation road |
| CN106206717A (en) * | 2015-03-13 | 2016-12-07 | 旺宏电子股份有限公司 | There is semiconductor device and the manufacture method thereof of metal level |
| WO2023124670A1 (en) * | 2021-12-31 | 2023-07-06 | 无锡华润上华科技有限公司 | Method for preparing ldmos device, and ldmos device |
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