CN116417034A - Setting module for synchronous dynamic random access memory and setting method thereof - Google Patents

Setting module for synchronous dynamic random access memory and setting method thereof Download PDF

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Publication number
CN116417034A
CN116417034A CN202111658500.0A CN202111658500A CN116417034A CN 116417034 A CN116417034 A CN 116417034A CN 202111658500 A CN202111658500 A CN 202111658500A CN 116417034 A CN116417034 A CN 116417034A
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sdram
register
setting
mode
value
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张雅闵
郑景允
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Realtek Semiconductor Corp
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Realtek Semiconductor Corp
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)

Abstract

A setting module for SDRAM and a setting method thereof. The setting module includes at least one register and a controller. The controller is used for: controlling the SDRAM to switch to an initialization setting mode, wherein the initialization setting mode is used for initializing the SDRAM; setting a value of at least one register in an initialization setting mode; and setting the SDRAM according to the value of the at least one register.

Description

Setting module for synchronous dynamic random access memory and setting method thereof
Technical Field
The present invention relates to a memory setting module and a setting method thereof, and more particularly, to a setting module for a synchronous dynamic random access memory and a setting method thereof.
Background
In a synchronous dynamic random access memory (Synchronous Dynamic Random Access Memory, SDRAM) architecture, SDRAM needs to be initialized by an SDRAM controller (SDRAM controller). Known SDRAM controllers are typically developed for the instructions and sequence of operations to be performed at the time of fabrication. It is difficult to verify or otherwise correct if the initialization settings or sequence of settings for the SDRAM have any defects, flaws or errors, just in the sense of the completed SDRAM controller.
Disclosure of Invention
The invention aims to provide a setting method for a synchronous dynamic random access memory (Synchronous Dynamic Random Access Memory, SDRAM), which comprises the following steps: controlling the SDRAM to switch to an initialization setting mode, wherein the initialization setting mode is used for initializing the SDRAM; setting a value of at least one register in an initialization setting mode; and setting the SDRAM according to the value of the at least one register.
The invention also provides a setting module for SDRAM, which comprises at least one register and a controller. At least one register is electrically connected to the SDRAM. The controller group is electrically connected with the SDRAM and at least one register for: controlling the SDRAM to switch to an initialization setting mode, wherein the initialization setting mode is used for initializing the SDRAM; setting a value of at least one register in an initialization setting mode; and setting the SDRAM according to the value of the at least one register.
Drawings
Embodiments of the invention will be best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that the various features may not be drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
FIG. 1 is a block diagram of a setup module according to some embodiments of the invention.
Fig. 2A is a block diagram of a setup module according to some embodiments of the invention.
Fig. 2B is a block diagram of a setup module according to some embodiments of the invention.
Fig. 3 is a flow chart of a setup method of some embodiments of the invention.
Fig. 4 is a flow chart of a setup method of some embodiments of the invention.
Detailed Description
Embodiments of the invention are discussed in more detail below. However, it should be appreciated that the present invention provides many applicable concepts that can be embodied in a wide variety of specific contexts. The particular embodiments discussed are merely illustrative and do not limit the scope of the invention.
The known SDRAM (Synchronous Dynamic Random Access Memory, SDRAM) architecture lacks flexibility in use, and if there are any defects, flaws or errors in the initialization settings or sequence of settings for the SDRAM, it will be difficult to verify or otherwise correct. In order to increase the operation flexibility of the SDRAM architecture, the invention provides a setting module and a setting method thereof.
Referring to fig. 1, a block diagram of a setup module 1 according to some embodiments of the invention is shown. The setup module 1 comprises at least one register 11 and a controller 13, the register 11 being electrically connected to the controller 13. The setting module 1 is electrically connected to a synchronous dynamic random access memory (Synchronous Dynamic Random Access Memory, SDRAM) 9. The components communicate data and signals through electrical connections. The associated control operations will be further described below.
In some embodiments, SDRAM 9 exchanges data with devices (e.g., a computer host) via a general purpose bus. When an initialization setting is required for the SDRAM 9, the controller 13 switches the SDRAM 9 to an initialization setting mode based on a user instruction. Wherein the initialization setting mode is used for initializing the SDRAM 9.
In the initialization setting mode, a user can set the value of at least one register 11 through the controller 13. Subsequently, after the value of the at least one register 11 is set, the controller 13 sets the SDRAM 9 according to the value of the at least one register 11. Further, when the user needs to perform the initialization setting for the SDRAM 9, it is generally required to perform the initialization setting for the SDRAM 9 according to different instruction types of the SDRAM 9.
In some embodiments, the instruction types of SDRAM 9 include: (1) macro command type, for example: an instruction class set cmd_type set, refresh, full bank precharge, and no operation Pre-charge all banks and No operation; (2) a mode address (mode address) type, for example: a mode register address (mode register address); (3) a mode data (mode data) type, for example: a mode register access data (mode register access data); and (4) time (timing) type, such as: the time interval between two instructions.
The different values of the at least one register 11 correspond to combinations of different instruction types of the SDRAM 9, so that the user can fill the corresponding values into the at least one register 11 for the different instruction types, and thus, after the value of the at least one register 11 is set, the controller 13 can set the SDRAM 9 according to the value of the at least one register 11 to complete the initialization setting of the SDRAM 9.
Referring to fig. 2A, a block diagram of a setup module 2 according to some embodiments of the invention is shown. The setting module 2 includes a plurality of registers 21A and 21B and a controller 23, and the registers 21A and 21B are electrically connected to the controller 23. In some embodiments, register 21A comprises an instruction index register that stores values corresponding to the index and time dependent instructions of SDRAM 8. The register 21B includes a macro instruction and mode (mode) information register storing values corresponding to a macro instruction, a mode address (mode address), and mode data (mode data) of the SDRAM 8.
The setting module 2 is electrically connected to the SDRAM 8 via a demultiplexer (demultiplexer) 7. The outputs of the demultiplexer 7 correspond to pins of the SDRAM 8. The demultiplexer 7 is used for decoding the value provided by the setting module 2, and triggering the corresponding pin of the SDRAM 8 according to the decoded value, thereby setting the SDRAM 8. The components communicate data and signals over electrical links. The associated control operations will be further described below.
In some embodiments, when the SDRAM 8 is in the bus data access mode (i.e., the SDRAM 8 exchanges data with a device (e.g., a host computer) via a universal bus) and an initialization setting is required for the SDRAM 8, the controller 23 stops the bus data access mode of the SDRAM 8 and switches the SDRAM 8 to the initialization setting mode based on a user command. Wherein the initialization setting mode is used for initializing the SDRAM 8. In more detail, in the initialization setting mode, the setting of the relevant initialization is mainly performed with respect to the type of instructions required to be used when the SDRAM 8 is operated and the operation order thereof.
In the initialization setting mode, the user can set the values of the registers 21A and 21B through the controller 23. Subsequently, after the values of the registers 21A and 21B are set, the controller 23 sets the SDRAM 8 according to the values of the registers 21A and 21B. Further, when the user needs to perform the initialization setting for the SDRAM 8, the user needs to set the initialization setting for the SDRAM 8 according to different instruction types of the SDRAM 8.
The different values of the registers 21A and 21B correspond to the combinations of different instruction types of the SDRAM 8, so that the user can fill the registers 21A and 21B with the corresponding values for the different instruction types, and thus, after the values of the registers 21A and 21B are set, the controller 23 can set the SDRAM 8 according to the values of the registers 21A and 21B to complete the initialization setting of the SDRAM 8. The technique of the present invention will be further described by various examples.
In some examples, the value of register 21A corresponds to an index and time dependent instruction of SDRAM 8. Specifically, the user can set corresponding values in the register 21A through the controller 23, where the values set in the register 21A are used to trigger the initialization setting of the index and time-dependent instructions of the SDRAM 8 accordingly. When the setting is completed, the controller 23 directly sets the SDRAM 8 according to the value of the register 21A.
In some examples, the value of register 21B corresponds to a macro instruction related instruction of SDRAM 8. Specifically, the user may set a corresponding value in the register 21B via the controller 23, where the value set in the register 21B is used to trigger the initialization setting of the macro instruction of the SDRAM 8 accordingly. When the setting is completed, the controller 23 directly sets the SDRAM 8 according to the value of the register 21B.
In some examples, the value of register 21B corresponds to the mode address of SDRAM 8 and the mode data dependent instruction. Specifically, the user can set a corresponding value in the register 21B through the controller 23, where the value set in the register 21B is used to trigger the mode address of the SDRAM 8 and the initialization setting of the mode data accordingly. When the setting is completed, the controller 23 directly sets the SDRAM 8 according to the value of the register 21B.
In some examples, the value of register 21B corresponds to a mode register read (mode register read, MRR) check status related instruction of SDRAM 8. Specifically, the user may set a corresponding value in the register 21B via the controller 23, where the value set in the register 21B is used to trigger the status check of the MRR instruction of the SDRAM 8 accordingly. When the setting is completed, the controller 23 directly sets the SDRAM 8 according to the value of the register 21B.
It should be noted that the above-described initialization setting operation of the SDRAM 8 may be performed singly or in various combinations according to the need. For example, the value of the register 21B may correspond to both the macro instruction related instruction and the mode address and the mode data related instruction of the SDRAM 8. The user can set corresponding values in the register 21B via the controller 23, and the values set in the register 21B are used to trigger the initialization settings of the macro instruction related instructions and the mode address and the mode data related instructions of the SDRAM 8 accordingly. When the setting is completed, the controller 23 directly sets the SDRAM 8 according to the value of the register 21B.
In some embodiments, if the initialization of different SDRAMs 8 is to be completed simultaneously (e.g., the initialization of the index and time related instructions, macro related instructions, and mode address and mode data related instructions of the SDRAM 8 is to be completed simultaneously), access to the synchronous registers 21A and 21B may be performed. Specifically, an additional synchronization control register may be used to trigger the initialization settings of the SDRAM 8 described above. Please refer to fig. 2B, which is another block diagram of the setup module 2 according to some embodiments of the present invention. The setting module 2 further includes a synchronization control register 21C for: (1) flag whether the SDRAM 8 is switched to the initialization setting mode; and (2) access of the synchronous trigger registers 21A and 21B.
Some embodiments of the invention include a method of setting SDRAM, the flow chart of which is shown in FIG. 3.
The setup method of these embodiments is implemented by a setup module (such as the setup module of the previous embodiments), and the detailed operation of the method is as follows. First, step S301 is executed to control the SDRAM to switch to the initialization setting mode. Wherein the initialization setting mode is used for initializing SDRAM. Step S302 is executed to set the value of at least one register in the initialization setting mode. Step S303 is performed to set SDRAM according to the value of at least one register.
Some embodiments of the invention include a method of setting SDRAM, the flow chart of which is shown in FIG. 4. The setup method of these embodiments is implemented by a setup module (such as the setup module of the previous embodiments), and the detailed operation of the method is as follows.
First, step S401 is executed to stop the bus data access mode of the SDRAM and control the SDRAM to switch to the initialization setting mode. Wherein the initialization setting mode is used for initializing SDRAM. Step S402 is executed to set the values of the instruction index register and the macro instruction and mode information registers in the initialization setting mode. Step S403 is executed to trigger an initialization operation based on the values of the synchronization control register to decode the values of the instruction index register and the macro and mode information registers via an interpreter (inter), and to set the instruction index, the instruction run time, the macro, the mode address, the mode data, the MRR check status, or any combination of the foregoing of the SDRAM according to the decoded values.
Step S404 is executed to determine whether to end the initialization setting mode. If yes, step S405 is executed to control the SDRAM to switch to the bus data access mode. If not, the step S402 is repeatedly executed.
In summary, the setting module and the setting method for the SDRAM provided by the present invention can control the SDRAM through the additional register and the control circuit to verify or correct the defects, flaws or errors of the initialization operation design and the sequence of the SDRAM. It should be noted that, in some embodiments, the controller includes logic circuitry capable of executing operations and instructions, but is not intended to limit the implementation of the hardware components of the present invention.
The foregoing description briefly sets forth features of certain embodiments of the invention in order to provide a more thorough understanding of the various embodiments of the invention to those skilled in the art. It will be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments herein. It will be apparent to those skilled in the art that such equivalent embodiments are within the spirit and scope of the present disclosure, and that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure.
Reference numerals illustrate:
1: setting module
11: register
13: controller for controlling a power supply
2: setting module
21A to 21C: register
23: controller for controlling a power supply
7: demultiplexer
8：SDRAM
9：SDRAM
S301 to S303: step (a)
S401 to S405: step (a)

Claims (10)

1. A setting method for a synchronous dynamic random access memory, SDRAM, comprising:
controlling the SDRAM to switch to an initialization setting mode, wherein the initialization setting mode is used for initializing the SDRAM;
setting a value of at least one register in the initialization setting mode; and
the SDRAM is set according to the value of the at least one register.
2. The setting method as claimed in claim 1, wherein the step of setting the SDRAM according to the value of the at least one register further comprises:
the value of the at least one register is decoded via an interpreter and the SDRAM is set according to the decoded value.
3. The setting method as claimed in claim 1, wherein the at least one register includes an instruction index register, and the step of setting the SDRAM according to a value of the at least one register further includes:
and setting the instruction index and the instruction running time of the SDRAM according to the numerical value of the instruction index register.
4. The setting method as claimed in claim 1, wherein the at least one register includes a macro instruction and mode information register, and the step of setting the SDRAM according to the value of the at least one register further includes:
and setting the macro instruction, the mode address and the mode data of the SDRAM according to the numerical value of the macro instruction and the mode information register.
5. The setting method as claimed in claim 1, wherein the at least one register includes a macro instruction and mode information register, and the step of setting the SDRAM according to the value of the at least one register further includes:
and setting the read check state of the mode register of the SDRAM according to the macro instruction and the numerical value of the mode information register.
6. The setting method as claimed in claim 1, wherein the step of controlling the SDRAM to switch to the initialization setting mode further comprises:
and stopping the bus data access mode of the SDRAM and controlling the SDRAM to switch to the initialization setting mode.
7. The setting method as claimed in claim 1, wherein the step of setting the SDRAM according to the value of the at least one register further comprises:
an initialization operation is triggered to set the SDRAM according to the value of the at least one register.
8. The setting method as claimed in claim 7, wherein the step of setting the SDRAM according to the value of the at least one register further comprises:
the initialization operation is triggered based on the value of the synchronization control register to set the SDRAM according to the value of the at least one register.
9. The setting method according to claim 1, further comprising:
it is determined whether to end the initialization setting mode.
10. The setting method according to claim 9, further comprising:
when the initialization setting mode is judged to be ended, the SDRAM is controlled to be switched to a bus data access mode.
CN202111658500.0A 2021-12-31 2021-12-31 Setting module for synchronous dynamic random access memory and setting method thereof Pending CN116417034A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117931265A (en) * 2024-03-25 2024-04-26 英诺达(成都)电子科技有限公司 Command management method, device, electronic apparatus, storage medium, and program product

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117931265A (en) * 2024-03-25 2024-04-26 英诺达(成都)电子科技有限公司 Command management method, device, electronic apparatus, storage medium, and program product

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