JP5107776B2 - Memory controller, memory system, and method of writing data to memory device - Google Patents

Description

  The present invention relates to a memory controller for writing data to a memory device having a nonvolatile memory, a memory system having such a memory controller, and a method for writing data to the memory device.

  For writing data into the nonvolatile memory, a memory controller such as a ROM writer is usually used. The memory controller performs verification in order to confirm that data has been normally written during or after data is written to the nonvolatile memory.

The ROM writer can write data to a plurality of nonvolatile memories at a time. Data to be written (hereinafter referred to as “write data”) is temporarily written in a volatile memory built in the ROM writer from a host device provided outside the ROM writer and then written in a plurality of nonvolatile memories. It is. At this time, the write data written in the volatile memory is held as it is.
The ROM writer reads out the write data written in the nonvolatile memory at the time of verification (that is, nonvolatile memory cell data written in the nonvolatile memory cell) and writes it in the built-in volatile memory. As a result, two pieces of data are stored in the volatile memory of the ROM writer. The ROM writer performs verification by comparing these two pieces of data (write data before writing to the nonvolatile memory serving as verification data and write data read from the nonvolatile memory serving as verification data). When the ROM writer determines that the data writing to the nonvolatile memory is normally performed by the verification, the ROM writer ends the writing to the nonvolatile memory.

  As described above, the volatile memory built in the ROM writer needs to have a capacity for storing at least two data used for verification. Further, the amount of data that can be written to the nonvolatile memory at a time depends on the storage capacity of the volatile memory of the ROM writer. Furthermore, since the time required for verification becomes longer due to writing to and reading from the volatile memory, the entire data writing operation takes time.

By using a non-volatile memory and a volatile memory in a single memory device, the above-mentioned drawbacks of the ROM writer can be compensated.
Patent Document 1 describes that write data is temporarily stored in a buffer (volatile memory) of a memory device, and the stored write data is written in a nonvolatile memory. After the write data is written to the nonvolatile memory, verification is performed using the write data stored in the buffer and the write data written to the nonvolatile memory.
Patent Document 2 describes an invention of a memory card including a plurality of flash memories and an SRAM (Static Random Access Memory) connected to a memory controller. The write data is temporarily written in the SRAM when the write data is written to the flash memory. The verify is performed at each stage of the voltage applied at the time of writing.
Patent Document 3 describes an invention of a semiconductor disk having a plurality of flash memories and a write buffer. By sequentially writing the write data to the vacant flash memory, the disadvantage of the flash memory having a slow write speed is compensated.
JP 2006-309829 A WO2003 / 060722 JP 2001-144853 A

  In Patent Documents 1 to 3 as described above, two data used for verification are read from the same memory device during verification. This eliminates the need for a volatile memory on the memory controller side. However, since two data used for verification are read in order from one memory device, the read time tends to be long. As a result, the time required for the entire writing operation to the memory device becomes longer.

  In view of the above problems, an object of the present invention is to provide a technique for reducing the time required for the entire writing operation to a memory device as compared with the conventional technique.

  A memory controller of the present invention that solves the above problems includes a plurality of memory devices that incorporate a nonvolatile memory and a volatile memory, and that can copy data from the volatile memory to the nonvolatile memory. Connectable. The memory controller has a one-to-one correspondence with the connectable memory devices, each enabling writing of the data to the volatile memory of the corresponding memory device, and the corresponding memory device A plurality of memory control units that enable reading of the data from the nonvolatile memory and the volatile memory, and the first data read from the nonvolatile memory of one memory device by the one memory control unit, A verification unit that performs verification using the second data read from the volatile memory of another memory device by the memory control unit.

The memory controller of the present invention can write data only to the volatile memory of the memory device, and does not write directly to the nonvolatile memory. In the nonvolatile memory, data is written from a volatile memory in the same memory device. Because of such a configuration, it is not necessary to prepare a volatile memory in the memory controller. Therefore, the amount of data that can be written to the nonvolatile memory at a time depends on the volatile memory of the memory device and does not depend on the memory controller.
The data (first data) written in the nonvolatile memory is verified using data (second data) written in the volatile memory of another memory device, which is different from the memory device having the nonvolatile memory. Done. Data is read from these two memory devices by different memory control units. For this purpose, in the memory controller of the present invention, for example, the one memory control unit and the other memory control unit operate in synchronization with each other, whereby the other memory control unit The second data can be read simultaneously with the memory controller reading the first data. Conventionally, the first data and the second data are read from one memory device, and it is difficult to read them simultaneously. Since the memory controller of the present invention can read simultaneously, it is possible to read two data used for verification faster than the conventional method. When one memory control unit and another memory control unit operate in synchronization with each other, the one memory control unit and the other memory control unit respectively correspond to the volatile memory of the corresponding memory device. The same data can be written simultaneously.
The one memory control unit reads, for example, data written in the volatile memory of the other memory device via the other memory control unit, and writes the data to the volatile memory of the one memory device. It may be a configuration. In such a configuration, for example, data can be written to the volatile memory of one memory device using another memory device. In addition, when one memory device is replaced with another new memory device, writing to the new memory device becomes possible using the other memory device.
Different lines may be connected between the verification unit and the one memory control unit and between the verification unit and the other memory control unit. In such a configuration, since the first data and the second data are acquired by different lines, they can be acquired simultaneously, and high-speed verification is possible.

  In such a memory controller of the present invention, for example, at least one of the plurality of memory control units can be configured as a ROM writer including a socket into which a corresponding memory device can be inserted and removed. Data can be transmitted and received through this socket. Since the socket can be inserted and removed, it can be replaced with another memory device when writing is completed.

A memory system according to the present invention includes a plurality of memory devices each including a nonvolatile memory and a volatile memory, and capable of copying data from the volatile memory to the nonvolatile memory, and the plurality of memory devices. The memory devices have a one-to-one correspondence, each enabling writing of data to the volatile memory of the corresponding memory device, and from the non-volatile memory and the volatile memory of the corresponding memory device. A plurality of memory control units that enable data reading, and the first data read from the non-volatile memory of one memory device by one memory control unit is volatilized by another memory control unit to another memory device. A verification unit that performs verification using the second data read from the memory.
Such a memory system can be mounted on a computer system, for example, and can be used as a nonvolatile memory of the computer system.

  The data writing method of the present invention includes a plurality of memory devices each including a nonvolatile memory and a volatile memory, and capable of copying data from the volatile memory to the nonvolatile memory. In this method, data is written by a memory controller capable of transmitting / receiving data to / from the plurality of memory devices. In this data writing method, the memory controller first writes the same data to the volatile memory of each memory device simultaneously through different paths, and the memory controller A second stage of transmitting control data for copying the data written in the volatile memory to the non-volatile memory, and the memory device receiving the control data and writing the volatile memory in the volatile memory A third stage of copying data to the non-volatile memory containing the data; and the memory controller writes the first data written in the non-volatile memory of one predetermined memory device to the volatile memory of another memory device And a fourth step of performing verification using the second data.

If the memory controller can simultaneously acquire the first data and the second data used for the verification in the four stages, high-speed verification is possible.
If it is determined in the fourth step that the verification fails, the memory controller retransmits the control data to the memory device, for example. By doing so, for example, when data copying is not successfully completed with one memory device, data copying can be performed again. Thereafter, re-verification is performed by performing the third and fourth steps again.
Further, if it is determined as a result of the verification that the first data is normally written in the nonvolatile memory of the one memory device, the memory controller stores the first data in a volatile memory of another new memory device. Data in the volatile memory of the other memory device may be written. Using the other memory device, data can be written to the nonvolatile memory of the new memory device.

  According to the present invention as described above, the data written in the nonvolatile memory is verified using the data written in the volatile memory of another memory device different from the memory device incorporating the nonvolatile memory. As a result, verification can be performed at a higher speed than before. Therefore, the time required for the entire writing operation to the memory device can be reduced as compared with the conventional case.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a configuration diagram of a memory system 1 according to an embodiment of the present invention.
The memory system 1 includes a memory controller 10 and two memory devices 20a and 20b each having nonvolatile memories 21a and 21b and volatile memories 22a and 22b. In this embodiment, a configuration using two memory devices 20a and 20b will be described, but a configuration including more memory devices may be used. An input device 2, an output device 3, and a host device 4 are connected to the memory controller 10. The input device 2 is a device for inputting various instruction data for operating the memory controller 10. For example, a keyboard or an operation panel can be used as the input device 2. The output device 3 outputs information necessary for operation of the memory controller 10, operation results, and the like by image or sound. For example, a display or a speaker can be used as the output device 3. The memory controller 10, the input device 2, and the output device 3 may be integrally configured. The host device 4 is an information processing device such as a general-purpose personal computer. The host device 4 transmits write data to the memory controller 10 in response to a request from the memory controller 10.

  The memory controller 10 includes an input interface (input I / F) 11, an output interface (output I / F) 12, a communication control unit 13, a verification unit 14 that performs verification, and memory devices 20 a and 20 b connected to the first and first 2 memory control units 15a and 15b and a control unit 16 are provided. The memory controller 10 acquires write data to be written in the nonvolatile memories 21a and 21b of the memory devices 20a and 20b from the host device 4, and stores the write data in the volatile memories 22a and 22b of the memory devices 20a and 20b. Write at the same time.

The input I / F 11 performs interface control with the input device 2. The input I / F 11 sends various instruction data input from the input device 2 to the control unit 16. In particular, in this embodiment, write instruction data for instructing writing to the memory devices 20 a and 20 b is sent from the input device 2 to the control unit 16 via the input I / F 11.
The output I / F 12 performs interface control with the output device 3. The output I / F 12 outputs an operation result in a form that can be output by the output device 3 under the control of the control unit 16. The output I / F 12 displays, for example, the status of the writing operation to the memory devices 20a and 20b on the output device 3, displays the end of writing when the writing ends, and displays the end of verification when the verification ends.
The communication control unit 13 is an interface for performing communication with the host device 4. For example, when there is write instruction data from the input device 2 to the memory controller 10, the communication control unit 13 acquires write data from the host device 4 under the control of the control unit 16.
In this embodiment, write data is acquired from the host device 4. However, the present invention is not limited to this. For example, the input device 2 may input the write data together with the write instruction data. In this case, the host device 4 and the communication control unit 13 are not necessary.

  The verification unit 14 verifies the write data written in the nonvolatile memories 21 a and 21 b of the memory devices 20 a and 20 b under the control of the control unit 16. The verifying unit 14, for example, write data captured from the nonvolatile memory 21 a of the memory device 20 a (data to be verified read from the cell after writing to the nonvolatile memory cell) and the volatile property of the memory device 20 b. The verification is performed by comparing with verification data (verification data that is data to be written to the nonvolatile memory cell) used for verification fetched from the memory 22b. That is, the verification data used for verification is fetched from a volatile memory of a memory device different from a memory device having a nonvolatile memory in which write data to be verified data is written. In addition to simple comparison of write data and verification data, the verification unit 14 performs verification by, for example, comparing hash values of write data and verification data. The verification data may be the same as the write data, or may be data dedicated for verification. For example, when verification is performed by comparing hash values, the verification data may be a hash value of write data.

The first and second memory control units 15a and 15b are controlled by the control unit 16 and provided corresponding to the memory devices 20a and 20b, respectively. The first and second memory control units 15a and 15b include a data line 17 for transmitting / receiving write data, verification data, data to be verified, and the like to / from the memory devices 20a and 20b, and the memory devices 20a and 20b. A control line 18 for transmitting and receiving control data for controlling the operation is connected to the corresponding memory devices 20a and 20b. Write data and verification data are written to and read from the memory devices 20a and 20b under the control of the control data. Further, the control data causes the memory devices 20a and 20b to copy the write data from the volatile memories 22a and 22b to the nonvolatile memories 21a and 21b (details will be described later). Corresponding memory devices 20a and 20b are connected to the first and second memory control units 15a and 15b, respectively, via sockets (not shown), for example. The memory devices 20a and 20b can be inserted and removed by the socket. As many memory devices as the number of memory control units can be connected to the memory controller 10. With such a configuration, the memory controller 10 can transmit and receive data through different paths between the memory devices 20a and 20b.
The first memory control unit 15a writes write data to the volatile memory 22a of the memory device 20a in order to write data to the nonvolatile memory 21a. In addition, the write data is read from the nonvolatile memory 21a of the memory device 20a as the data to be verified, and from the volatile memory 22a for use in verification of the write data to be verified of the nonvolatile memory 21b of the memory device 20b. Read verification data.
The second memory control unit 15b has the same function as the first memory control unit 15a. The second memory control unit 15b writes the write data to the volatile memory 22b of the memory device 20b at the same time that the first memory control unit 15a writes the write data to the volatile memory 22a of the memory device 20a.
The verification data is normally written into the volatile memories 22a and 22b at the same time when the first and second memory control units 15a and 15b write the write data into the volatile memories 22a and 22b of the memory devices 20a and 20b.

  The first and second memory control units 15a and 15b are connected to the verification unit 14 through different lines. Each line includes a verification data line for transmitting / receiving verification data and a verification data line for transmitting / receiving verification data. With such a configuration, verification data and verification target data used for verification can be provided to the verification unit 14 at a higher speed than before.

  The control unit 16 controls the operation of each component of the memory controller 10 according to the instruction data input from the input device 2 and performs processing according to the instruction. The control unit 16 generates control data to be input to the memory devices 20a and 20b and inputs the control data to the first and second memory control units 15a and 15b. In addition, the control unit 16 controls the operations of the first and second memory control units 15a and 15b with one signal, for example. Therefore, the writing and reading operations of the first and second memory control units 15a and 15b are performed in synchronization.

FIG. 2 is a schematic cross-sectional view of the memory device 20a. The memory device 20b has the same configuration as the memory device 20a. Here, the configuration of the memory device 20a will be described, and the description of the configuration of the memory device 20b will be omitted.
An MCP (Multi Chip Package) stacking technique is used for the memory device 20 a, and a nonvolatile memory 21 a and a volatile memory 22 a are stacked on the substrate 23. The nonvolatile memory 21a and the volatile memory 22a are bonded to each other with an adhesive (for example, polyimide, silicone, epoxy-based thermally conductive adhesive) that is an example of an interlayer insulator (not shown), a spacer, or the like. 21a is bonded to the substrate 23 with an adhesive (not shown). FIG. 2 shows an example of the structure of the memory device, and a PoP (Package-on-Package) structure in which the nonvolatile memory 21a and the volatile memory 22a are built in one package may be used. In addition to the nonvolatile memory 21a and the volatile memory 22a, for example, a semiconductor chip having the function of the memory controller 10 may be further provided.
The non-volatile memory 21 a and the volatile memory 22 a are connected to each other by terminals 24 through which the same data is input. A ball electrode 25 is disposed below the substrate 23. The wiring 24 and the ball electrode 25 are connected by an internal wiring of the substrate 23. A power supply voltage is applied to the ball electrode 25 from the outside of the memory device 20a, and various data (for example, write data, verification data, data to be received, etc.) are connected to the memory controller 10 via the data line 17 and the control line 18. Verification data, etc.) are transmitted and received.

  FIG. 3 is a diagram illustrating a circuit configuration of the memory device 20a. The write data written from the memory controller 10 to the nonvolatile memory 21a is once written to the volatile memory 22a, and then copied from the volatile memory 22a to the nonvolatile memory 21a. When reading out the write data written in the nonvolatile memory 21a and the verification data written in the volatile memory 22a, the memory controller 10 directly reads out from the nonvolatile memory 21a and the volatile memory 22a.

  Control data such as various clock signals, various command signals, and address signals AD, and a data signal DQ that is write data are transmitted and received between the memory controller 10, the nonvolatile memory 21a, and the volatile memory 22a. . Which of the nonvolatile memory 21a and the volatile memory 22a is activated is determined by the chip select signals CS1 and CS2.

The volatile memory 22a decodes a row address select signal RAS, a column address select signal CAS, and a write enable signal WE, which are control data output from the memory controller 10, and accesses a memory cell of the volatile memory 22a (not shown). A command determination circuit is provided.
The nonvolatile memory 21a has a function of writing data read from the volatile memory 22a to different addresses. This function is realized by the command determination circuit 26 and the address control circuit 27.

FIG. 4 is a circuit diagram showing an example of the command determination circuit 26 and the address control circuit 27 provided in the nonvolatile memory 21a.
The command determination circuit 26 includes an inverter 31, AND gates 32 to 35, and switches 36 and 37.

  The inverter 31 outputs an inverted signal of the chip select signal CS1. That is, when the nonvolatile memory 21a is selected and the chip select signal CS1 becomes low level, the inverter 31 outputs high level.

In the AND gate 32, when the row address select signal RAS is at a low level and the column address select signal CAS and the write enable signal WE are at a high level, the output active signal ACT is at a high level.
The AND gate 33 outputs a high level when the column address select signal CAS and the write enable signal WE are at a low level while the chip select signal CS1 is at a low level, and the row address select signal RAS is at a high level. In the switch 36, when an execution code determination signal CBC described later is at a low level, the output of the AND gate 33 is output as the write signal WT. When the execution code determination signal CBC is at a high level, a high level pulse is forcibly output to the write signal WT.
In the AND gate 34, when the row address select signal RAS and the write enable signal WE become low level and the column address select signal CAS becomes high level, the output precharge signal PR becomes high level.
The AND gate 35 outputs a high level when the chip select signal CS1 is at a low level, the column address select signal CAS is at a low level, and the row address select signal RAS and the write enable signal WE are at a high level. In the switch 37, when an execution code determination signal CBC, which will be described later, is at a low level, the output of the AND gate 35 is output to the read signal RD, and when the execution code determination signal CBC is at a high level, the low level is the read signal RD. Is output.

The address control circuit 27 includes an execution code determination circuit 38, an address latch latency adding circuit 39, a row address latch circuit 40, and a column address latch circuit 41.
The execution code determination circuit 38 receives the data signal DQ, the active signal ACT, and the precharge signal PR. When the active signal ACT becomes high level, the execution code CMD included in the data signal DQ is acquired. With the execution code CMD, the nonvolatile memory 21a enters a mode in which data can be copied from the volatile memory 22a. The execution code CMD determines whether or not to add address latency. When the data transfer source (volatile memory 22a) and the transfer destination (nonvolatile memory 21a) are different depending on the execution code CMD, the execution code determination signal CBC becomes high level. The execution code determination signal CBC becomes low level when the precharge signal PR becomes high level.

  The address latch latency adding circuit 39 receives the clock signal CLK and the execution code determination signal CBC. When the execution code determination signal CBC is at a high level, an address latency control signal for adding latency to the addresses in the row address latch circuit 40 and the column address latch circuit 41 is output. The latency value of the address to be added may be “1” or may be a value exceeding “1”. When the execution code determination signal CBC is at a low level, the latency value of the address is “0”. The latency value can be set in advance by a mode register setting cycle (not shown).

  The row address latch circuit 40 receives the active signal ACT, the address latency control signal from the address latch latency adding circuit 39, and the address signal AD. When the active signal ACT becomes high level, the row address is latched and the row address ROWAD is output with the address latency according to the address latency control signal from the address latch latency adding circuit 39.

  The column address latch circuit 41 receives the write signal WT, the read signal RD, the address latency control signal from the address latch latency adding circuit 39, and the address signal AD. When the write signal WT becomes high level, the column address is latched with the address latency according to the address latency control signal from the address latch latency adding circuit 39, and the column address COLAD is output. When the read signal RD is at a high level, the address latency is “0” and the address signal AD is latched.

  A write control circuit (not shown) of the volatile memory 22a will be described. As will be described later, the write data of the nonvolatile memory 21a is read data of the volatile memory 22a, and the nonvolatile memory 21a latches the data. Therefore, the write latency WCL of the nonvolatile memory 21a (the number of CLKs from the command until the write data is latched) is the same as the read latency RCL of the volatile memory 22a that is the transfer source. The data latch latency adding circuit included in the write control circuit of the volatile memory 22a is a circuit similar to the address latch latency adding circuit 39, and receives the execution code determination signal CBC and the clock signal CLK of the execution code determination circuit 38, A data latch circuit (not shown) is controlled.

  With reference to FIG. 5, the write data copy operation from the volatile memory 22a to the nonvolatile memory 21a performed in the memory device 20a will be described. FIG. 5 is a timing chart showing the operation of the memory device 20a. The clock signal CLK, the chip select signal CS2, the row address select signal RAS, the column address select signal CAS, the write enable signal WE, the address signal AD, and the data signal DQ are input from the first memory control unit 15a of the memory controller 10. . The middle stage active signal ACT, read signal RD, write signal WT, and precharge signal PR are memory commands of the volatile memory 22a. The lower stage active signal ACT, read signal RD, write signal WT, and precharge signal PR are memory commands of the nonvolatile memory 21a.

At time T1, when the chip select signal CS2 and the row address select signal RAS are at a low level, and the column address select signal CAS and the write enable signal WE are at a high level, the active signal ACT of the nonvolatile memory 21a is at a high level. At the same time, the execution code CMD is acquired from the data signal DQ. In the present embodiment, the address latency AL of the transfer destination is “+1”. The read latency RCL of the transfer source is “+2”. The write latency WCL of the transfer destination is “+2”, and the numerical value is matched with the read latency RCL of the transfer source. That is, the read latency RCL and the write latency WCL are equal.
The active signal ACT of the volatile memory 22a becomes high level. As a result, the row address “3A” is set (latched) in the volatile memory 22a.

  At time T2, since the address latency AL of the transfer destination is “1”, the non-volatile memory 21a sets (latches) the row address “1B” at a timing delayed by 1 CLK from the active signal ACT.

At time T3, when the chip select signal CS2 and the column address select signal CAS become low level, and the row address select signal RAS and the write enable signal WE become high level, the read signal RD of the volatile memory 22a becomes high level. As a result, the column address “B0” of the volatile memory 22a is set (latched).
On the other hand, in the nonvolatile memory 21a, the execution code determination signal CBC is at a high level, so that the write signal WT is at a high level.
Since the read latency RCL of the volatile memory 22a is set to “2”, the data of the volatile memory 22a is output as the data signal DQ after two cycles (time T5).

At time T4, since the address latency AL of the transfer destination is “1”, the column address “A0” is set (latched) in the nonvolatile memory 21a.
The transfer destination address given to the nonvolatile memory 21a can be established within the same cycle (T2, T4) as the transfer source address given to the volatile memory 22a by the address latency technique.

  At times T5 to T8, the data D1 to D4 stored in the address “3AB0” of the volatile memory 22a are sequentially read by the read latency RCL = 2, and the volatile memory is transferred to the address “1BA0” of the nonvolatile memory 21a. Data D1 to D4 are written with the same write latency WCL = 2 as that of 22a.

  At time T9, since the row address select signal RAS and the write enable signal WE are at a low level and the column address select signal CAS is at a high level, the precharge signal PR is at a high level in the nonvolatile memory 21a. As a result, the execution code determination signal CBC becomes low level, and the nonvolatile memory 21a returns to the normal operation mode.

  As described above in detail, in this memory device 20a, the data copy from the volatile memory 22a serving as the transfer source to the non-volatile memory 21a serving as the transfer destination is performed using the control data from the memory controller 10 to the memory device 20a. It can be performed only by the operation in the above.

FIG. 6 is a process flowchart of a write operation to the memory device 20a by the memory system 1.
The memory controller 10 receives write instruction data from the input device 2 to the memory devices 20a and 20b (step S10). The memory controller 10 writes (transfers) write data from the host device 4 to the memory devices 20a and 20b. The write data is simultaneously written into the volatile memories 22a and 22b of the memory devices 20a and 20b by the memory controller 10 (step S20).

When the write data is written in the volatile memories 22a and 22b of the memory devices 20a and 20b, the memory controller 10 transmits the control data to the memory devices 20a and 20b. When the memory devices 20a and 20b receive the control data from the memory controller 10, the write data written in the volatile memories 22a and 22b in the memory devices 20a and 20b are converted into nonvolatile data in the same memory devices 20a and 20b. Copy to the memories 21a and 21b, respectively (step S30).
Next, the memory controller 10 verifies the write data written in the nonvolatile memories 21a and 21b. Here, verification of write data written in the nonvolatile memory 21a of the memory device 20a will be described as an example.
The memory controller 10 reads the write data as the data to be verified from the nonvolatile memory 21a of the memory device 20a by the first memory control unit 15a. The read write data is sent to the verification unit 14. At the same time, the memory controller 10 reads verification data from the volatile memory 22b of the memory device 20b by the second memory control unit 15b. The read verification data is sent to the verification unit 14 (step S40). The verification data is, for example, write data written from the memory controller 10 to the volatile memory 22b in step S20.

The verification unit 14 performs verification by comparing the write data read as the data to be verified from the nonvolatile memory 21a of the memory device 20a with the verification data read from the volatile memory 22b of the memory device 20b. (Step S50). That is, the verification of the write data written in the nonvolatile memory of one memory device is performed by the verification data read from the volatile memory of another memory device.
As a result of the verification, if the writing to the nonvolatile memory 21a is normally performed (verification pass), the memory controller 10 ends the writing to the memory device 20a (step S60: Y). When writing is not normally performed (verify fail), for example, as shown below, there are a method of returning to step S20 and a method of returning to step 30 (step S60: N).
If the cause of the verify failure is in the volatile memory 22a, the memory controller 10 returns to step S20, and starts the write operation from the stage of rewriting (transferring) the write data from the host device 4 to the volatile memory 22a. And the process is repeated until the verification ends normally (loop from step S20 to step S60). Since the memory controller 10 is not provided with a memory for temporarily storing the write data, the write data is again written from the host device 4 to the volatile memory 22a.
If the cause of the verify failure is in the nonvolatile memory 21a, the memory controller 10 returns to step S30 and starts the write operation from the stage of copying the write data from the volatile memory 22a to the nonvolatile memory 21a. Is repeated until the process ends normally (loop from step S30 to step S60). Since the memory controller 10 is not provided with a memory for temporarily storing the write data, the write data is copied again from the volatile memory 22a to the nonvolatile memory 21a.

  When a memory device that has been written, including verification, is replaced with another new memory device, writing of write data to the other memory device can be performed at high speed. For example, when the memory device 20a that has been written is inserted and removed from the socket and another new memory device is inserted, the second memory control unit 15b and the first memory control unit 15a are connected to the volatile memory of this memory device. And write data can be written from the volatile memory 22b of the memory device 20b. As a result, there is no need to newly transfer write data from the host device 4, and writing is performed at high speed. In addition, the host device 4 can communicate with other devices (not shown) without disturbing from the memory controller 10 or the memory system 1 after transferring the write data to any one of the volatile memories.

Conventionally, in order to read write data and verification data as data to be verified from the same memory device, it is necessary to add time required for each. However, in this embodiment as described above, since the verification data is read from a memory device different from the memory device to which the write data that is the verification data is written, the write data and the verification data can be read simultaneously. is there. Therefore, the time required for verification can be shortened compared to the conventional case. Thereby, the time of the entire writing operation can be shortened.
In addition to being used as a ROM writer, the memory controller 10 can be used, for example, as a device that is provided in a computer system and writes to a memory device in the same computer system. When provided in the computer system, for example, the memory device is connected so that it cannot be inserted into or removed from the memory controller.

It is a block diagram of the memory system of this embodiment. It is a schematic sectional drawing of a memory device. It is a figure explaining the circuit structure of a memory device. It is a circuit diagram which shows an example of the command determination circuit and address control circuit with which the non-volatile memory was equipped. 3 is a timing chart showing the operation of the memory device. 4 is a process flowchart of a write operation to a memory device by the memory system.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Memory system, 10 ... Memory controller, 11 ... Input interface, 12 ... Output interface, 13 ... Communication control part, 14 ... Verification part, 15a ... 1st memory control part, 15b ... 2nd memory control part, 16 ... Control 17, data line, 18, control line, 20 a, 20 b, memory device, 21 a, 21 b, nonvolatile memory, 22 a, 22 b, volatile memory, 23, substrate, 24, wiring, 25, ball electrode, 26,. Command determination circuit, 27 ... Address control circuit, 31 ... Inverter, 32-35, AND gate, 36, 37 ... Switch, 38 ... Execution code determination circuit 38, 39 ... Address latch latency addition circuit, 40 ... Row address latch circuit, 41 ... Column address latch circuit, 2 ... Input device, 3 ... Output device, 4 ... Host device

Claims (11)

A memory controller having a built-in nonvolatile memory and a volatile memory and capable of connecting a plurality of memory devices capable of copying data from the volatile memory to the nonvolatile memory,
Each of the connectable memory devices has a one-to-one correspondence, each enabling writing of the data to the volatile memory of the corresponding memory device, and the non-volatile memory of the corresponding memory device and the A plurality of memory controllers that allow reading of the data from volatile memory;
The first data read from the non-volatile memory of one memory device by one memory control unit is verified using the second data read from the volatile memory of another memory device by another memory control unit. And a verification unit
Memory controller. The one memory control unit and the other memory control unit operate in synchronization with each other, whereby the other memory control unit reads the first data from the one memory control unit. At the same time, the second data is read out.
The memory controller according to claim 1. The one memory control unit and the other memory control unit simultaneously write the same data to the volatile memory of the corresponding memory device,
The memory controller according to claim 2. The one memory control unit reads data written in the volatile memory of the other memory device through the other memory control unit, and writes the data to the volatile memory of the one memory device.
The memory controller according to claim 1 or 2. Between the verification unit and the one memory control unit and between the verification unit and the other memory control unit are connected by different lines, respectively.
The memory controller according to claim 1. At least one of the plurality of memory control units includes a socket into which a corresponding memory device can be inserted and removed, and transmits and receives data through the socket.
The memory controller according to claim 1. A plurality of memory devices each including a nonvolatile memory and a volatile memory, and capable of copying data from the volatile memory to the nonvolatile memory;
The plurality of memory devices correspond one-to-one, and each enables writing of data to the volatile memory of the corresponding memory device, and the nonvolatile memory and the volatile of the corresponding memory device A plurality of memory control units that enable reading of data from the memory;
The first data read from the non-volatile memory of one memory device by one memory control unit is verified using the second data read from the volatile memory of another memory device by another memory control unit. And a verification unit
Memory system. A method of writing data to a plurality of memory devices each including a nonvolatile memory and a volatile memory by a memory controller capable of transmitting / receiving data to / from the plurality of memory devices,
A first stage in which the memory controller writes the same data simultaneously in different paths to the volatile memory of each memory device;
A second stage in which the memory controller transmits control data for causing each memory device to copy data written in the volatile memory to the nonvolatile memory;
A third stage in which each memory device receives the control data and copies the data written in the built-in volatile memory to the built-in nonvolatile memory;
A fourth stage in which the memory controller verifies the first data written in the non-volatile memory of a predetermined memory device using the second data written in the volatile memory of another memory device; ,including,
How to write data. In the four steps, the memory controller simultaneously acquires the first data and the second data used for the verification.
The data writing method according to claim 8. In the fourth step, when the verify is determined to fail, the memory controller retransmits the control data to the memory device.
10. The data writing method according to claim 8 or 9. As a result of the verification, when it is determined that the first data is normally written in the nonvolatile memory of the one memory device, the memory controller stores the first data in the volatile memory of another new memory device. Write the volatile memory data of other memory devices,
The data writing method according to claim 8.

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