CN104102592B - The write method and device of a kind of memory - Google Patents
The write method and device of a kind of memory Download PDFInfo
- Publication number
- CN104102592B CN104102592B CN201310115706.8A CN201310115706A CN104102592B CN 104102592 B CN104102592 B CN 104102592B CN 201310115706 A CN201310115706 A CN 201310115706A CN 104102592 B CN104102592 B CN 104102592B
- Authority
- CN
- China
- Prior art keywords
- data
- write
- buffer
- unit
- address
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Abstract
The invention provides the write method and device of a kind of memory；Method includes：The instruction of write buffer is input into, by the zeros data in buffer；The corresponding data of writing in the address of N number of unit in memory and each address are write into buffer；Wherein N is positive integer；Data of writing in buffer are verified and write parallel to N number of unit；Wherein, described being write to any one unit refers to：The data of writing of the address in the buffer corresponding to the unit are write into the unit.What the present invention can improve memory writes speed.
Description
Technical field
The present invention relates to electronic applications, more particularly to a kind of memory write method and device.
Background technology
Today of fast-developing and electronic market high speed expansion in various electronic technology, the demand of memory rapidly increases
It is long.In numerous type of memory, NOR-type flash memory is extensive due to the advantages of with random read-write speed, soon, unfailing performance is high
Be applied to various electronic equipments, such as mobile product, automotive electronics etc..It was developed so far from 1988, NOR-type flash memory technology is closelyed follow
Market development demand also updates constantly progressive, and not only capacity increasingly increases, unfailing performance more and more higher, random read-write speed
Also it is more and more faster.
For memory, each a unit cell correspondences piece wordline word line and bit line bit line.
If to carry out program (writing) to a cell, a high pressure is exactly added to read signal WL, contraposition signal BL adds a spy
Determine voltage.Than 9 cell for being arranged in the row of 3 row 3 as shown in Figure 1, the cell of the first row receives WL<n+1>, the second row
Cell receives WL<n>, the cell receptions WL of the third line<n-1>, from left to right first row cell receive BL<n-1>, secondary series
Cell receives BL<n>, tertial cell receptions BL<n+1>.
In current design, mainly a word word (16bits) or a byte byte (8bits) are entered
Row program, each word are required for carrying out verify (verification), program that (16 bit lines are according to programming data
Program data add corresponding high pressure or low pressure) and verify process.Have the disadvantage the write-in for continuous multiple address
Data will repeat multiple single address operations, waste the substantial amounts of verify and program times.
And as the systemic-function of various electronic equipments is complicated, modern processors speed is continuously increased, to memory
Frequently read and write into most basic operation, the speed of writing of memory increasingly influences the speed of whole processor, therefore
Read or write speed turns into actual applications weighs the more and more important performance indications of NOR-type flash memory.Manufacturer is urgent more and more
The erasable speed of raising memory is needed, so needing to improve present situation.
The content of the invention
The technical problem to be solved in the present invention be how to improve memory write speed.
In order to solve the above problems, the invention provides a kind of write method of memory, including：
The instruction of write buffer is input into, by the zeros data in buffer；
The corresponding data of writing in the address of N number of unit in memory and each address are write into buffer；Wherein N is just whole
Number；
Data of writing in buffer are verified and write parallel to N number of unit；Wherein, it is described to any
Individual unit is write and refers to：The data of writing of the address in the buffer corresponding to the unit are write into the unit.
Further, N is 64 or 128.
Further, also include before the step of instruction of the input write buffer：
When in one or more addresses data occur mistake when, be loaded into again one or more of addresses and this one
The volume of individual or multiple addresses writes data to the buffer；
After all data validations are errorless, perform it is described input write buffer instruction the step of.
Further, the data of writing in buffer are verified to N number of unit and write parallel
Step includes：
S1, data will be respectively write in buffer respectively and the data write in the unit in data corresponding address are compared
Compared with, obtain and N number of unit the one-to-one N number of comparative result in address；When writing the data in data and unit and being identical or
It is out-of-date that unit has been encoded, and the comparative result is 1；
S2, N number of comparative result is write into original volume in buffer described in data cover as corresponding address
Write data；Judge to write data whether all 1 in the buffer；If it is terminate；If it is not, then respectively will be slow
Each is rushed in device for 0 writes during data write the unit that this is write in data corresponding address, return to step S1.
Present invention also offers a kind of device of writing of memory, including：
Buffer；
Control unit, the instruction for being input into write buffer, by the zeros data in buffer；And by N in memory
The corresponding data of writing in the address of individual unit and each address write into buffer；N is positive integer；
Unit is write, N number of unit is verified and write parallel for the data of writing in buffer；Its
In, described being write to any one unit refers to：The data of writing of the address of the unit in the buffer are write into the unit.
Further, N is 64 or 128.
Further, described control unit is additionally operable to before the instruction of input write buffer, if it is determined that one or more
There is mistake in data in address, then be loaded into one or more of addresses and one or more addresses again writes number
According to the buffer；After judging that all data validations are errorless, the instruction of write buffer is input into.
Further, write write data of the unit in buffer N number of unit is verified and compiled parallel
Write and refer to：
It is described write unit and will respectively write data in buffer respectively write in the unit in data corresponding address with this
Data are compared, and obtain and the one-to-one N number of comparative result in the address of N number of unit；When writing the number in data and unit
According to it is identical when or unit be encoded it is out-of-date, the comparative result be 1；Using N number of comparative result as corresponding address
Write and original in buffer described in data cover write data；Judge in the buffer whether write data all
1；If it is terminate；If it is not, then respectively by buffer each write this and write data accordingly for 0 data of writing
In unit on location；Then above-mentioned steps are repeated up to the data all 1 in the buffer.
Technical scheme can be operated to many bit line, that is, can be simultaneously to multiple bits'
Data carry out verify or program, greatly reduce the verify times and averagely arrive the program times of each unit；And
Required data need not be input into every time during verify and program, time-consuming；Greatly increase
The efficiency of verify and program.
Brief description of the drawings
Fig. 1 is the structural representation of existing memory；
Fig. 2 is the schematic flow sheet of the memory write method of embodiment one.
Specific embodiment
Technical scheme is described in detail below in conjunction with drawings and Examples.
Embodiment one, a kind of write method of memory, as shown in Fig. 2 including：
The instruction of write buffer is input into, by the zeros data in buffer；
The corresponding data of writing in the address of N number of unit in memory and each address are write into buffer；Wherein, N is just whole
Number；
Data of writing in buffer are verified and write parallel to N number of unit；Wherein, it is described to any
Individual unit is write and refers to：The data of writing of the address in the buffer corresponding to the unit are write into the unit.
In an embodiment of the present embodiment, N is 64 or 128.
Present embodiment can once write the data for completing 64bits or 128bits；To write feelings during 128bit data
As a example by condition, circuit is connected into 8 or 16 bit lines by an original wordline, be changed to a wordline and connect 128 bit lines.If
The driving force (strength) of pump is not enough to support the program of 64bit and above bit numbers, can be by strengthening pump
Clk (clock) frequencies and pump electric capacity strengthen the driving force of pump, the current requirements for making it meet 64 or 128bit enough,
With reach can simultaneously program possibility.
, just for a word, existing program processes are just for 8 or 16 for existing verify processes
Bits is operated.The method of the present embodiment is during program, while the multiple for sending multiple addresses writes data, them
It is stored temporarily in buffer buffer, it is possible to many bit line (64bits or 128bits) are operated, also
Can be that verify is carried out to the data of 64bits or 128bits simultaneously, greatly reduce the time of verify, and can be right
The data of 64bits or 128bits carry out program simultaneously, the required data during verify and program
It is time-consuming from buffer load (loading), it is not necessary to input every time；Although carrying out the program times to 128bits simultaneously
Program time presidents are carried out relative to 16bits, but are averagely then greatly reduced to the program times on a bit,
Improve efficiency during write-in.Can increase to equivalent to verify processes carries out verify to 4 word or 8 word,
And originally in a time of the program of word, program can have been carried out to 4 word or 8 word.So
Just greatly increase the efficiency of verify and program.
In an embodiment of the present embodiment, it is described input write buffer instruction the step of before can also include：
When in one or more addresses data occur mistake when, be loaded into again one or more of addresses and this one
The volume of individual or multiple addresses writes data to the buffer；
After all data validations are errorless, perform it is described input write buffer instruction the step of.
Wrong data modification can be turned into correct data by the implementation method during erase (erasing) is not.
In existing scheme, during some are continuously written into, if having carried out the write-in of the data of mistake to an address, if
Want to be corrected, erase can only be carried out to this block, then carry out writing correct data again；And in the write-in of write buffer
During first need load data, it is allowed to the multiple load data in address, be defined by last time data and write, from
And reduce more write-in number of times.
It is described to have the step of N number of unit is verified and write parallel in an embodiment of the present embodiment
Body can include：
S1, data will be respectively write in buffer respectively and the data write in the unit in data corresponding address are compared
Compared with, obtain and N number of unit the one-to-one N number of comparative result in address；When writing the data in data and unit and being identical or
It is out-of-date that unit has been encoded, and the comparative result is 1；
S2, N number of comparative result is write into original volume in buffer described in data cover as corresponding address
Write data；Judge to write data whether all 1 in the buffer；If it is terminate；If it is not, then respectively will be slow
Each is rushed in device for 0 writes during data write the unit that this is write in data corresponding address, return to step S1.
Above-mentioned steps are illustrated with the cell distance of 4, it is assumed that the data of writing in buffer are below：
0011；
The data in cell on appropriate address are：
0101；
Then in first time verify, comparative result is：
1011；
Wherein, the 1st, 4 because in buffer to write data identical with the data in unit, so comparative result is
“1”；And the data in the unit of the 3rd are " 0 ", therefore the unit is the unit write, and comparative result is also 1 (program
The cell for crossing is time of day, is the metal-oxide-semiconductor for being enhanced threshold value, except being operated by erase, cannot otherwise change and arrive
The state of " 1 ").
Comparative result load entered into buffer cover original to write data；Data of writing in due to buffer are not all
" 1 ", now owns " 0 " by program, that is, write the unit of the 2nd, and writes data for " 0 ".
The data in cell after program on appropriate address are：
0001；
Then second verify is carried out, i.e., is compared again；Comparative result (has write data more in buffer before this
It is newly " 1011 ") be：
1111；
Wherein, the data in the unit of the 1st, 2,3 are 0, therefore comparative result is " 1 "；And the 4th due in buffer
To write data identical with the data in unit, so comparative result is also " 1 ".
Comparative result is written back into buffer, is substituted and original is write data；At this moment all data are all in buffer
" 1 ", completes the process of verification and programming.
If do not succeeded during the unit for writing the 2nd, the data in real cell remain as " 0101 " during beginning,
It (is " 1011 " that the 4th data are identical therefore compare in buffer that comparative result remains as " 1011 " when so carrying out second verify
Relatively result is " 1 ", and the 1st, 3 bit location mileages are " 1 " according to for " 0 " therefore comparative result)." 1011 " are written back into buffer, due to
Still it is not complete " 1 ", it will continue to write the unit of the 2nd.It can be seen that, until writing successfully, i.e., data are " 0001 " in unit
Untill, will obtain writing the situation that data are " 1111 " in buffer, terminate verification and write.
The situation for being verified parallel to 64 or 128 bit locations and being programmed can be so that the rest may be inferred.
Embodiment two, a kind of memory write device, including：
Buffer；
Control unit, the instruction for being input into write buffer, by the zeros data in buffer；And by N in memory
The corresponding data of writing in the address of individual unit and each address write into buffer；N is positive integer；
Unit is write, N number of unit is verified and compiled parallel for the data of writing in the buffer
Write；Wherein, described being write to any one unit refers to：The data of writing of the address of the unit in the buffer are write into the list
Unit.
In an embodiment of the present embodiment, N is 64 or 128.
In an embodiment of the present embodiment, described control unit can be also used for the instruction in input write buffer
Before, if it is determined that there is mistake in data in one or more addresses, then be loaded into again one or more of addresses and this one
The volume of individual or multiple addresses writes data to the buffer；It is input into the finger of write buffer again after judging that all data validations are errorless
Order.
In an embodiment of the present embodiment, the unit of writing writes data to described in the buffer
N number of unit is verified and write parallel：
It is described write unit and will respectively write data in buffer respectively write in the unit in data corresponding address with this
Data are compared, and obtain and the one-to-one N number of comparative result in the address of N number of unit；When writing the number in data and unit
According to it is identical when or unit be encoded it is out-of-date, the comparative result be 1；Using N number of comparative result as corresponding address
Write and original in buffer described in data cover write data；Judge in the buffer whether write data all
1；If it is terminate；If it is not, then respectively by buffer each write this and write data accordingly for 0 data of writing
In unit on location；Then above-mentioned steps are repeated up to the data all 1 in the buffer.
Certainly, the present invention can also have other various embodiments, ripe in the case of without departing substantially from spirit of the invention and its essence
Know those skilled in the art and work as and various corresponding changes and deformation, but these corresponding changes and change can be made according to the present invention
Shape should all belong to scope of the claims of the invention.
Claims (6)
1. a kind of write method of memory, including：
The instruction of write buffer is input into, by the zeros data in buffer；
The corresponding data of writing in the address of N number of unit in memory and each address are write into buffer；Wherein N is positive integer；
Data of writing in buffer are verified and write parallel to N number of unit, including：
S1, data will be respectively write in buffer respectively and this is write the data in the unit in data corresponding address and is compared,
Obtain and the one-to-one N number of comparative result in the address of N number of unit；It is when writing the data in data and unit and being identical or single
It is out-of-date that unit has been encoded, and the comparative result is 1；
S2, original in buffer described in data cover write number using N number of comparative result as writing for corresponding address
According to；Judge to write data whether all 1 in the buffer；If it is terminate；If it is not, then respectively by buffer
In each write during data write the unit that this is write in data corresponding address for 0, return to step S1.
2. the method for claim 1, it is characterised in that：
N is 64 or 128.
3. the method for claim 1, it is characterised in that also include before the step of the instruction of the input write buffer：
When there is mistake in data in one or more addresses, be loaded into again one or more of addresses and this or
The volume of multiple addresses writes data to the buffer；
After all data validations are errorless, perform it is described input write buffer instruction the step of.
4. a kind of memory writes device, it is characterised in that including：
Buffer；
Control unit, the instruction for being input into write buffer, by the zeros data in buffer；And by N number of list in memory
The corresponding data of writing in address and each address of unit write into buffer；N is positive integer；
Unit is write, N number of unit is verified and write parallel for the data of writing in buffer, including：
Data will be respectively write in buffer respectively write the data in the unit in data corresponding address with this and be compared, obtain and N
The one-to-one N number of comparative result in the address of individual unit；When writing the data in data and unit and being identical or unit by
Write out-of-date, the comparative result is 1；Delay described in data cover
Rush and original in device write data；Judge to write data whether all 1 in the buffer；If it is terminate；If
Be not, then respectively by buffer each write during data write the unit that this is write in data corresponding address for 0；Then weigh
Above-mentioned steps are carried out again up to the data all 1 in the buffer.
5. device is write as claimed in claim 4, it is characterised in that：
N is 64 or 128.
6. device is write as claimed in claim 4, it is characterised in that：
Described control unit is additionally operable to before the instruction of input write buffer, if it is determined that data occur in one or more addresses
Mistake, the then volume for being loaded into one or more of addresses and one or more addresses again writes data to the buffer；
After judging that all data validations are errorless, the instruction of write buffer is input into.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310115706.8A CN104102592B (en) | 2013-04-03 | 2013-04-03 | The write method and device of a kind of memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310115706.8A CN104102592B (en) | 2013-04-03 | 2013-04-03 | The write method and device of a kind of memory |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104102592A CN104102592A (en) | 2014-10-15 |
| CN104102592B true CN104102592B (en) | 2017-06-13 |
Family
ID=51670760
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310115706.8A Active CN104102592B (en) | 2013-04-03 | 2013-04-03 | The write method and device of a kind of memory |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104102592B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101188142A (en) * | 2006-09-01 | 2008-05-28 | 三星电子株式会社 | Flash memory device using program data cache and programming method thereof |
| CN101197189A (en) * | 2006-09-15 | 2008-06-11 | 三星电子株式会社 | Flash memory devices and programming methods for the same |
| CN101740126A (en) * | 2008-11-13 | 2010-06-16 | 旺宏电子股份有限公司 | Memory and method applied in one program command for the memory |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100943141B1 (en) * | 2008-01-10 | 2010-02-18 | 주식회사 하이닉스반도체 | Method of programming a non volatile memory device |
-
2013
- 2013-04-03 CN CN201310115706.8A patent/CN104102592B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101188142A (en) * | 2006-09-01 | 2008-05-28 | 三星电子株式会社 | Flash memory device using program data cache and programming method thereof |
| CN101197189A (en) * | 2006-09-15 | 2008-06-11 | 三星电子株式会社 | Flash memory devices and programming methods for the same |
| CN101740126A (en) * | 2008-11-13 | 2010-06-16 | 旺宏电子股份有限公司 | Memory and method applied in one program command for the memory |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104102592A (en) | 2014-10-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11775178B2 (en) | Data storage systems and methods for improved data relocation based on read-level voltages associated with error recovery | |
| US7921339B2 (en) | Flash storage device with data correction function | |
| US8812784B2 (en) | Command executing method, memory controller and memory storage apparatus | |
| US8289771B2 (en) | Data reading method and control circuit and memory controller using the same | |
| US8392794B2 (en) | Non-volatile memory device and data processing method thereof | |
| CN110413535B (en) | Memory controller and operation method thereof | |
| CN108694096A (en) | Controller, storage system and its operating method | |
| US8775760B2 (en) | Modifying a host interface setting for a non-volatile memory module | |
| US9063888B2 (en) | Program code loading and accessing method, memory controller, and memory storage apparatus | |
| CN110058799A (en) | Memory device and the method for operating memory device | |
| US20190304557A1 (en) | Memory device, memory system including the memory device, and method of operating memory device | |
| CN110727398A (en) | Memory system and operating method thereof | |
| CN107797821A (en) | Retry read method and the device using this method | |
| CN109426446A (en) | Storage system and its operating method | |
| CN109388514B (en) | Memory system and operating method thereof | |
| CN108447513A (en) | Storage system and its operating method | |
| US8738847B2 (en) | Data writing method, and memory controller and memory storage apparatus using the same | |
| CN104102592B (en) | The write method and device of a kind of memory | |
| CN111951871A (en) | Memory device, memory system including the same, and method of operating the same | |
| KR102632452B1 (en) | Semiconductor memory device and operating method thereof | |
| US20130246687A1 (en) | Data writing method, memory controller and memory storage apparatus | |
| CN103984614A (en) | Monitoring method, monitoring device and electronic device | |
| CN110209433B (en) | Method for identifying concentrators of different models | |
| TWI707362B (en) | Data writing method and storage controller | |
| US9229798B2 (en) | Error handling method, memory storage device and memory controlling circuit unit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address |
Address after: Room 101, Floor 1-5, Building 8, Yard 9, Fenghao East Road, Haidian District, Beijing 100094 Patentee after: Zhaoyi Innovation Technology Group Co.,Ltd. Address before: 100083 12 Floors, Block A, Tiangong Building, Science and Technology University, 30 College Road, Haidian District, Beijing Patentee before: GIGADEVICE SEMICONDUCTOR(BEIJING) Inc. |
|
| CP03 | Change of name, title or address |