CN116403993B - Wafer acceptance test structure and detection method - Google Patents

Wafer acceptance test structure and detection method Download PDF

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Publication number
CN116403993B
CN116403993B CN202310614497.5A CN202310614497A CN116403993B CN 116403993 B CN116403993 B CN 116403993B CN 202310614497 A CN202310614497 A CN 202310614497A CN 116403993 B CN116403993 B CN 116403993B
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wire
pad
tested
bonding pad
bonding
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CN116403993A (en
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赖福东
刘翔
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Yuexin Semiconductor Technology Co ltd
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Yuexin Semiconductor Technology Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy

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  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

The application provides a wafer acceptance test structure and a wafer acceptance test method, which are used for detecting wire resistance on a wafer, and comprise a first wire to be tested, a second wire to be tested, a first bonding pad, a second bonding pad, a third bonding pad, a fourth bonding pad and a fifth bonding pad, wherein the wire widths of the first wire to be tested and the second wire to be tested are different, the first wire to be tested and the second wire to be tested are arranged along a first direction, the first bonding pad, the second bonding pad, the third bonding pad, the fourth bonding pad and the fifth bonding pad are arranged along a second direction, the second direction is perpendicular to the first direction, the first wire to be tested is provided with a first end and a second end which are oppositely arranged, the second wire to be tested is provided with a third end and a fourth end which are oppositely arranged, the first end is respectively connected with the first bonding pad and the second bonding pad, the second end is respectively connected with the third end and the third bonding pad, and the fourth end is respectively connected with the fourth bonding pad and the fifth bonding pad, so that the efficiency of detecting wire resistance is improved, and the number of bonding pads is reduced.

Description

Wafer acceptance test structure and detection method
Technical Field
The application relates to the technical field of semiconductors, in particular to a wafer acceptance test structure and a wafer acceptance test method.
Background
Wafer acceptance test (Wafer AcceptanceTest, WAT), which is a method for judging whether a Wafer process is good or not for testing and monitoring production, is a common monitoring parameter, and is usually detected by using a Wafer acceptance test (testkey) structure of a Wafer.
At present, 4 bonding pads are needed for testing the resistance of one wire, if the wire is of two different sizes, 8 bonding pads are needed for completing the resistance test of the two wires, and multiple tests are needed, so that the testing efficiency of the resistance of the wire is low, and meanwhile, the positions on a wafer are limited, and more bonding pads cannot be placed.
Disclosure of Invention
In view of the above, the present application provides a wafer acceptance test structure and a testing method thereof, so as to improve the testing efficiency of the wire resistance and reduce the number of pads.
The application provides a wafer acceptance test structure, which is used for detecting the resistance of a wire on a wafer and comprises a first wire to be tested, a second wire to be tested, a first bonding pad, a second bonding pad, a third bonding pad, a fourth bonding pad and a fifth bonding pad, wherein the wire widths of the first wire to be tested and the second wire to be tested are different, the first wire to be tested and the second wire to be tested are arranged along a first direction, the first bonding pad, the second bonding pad, the third bonding pad, the fourth bonding pad and the fifth bonding pad are arranged along a second direction, the second direction is perpendicular to the first direction, the first wire to be tested is provided with a first end part and a second end part which are oppositely arranged, the second wire to be tested is provided with a third end part and a fourth end part which are respectively connected with the first bonding pad and the second bonding pad, the second end part is respectively connected with the third end part and the third bonding pad, and the fourth end part is respectively connected with the fourth bonding pad and the fifth bonding pad.
The first bonding pad is connected with the first end portion through a first connecting wire, the second bonding pad is connected with the first end portion through a second connecting wire, the third bonding pad is connected with the second end portion through a third connecting wire, the fourth bonding pad is connected with the fourth end portion through a fourth connecting wire, and the fifth bonding pad is connected with the fourth end portion through a fifth connecting wire.
The first bonding pad, the second bonding pad and the third bonding pad are all positioned on one side of the first wire to be tested, and the fourth bonding pad and the fifth bonding pad are all positioned on the other side of the first wire to be tested.
The second bonding pad is arranged between the first bonding pad and the third bonding pad, the third bonding pad is positioned on one side of the second bonding pad, which is close to the first wire to be tested and the second wire to be tested, and the fifth bonding pad is positioned on one side of the fourth bonding pad, which is far away from the first wire to be tested.
The first bonding pad, the second bonding pad, the third bonding pad, the fourth bonding pad and the fifth bonding pad are located in a cutting channel of the wafer.
The line width of the first wire to be tested is smaller than that of the second wire to be tested.
The patch cord further comprises a patch cord, wherein the patch cord is provided with a head end and a tail end which are oppositely arranged, the head end is connected with the fourth end, the tail end is connected with the fifth connecting wire, and the fourth connecting wire is connected in the middle area of the head end and the tail end.
The first connecting line, the second connecting line, the third connecting line, the fourth connecting line, the fifth connecting line and the patch cord are all located in the dicing channels of the wafer.
The application also provides a detection method, which adopts the wafer acceptance test structure to carry out detection, and comprises the following steps:
applying current to the first bonding pad and the fifth bonding pad, and testing to obtain a current value I;
applying a first voltage between the second bonding pad and the third bonding pad to obtain a first voltage value V 1 ；
Applying a second voltage between the third bonding pad and the fourth bonding pad to obtain a second voltage value V 2 ；
Obtaining the resistance of the first wire to be tested as V1/(I. SQR) 1 ) The resistance of the second wire to be tested is V 2 /(I*SQR 2 ) The method comprises the steps of carrying out a first treatment on the surface of the Wherein SQR 1 For the number of blocks of the first wire to be tested, SQR 2 And the number of the square blocks of the second wire to be tested.
Wherein the first voltage V is measured by a voltmeter 1 Said second voltage V 2 。
The application provides a wafer acceptance test structure and a test method, which are used for detecting wire resistance on a wafer, and comprise a first wire to be tested, a second wire to be tested, a first bonding pad, a second bonding pad, a third bonding pad, a fourth bonding pad and a fifth bonding pad, wherein the wire widths of the first wire to be tested and the second wire to be tested are different, the first wire to be tested and the second wire to be tested are arranged along a first direction, the first bonding pad, the second bonding pad, the third bonding pad, the fourth bonding pad and the fifth bonding pad are arranged along a second direction, the second direction is perpendicular to the first direction, the first wire to be tested is provided with a first end part and a second end part which are oppositely arranged, the second wire to be tested is provided with a third end part and a fourth end part which are oppositely arranged, the first end part is respectively connected with the first bonding pad and the second bonding pad, the second end part is respectively connected with the third end part and the third bonding pad, and the fourth end part is respectively connected with the fourth bonding pad and the fifth bonding pad, so that the number of the bonding pads is reduced, and meanwhile, the test efficiency of the wire resistance is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of a wafer acceptance test structure provided by the present application.
Reference numerals:
10. a wafer acceptance test structure; 100. a first wire to be tested; 101. a first end; 102. a second end; 200. a second wire to be tested; 201. a third end; 202. a fourth end; 300. a first bonding pad; 400. a second bonding pad; 500. a third bonding pad; 600. a fourth pad; 700. a fifth bonding pad; 710. a first connecting line; 720. a second connecting line; 730. a third connecting line; 740. a fourth connecting line; 750. a fifth connecting line; 760. and a patch cord.
Detailed Description
The following description of the embodiments of the present application will be made in detail and with reference to the accompanying drawings, wherein it is apparent that the embodiments described are only some, but not all embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to fall within the scope of the application. The various embodiments described below and their technical features can be combined with each other without conflict.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present application and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate in order to describe the embodiments of the application herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. Furthermore, in the description and in the claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element or "connected" to the other element through a third element.
The application provides a wafer acceptance test structure which is used for detecting wire resistance on a wafer and comprises a first wire to be tested, a second wire to be tested, a first bonding pad, a second bonding pad, a third bonding pad, a fourth bonding pad and a fifth bonding pad, wherein the wire widths of the first wire to be tested and the second wire to be tested are different, the first wire to be tested and the second wire to be tested are arranged along a first direction, the first bonding pad, the second bonding pad, the third bonding pad, the fourth bonding pad and the fifth bonding pad are arranged along a second direction, the second direction is perpendicular to the first direction, the first wire to be tested is provided with a first end and a second end which are oppositely arranged, the second wire to be tested is provided with a third end and a fourth end which are oppositely arranged, the first end is respectively connected with the first bonding pad and the second bonding pad, the second end is respectively connected with the third end and the third bonding pad, and the fourth end is respectively connected with the fourth bonding pad and the fifth bonding pad.
According to the application, the first end part is respectively connected with the first bonding pad and the second bonding pad, the second end part is respectively connected with the third end part and the third bonding pad, and the fourth end part is connected with the fourth bonding pad and the fifth bonding pad, so that the resistance of two wires with different sizes can be tested, the resistance of the two wires with different sizes can be tested only by 5 bonding pads, the number of bonding pads is reduced, the occupied space of the bonding pads is reduced, the space of a cutting path is saved, meanwhile, the resistance of the two wires with different sizes can be tested by 5 bonding pads, the resistance test of the two wires with different sizes can be completed only by 3 times of operation, 4 times of operation is not required, and the test efficiency of the resistance of the wires is improved; the arrangement directions of the first to-be-tested wire and the second to-be-tested wire are set to be perpendicular to the arrangement directions of the first bonding pad, the second bonding pad, the third bonding pad, the fourth bonding pad and the fifth bonding pad, so that the wire resistance is conveniently tested, and the testing efficiency of the wire resistance is further improved.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a wafer acceptance test structure provided by the present application. The application provides a wafer acceptance test structure, which is used for detecting wire resistance on a wafer, and comprises a first wire 100 to be tested, a second wire 200 to be tested, a first bonding pad 300, a second bonding pad 400, a third bonding pad 500, a fourth bonding pad 600 and a fifth bonding pad 700, wherein the wire widths of the first wire 100 to be tested and the second wire 200 to be tested are different, the first wire 100 to be tested and the second wire 200 to be tested are arranged along a first direction y, a second direction x is perpendicular to the first direction y, the first bonding pad 300, the second bonding pad 400, the third bonding pad 500, the fourth bonding pad 600 and the fifth bonding pad 700 are arranged along a second direction x, the first wire 100 to be tested is provided with a first end 101 and a second end 102 which are oppositely arranged, the second wire 200 to be tested is provided with a third end 201 and a fourth end 202 which are oppositely arranged, the first end 101 is respectively connected with the first bonding pad 300 and the second bonding pad 400, the second end 102 is respectively connected with the third end 201 and the third bonding pad 500, and the fourth end 202 is respectively connected with the fourth bonding pad 600 and the fifth bonding pad 700. The first wire to be tested 100 and the second wire to be tested 200 are aluminum wires. The first wire 100 to be tested and the second wire 200 to be tested are resistor structures of different sizes that the chip needs to use.
The first bonding pad 300 is connected to the first end portion 101 through a first connection line 710, the second bonding pad 400 is connected to the first end portion 101 through a second connection line 720, the third bonding pad 500 is connected to the second end portion 102 through a third connection line 730, the fourth bonding pad 600 is connected to the fourth end portion 202 through a fourth connection line 740, and the fifth bonding pad 700 is connected to the fourth end portion 202 through a fifth connection line 750. The bonding pads are connected with the wires to be tested through connecting wires, so that the bonding pads can be well arranged in the wafer.
The first pad 300, the second pad 400 and the third pad 500 are all located at one side of the first wire 100 to be tested, and the fourth pad 600 and the fifth pad 700 are all located at the other side of the first wire 100 to be tested, so that a point to be detected can be rapidly determined when the wire resistance is tested, thereby further improving the detection efficiency of the wire resistance.
The second bonding pad 400 is disposed between the first bonding pad 300 and the third bonding pad 500, the third bonding pad 500 is located at one side of the second bonding pad 400 close to the first wire to be tested 100 and the second wire to be tested 200, and the fifth bonding pad 700 is located at one side of the fourth bonding pad 600 far away from the first wire to be tested 100, so that a point to be tested can be rapidly determined when testing the wire resistance, thereby further improving the testing efficiency of the wire resistance.
The line width of the first wire 100 to be tested is smaller than the line width of the second wire 200 to be tested, and the length of the first wire 100 to be tested is equal to the length of the second wire 200 to be tested, that is, the size of the first wire 100 to be tested is smaller than the size of the second wire 200 to be tested.
The wafer acceptance test structure 10 further includes an interposer 760, where the interposer 760 has a head end and a tail end that are disposed opposite to each other, the head end is connected to the fourth end 202, the tail end is connected to the fifth connecting wire 750, and the fourth connecting wire 740 is connected to an intermediate area between the head end and the tail end, so that the bonding pads can be better arranged in the wafer, and the bonding wires are prevented from crossing each other to cause interference, thereby avoiding affecting the detection accuracy of the corresponding wires.
The first, second, third, fourth and fifth pads 300, 400, 500, 600 and 700 are located in dicing streets of a wafer. Optionally, the first connection line 710, the second connection line 720, the third connection line 730, the fourth connection line 740, the fifth connection line 750, and the patch cord 760 are all disposed in the scribe line with the pad, so as to avoid the pad, the connection line, and the patch cord 760 occupying the actual area of the wafer, that is, to avoid the pad, the connection line, and the patch cord 760 overlapping the chip.
In another embodiment, the wire to be tested further includes a third wire to be tested and a sixth pad, the wire widths of the third wire to be tested and the first wire to be tested 100 and the second wire to be tested 200 are different, the third wire to be tested has a fifth end and a sixth end which are disposed opposite to each other, the sixth end is connected to the second pad 400 and the first end 101, and the fifth end is connected to the first pad 300 and the sixth pad. On the original basis, a third wire to be tested and a sixth bonding pad are arranged, so that the resistance of three different wires can be tested by only 6 bonding pads, the resistance test of 3 different wires can be finished by only 4 operations, the testing efficiency of the wire resistance is improved, the number of bonding pads is reduced, and the cost is reduced.
The application also provides a detection method, which adopts the wafer acceptance test structure 10 provided by the application for detection, and comprises the following steps:
step 1: a current is applied to the first pad 300 and the fifth pad 700, and a current value I is measured.
Specifically, the current value I of the first wire to be tested 100 and the second wire to be tested 200 is measured by using an ammeter. Alternatively, the current values I of the first wire 100 to be tested and the second wire 200 to be tested may be tested in other manners.
Step 2: a first voltage is applied between the second pad 400 and the third pad 500 to obtain a first voltage value V1.
Specifically, a first voltage is applied between the second pad 400 and the third pad 500, and a voltmeter test is used to obtain a first voltage value V1 of the first wire 100 to be tested. Alternatively, the voltage value of the first wire 100 to be tested may be tested in other manners.
Step 3: applying a second voltage between the third pad 500 and the fourth pad 600 to obtain a second voltage value V2;
obtaining the resistance of the first wire 100 to be tested as V1/(i×sqr1), and the resistance of the second wire 200 to be tested as V2/(i×sqr2); wherein SQR1 is the number of blocks of the first wire 100 to be tested, SQR2 is the number of blocks of the second wire 200 to be tested.
Specifically, a second voltage is applied between the third pad 500 and the fourth pad 600, and a voltmeter test is used to obtain a second voltage value V2 of the second wire 200 to be tested. Alternatively, the voltage value of the second wire 200 to be tested may be tested in other manners.
And calculating the square resistance of the corresponding wire to be tested according to the obtained current value and voltage value. The number of blocks of the wire to be tested may be expressed as SQR, which is related to the wire length L and the wire width W of the wire to be tested, and is obtained by dividing the wire length L by the wire width W.
It should be noted that the sequence of steps 1, 2 and 3 may be interchanged, which is not limited herein.
The application provides a wafer acceptance test structure 10 and a detection method, wherein a first end part 101 is connected with a first bonding pad 300 and a second bonding pad 400, a second end part 102 is connected with a third end part 201 and a third bonding pad 500, and a fourth end part 202 is connected with a fourth bonding pad 600 and a fifth bonding pad 700, so that the resistance of two wires with different sizes can be tested, the resistance of the two wires with different sizes can be tested only by 5 bonding pads, the number of bonding pads is reduced, the occupied space of the bonding pads is reduced, the space of a cutting path is saved, meanwhile, the resistance of the two wires with different sizes is tested by 5 bonding pads, and during the test, the current of the wires with different sizes can be obtained by only carrying out 1 time of current test and only 2 times of voltage test on the rest 3 bonding pads, namely the resistance test of the wires with different sizes can be completed by only 3 times of operation, the resistance test of the wires with different sizes is not required, the operation efficiency of the wires with different sizes is improved by 4 times of operation is not required; the arrangement direction of the first wire 100 to be tested and the second wire 200 to be tested is set to be perpendicular to the arrangement direction of the first pad 300, the second pad 400, the third pad 500, the fourth pad 600 and the fifth pad 700, so that the wire resistance is tested, thereby further improving the testing efficiency of the wire resistance.
In the description of the embodiments of the present application, the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, are merely for convenience in describing the technical solutions of the respective embodiments, and do not indicate or imply that the devices or elements must have a specific orientation, be configured and operated in a specific orientation, and are not to be construed as limiting the present application.
The foregoing embodiments of the present application are not limited to the above embodiments, but are intended to be included within the scope of the present application as defined by the appended claims and their equivalents.

Claims (10)

1. The utility model provides a wafer acceptance test structure, its characterized in that is used for detecting the resistance of wire on the wafer, including first wire to be tested, second wire to be tested, first pad, second pad, third pad, fourth pad and fifth pad, first wire to be tested is different with the wire width of second wire to be tested, first wire to be tested with the second wire to be tested is arranged along first direction, first pad, second pad, third pad, fourth pad and fifth pad are arranged along the second direction, the second direction is perpendicular with first direction, first wire to be tested has relative setting's first tip and second tip, second wire to be tested has relative setting's third tip and fourth tip, first tip respectively with first pad and second pad are connected, the second tip respectively with third tip and third pad are arranged along the second direction, the fourth tip is perpendicular with fourth pad respectively.
2. The wafer acceptance test structure of claim 1, wherein said first bonding pad is connected to said first end by a first connection line, said second bonding pad is connected to said first end by a second connection line, said third bonding pad is connected to said second end by a third connection line, said fourth bonding pad is connected to said fourth end by a fourth connection line, and said fifth bonding pad is connected to said fourth end by a fifth connection line.
3. The wafer acceptance test structure of claim 1, wherein the first pad, the second pad, and the third pad are all located on one side of the first wire under test, and the fourth pad and the fifth pad are all located on the other side of the first wire under test.
4. A wafer acceptance test structure of any of claims 1-3, wherein said second pad is disposed between said first pad and said third pad, said third pad is located on a side of said second pad that is adjacent to said first wire to be tested and said second wire to be tested, and said fifth pad is located on a side of said fourth pad that is remote from said first wire to be tested.
5. The wafer acceptance test structure of any of claims 1-3, wherein said first pad, said second pad, said third pad, said fourth pad, and said fifth pad are located in a scribe line of said wafer.
6. A wafer acceptance test structure of any of claims 1-3 wherein the linewidth of said first wire to be tested is less than the linewidth of said second wire to be tested.
7. The wafer acceptance test structure of claim 2, further comprising a patch cord having a head end and a tail end disposed opposite to each other, said head end being connected to said fourth end, said tail end being connected to said fifth connection line, said fourth connection line being connected in an intermediate region of said head end and said tail end.
8. The wafer acceptance test structure of claim 7, wherein said first connection line, said second connection line, said third connection line, said fourth connection line, said fifth connection line, and said patch cord are all located in dicing lanes of said wafer.
9. A method of inspection using the wafer acceptance test structure of any of claims 1-8, comprising:
applying current to the first bonding pad and the fifth bonding pad, and testing to obtain a current value I;
applying a first voltage between the second bonding pad and the third bonding pad to obtain a first voltage value V 1 ；
Applying a second voltage between the third bonding pad and the fourth bonding pad to obtain a second voltage value V 2 ；
Obtaining the resistance of the first wire to be tested as V1/(I. SQR) 1 ) The resistance of the second wire to be tested is V 2 /(I*SQR 2 ) The method comprises the steps of carrying out a first treatment on the surface of the Wherein SQR 1 For the number of blocks of the first wire to be tested, SQR 2 And the number of the square blocks of the second wire to be tested.
10. The method of claim 9, wherein the first voltage V is measured using a voltmeter 1 Said second voltage V 2 。
CN202310614497.5A 2023-05-29 2023-05-29 Wafer acceptance test structure and detection method Active CN116403993B (en)

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