CN105226051B - Semi-conductor test structure and conductive plunger and the detection method of active region contact performance - Google Patents
Semi-conductor test structure and conductive plunger and the detection method of active region contact performance Download PDFInfo
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- CN105226051B CN105226051B CN201410240692.7A CN201410240692A CN105226051B CN 105226051 B CN105226051 B CN 105226051B CN 201410240692 A CN201410240692 A CN 201410240692A CN 105226051 B CN105226051 B CN 105226051B
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Abstract
A kind of semi-conductor test structure and conductive plunger and the detection method of active region contact performance.Test structure includes：At least two groups of conductive plungers, every group of two conductive plungers, one end of every group of conductive plunger are connected to the other end active area of same selection transistor by metal silicide；Every group of conductive plunger carries out test using 4-Wire Kelvin Test method and obtains an equation, two equation of simultaneous, you can the accurate resistance for obtaining conductive plunger and the contact structures with metal silicide and.Due to being connected completely by metal silicide between the conductive plunger and contact structures of above-mentioned acquisition, thus conductive plunger with contact good contact structures resistance and, if in detected semiconductor structure conductive plunger with and contact structures resistance and more than above-mentioned resistance and, then illustrate that it is entirely metal silicide to have no metal silicide in detected semiconductor structure between conductive plunger and Semiconductor substrate or be not, that is the two contact performance is bad, conversely, the two contact performance is good.
Description
Technical field
The present invention relates to technical field of semiconductors more particularly to a kind of semi-conductor test structures and conductive plunger and active area
The detection method of contact performance.
Background technology
In recent years, in order to increase storage density, nand flash memory is widely used in the design of nonvolatile memory.
Nand flash memory includes the storage array that multiple memory cells are formed, and each memory cell includes：NAND memory cell strings, with
And the selection transistor for selecting the NAND memory cell strings, one end active area of selection transistor are coupled to NAND storages
One end active area of unit string, the other end active area of selection transistor receive selection telecommunications by being coupled with conductive plunger
Number.
In order to improve device density, reduce critical size, occur in industry using the double composition method (Self- of autoregistration
Align Double Pattern, SaDP) make NAND memory cell strings, using the above method make each storage unit
The active area of middle selection transistor all extends in one direction.
In the prior art, in order to reduce the contact resistance between conductive plunger and the active area of Semiconductor substrate, general meeting
Metal silicide is made on the active area.However, found in actual process, above-mentioned conductive plunger and Semiconductor substrate active area it
Between often and non-fully coupled by metal silicide, this is caused in storing process, the reduced performance of NAND storage arrays.
In order to find the above problem in time, there are also existing some to obtain contact structures resistance between conductive plunger and active area
The scheme of value, but mostly connect using by multiple conductive plungers, contact structures, Semiconductor substrate active area, metal interconnecting wires, by
In conductive plunger, Semiconductor substrate active area, metal interconnecting wires resistance generally by empirical value to realize from total test knot
It is stripped out in fruit, the resistance of contact structures and the far smaller than resistance of Semiconductor substrate active area in addition, thus, the above method
The contact structures resistance value of acquisition is inaccurate, this influences the judgement of the contact performance between conductive plunger and active area.
In view of this, the present invention provides a kind of semi-conductor test structure and conductive plunger and the detection of active region contact performance
Method, with the contact performance progress accurate judgement between conductive plunger and Semiconductor substrate active area.
Invention content
The present invention solves the problems, such as be how between conductive plunger and Semiconductor substrate active area contact performance carry out standard
Really judge.
To solve the above problems, an aspect of of the present present invention provides a kind of semi-conductor test structure, the test structure is formed
On a semiconductor substrate, there is NAND memory array, the unit packet of the NAND memory array in the Semiconductor substrate
It includes：The NAND memory cell strings formed using the double composition methods of autoregistration and the choosing for selecting the NAND memory cell strings
Select transistor；Wherein, one end active area of the selection transistor is connect with one end active area of the NAND memory cell strings,
Wherein, the test structure includes：
At least two groups of conductive plungers, every group of two conductive plungers, one end of every group of conductive plunger is connected by metal silicide
Be connected to the other end active area of same selection transistor, the active area length in first group of conductive plunger between two conductive plungers with
Active area length in second group of conductive plunger between two conductive plungers is unequal；
Signal applies weld pad and detection welding pad, and the other end of each conductive plunger connects a signal and applies weld pad and one
Detection welding pad.
Optionally, one end of first group of conductive plunger and one end of second group of conductive plunger are connected to same selection transistor
Active area.
Optionally, a conductive plunger in the conductive plunger and second group of conductive plunger in first group of conductive plunger
It shares.
Optionally, the semi-conductor test structure further includes third group conductive plunger, and the one of the third group conductive plunger
End is connected to the other end active area of another selection transistor by the metal silicide, and two is conductive in third group conductive plunger
Active area length in active area length, first group of conductive plunger between plug between two conductive plungers is inserted with second group of conduction
Active area length in plug between two conductive plungers is unequal.
Optionally, one end of first group of conductive plunger is connected to different selection transistors from one end of second group of conductive plunger
Active area.
Optionally, the selection transistor is bit line selection transistor, and the active area with metal silicide is drain region.
Optionally, the selection transistor is source line options transistor, and the active area with metal silicide is source region.
Optionally, the current signal size that two conductive plungers are applied in first group of conductive plunger and second group of conductive plunger
In the current signal that is applied of two conductive plungers differ in size.
Optionally, the Semiconductor substrate is silicon, germanium or silicon-on-insulator.
In addition, another aspect of the present invention provides a kind of conductive plunger and the detection method of active region contact performance, use
Semi-conductor test structure described in above-mentioned any one obtains completely by metal silicide connecting between conductive plunger and active area
When connecing, the resistance of the conductive plunger and contact structures and, and with conductive plunger in detected semiconductor structure with and contact
The resistance of structure and compare, if the latter is more than the former, conductive plunger and active region contact in detected semiconductor structure
Can be bad, conversely, conductive plunger is functional with active region contact.
Compared with prior art, technical scheme of the present invention has the following advantages：1) test structure packet provided by the invention
It includes：At least two groups of conductive plungers, every group of two conductive plungers, one end of every group of conductive plunger is connected to together by metal silicide
The other end active area of one selection transistor；Every group of conductive plunger is obtained using 4-Wire Kelvin Test method (Kelvin Contact)
The resistance of conductive plunger and the contact structures with metal silicide and, there are two above-mentioned 4-Wire Kelvin Test method tools signal
Apply end, two test leads, i.e., for first group of conductive plunger, current signal I1 is passed through from the end input of a conductive plunger
Cross contact structures, the Semiconductor substrate of a segment length between the conductive plunger, the conductive plunger and Semiconductor substrate active area
It is flowed out after contact structures, another conductive plunger between active area, another conductive plunger and Semiconductor substrate active area, this
When, the voltage difference V1 of two conductive plunger ends of measurement, you can one conductive plunger of the group, the conductive plunger are obtained according to V1/I1
Corresponding contact structures, the Semiconductor substrate active area of a segment length, the corresponding contact structures of another conductive plunger, another conduction
The resistance and R1 of plug；For second group of conductive plunger：Current signal I2 is led from the end input of a conductive plunger by this
The Semiconductor substrate active area of contact structures, a segment length between electric plug, the conductive plunger and Semiconductor substrate active area,
It flows out after contact structures, another conductive plunger between another conductive plunger and Semiconductor substrate active area, is led at this point, measuring two
The voltage difference V2 of electric plug end, you can the corresponding contact of one conductive plunger of the group, the conductive plunger is obtained according to V2/I2 and is tied
Structure, the Semiconductor substrate active area of a segment length, the corresponding contact structures of another conductive plunger, another conductive plunger resistance and
R2；Since the resistance of the conductive plunger in each group is all equal, the resistance of contact structures is also all equal, each conductive plunger with it is each
The resistance of contact structures and it is denoted as RC, the resistivity of Semiconductor substrate active area unit cross-sectional area is ρ, and two is conductive in first group
The length of Semiconductor substrate active area is L1 between plug, in second group between two conductive plungers Semiconductor substrate active area length
It spends for L2.For first group of conductive plunger：V1/I1=2RC+ ρ * L1, for second group of conductive plunger：V2/I2=2RC+ ρ * L2；
The two simultaneous, you can obtain RC=(I1*L1*V2-I2*L2*V1)/[2 (L1-L2) * I1*I2].It can be seen that said program
In, in the active area length L1 and second group of conductive plunger in first group of conductive plunger between two conductive plungers two conductive plungers it
Between active area length L2 need it is unequal.Be utilized in said program 4-Wire Kelvin Test method to conductive plunger, contact structures,
Semiconductor substrate active area, another contact structures, the resistance of another conductive plunger and acquisition are more accurate, are joined by equation group
It is vertical, you can accurately obtain each conductive plunger and each contact structures resistance and.Since the conductive plunger of above-mentioned acquisition is with connecing
Touch and connected completely by metal silicide between structure, thus be conductive plunger with contact good contact structures resistance and,
If in detected semiconductor structure conductive plunger with and contact structures resistance and more than above-mentioned resistance and, illustrate detected
Semiconductor structure in had no between conductive plunger and Semiconductor substrate metal silicide or not be entirely metal silicide, i.e.,
The two contact performance is bad, conversely, the two contact performance is good.
2) in alternative, one end of first group of conductive plunger and one end of second group of conductive plunger are connected to same selection
The active area of transistor obtains each conductive plunger and the electricity of each contact structures by the active area of same selection transistor
Resistance and.
3) in alternative, for 2) alternative, a conductive plunger in first group of conductive plunger is led with second group
A conductive plunger in electric plug shares, i.e., is obtained by three conductive plungers of the active area for being located at same selection transistor
The resistance of each conductive plunger and each contact structures and.
4) in alternative, for 2) alternative or 3) alternative, in addition to simultaneous is connected to same selection transistor
Two groups of conductive plungers obtain each conductive plunger and each contact structures resistance and, can also by above-mentioned any one group conduction
Plug and the third group conductive plunger simultaneous for being connected to another selection transistor, obtain each conductive plunger with each contacting again
The resistance of structure and, above-mentioned two resistance and be averaged, you can reduce the error in test process.
5) in alternative, one end of first group of conductive plunger is connected to different selections from one end of second group of conductive plunger
The active area of transistor obtains each conductive plunger and the electricity of each contact structures by the active area of different selection transistors
It hinders and four conductive plungers is at least needed in this programme.
6) in alternative, selection transistor can be bit line selection transistor or source line transistor, i.e., with metallic silicon
The active area of compound is drain region or source region.
7) in alternative, the current signal size that two conductive plungers are applied in first group of conductive plunger is led with second group
The current signal that two conductive plungers are applied in electric plug differs in size, and reduces the error in test process.
Description of the drawings
Fig. 1 is the schematic diagram of the test structure of one embodiment of the invention；
Fig. 2 is the sectional view along the A-A straight lines in Fig. 1；
Fig. 3 is the sectional view of the test structure of another embodiment of the present invention；
Fig. 4 is the sectional view of the test structure of further embodiment of the present invention.
Specific embodiment
As described in the background art, prior art contact performance between conductive plunger and Semiconductor substrate active area judges
It is inaccurate.In order to solve the above technical problem, the present invention provides following test structures：At least two groups of conductive plungers, every group
Two conductive plungers, the other end that one end of every group of conductive plunger is connected to same selection transistor by metal silicide are active
Area；Every group of conductive plunger carries out test using 4-Wire Kelvin Test method (Kelvin Contact) and obtains an equation, simultaneous two
Equation, you can the accurate resistance for obtaining conductive plunger and the contact structures with metal silicide and.Due to leading for above-mentioned acquisition
It is connected completely by metal silicide between electric plug and contact structures, thus is conductive plunger with contacting good contact structures
Resistance and, if in detected semiconductor structure conductive plunger with and contact structures resistance and more than above-mentioned resistance and,
Illustrate to have no metal silicide or not completely golden in detected semiconductor structure between conductive plunger and Semiconductor substrate
Belong to silicide, i.e. the two contact performance is bad, conversely, the two contact performance is good.
It is understandable for the above objects, features and advantages of the present invention is enable to become apparent, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
Fig. 1 is the schematic diagram of test structure provided by one embodiment of the present invention.Fig. 2 is cuing open along the A-A straight lines in Fig. 1
View.
With reference to shown in Fig. 1 and Fig. 2, the test structure is formed over the semiconductor substrate 10, in the Semiconductor substrate 10
With NAND memory array 11, the unit of the NAND memory array 11 includes：It is formed using the double composition methods of autoregistration
NAND memory cell strings 111 and the selection transistor 112 for selecting the NAND memory cell strings 111；Wherein, it selects
One end active area of transistor 112 is connect with one end active area (not indicating) of the NAND memory cell strings 111, selects crystal
The other end active region region overlay of pipe 112 has metal silicide 101, wherein, the test structure includes：
First conductive plunger 12, the second conductive plunger 13 and third conductive plunger 14, the first conductive plunger 12 are led with second
Electric plug 13 is first group of conductive plunger, and the second conductive plunger 13 and third conductive plunger 14 are second group of conductive plunger, first
One end of conductive plunger 12, the second conductive plunger 13 and third conductive plunger 14 is connected to same choosing by metal silicide 101
Select the other end active area (not indicating) of transistor 112；
Signal applies weld pad 15 and detection welding pad 16, and the other end of each conductive plunger connects a signal and applies weld pad 15
With a detection welding pad 16.
Each NAND memory cell strings 111 can include multiple NAND storage units, be 2 in the present embodiment.In addition,
Since NAND memory cell strings 111 use the double composition methods of autoregistration to be formed, thus, the active area with NAND memory cell strings 111
The active area of the selection transistor 112 of connection extends in one direction, and referring for example to shown in Fig. 1, extends along vertical paper direction.
It should be noted that the active region region covered with metal silicide 101 is and each conductive plunger bottom
The region of alignment, the other regions of active area are without metal silicide 101.
In specific implementation process, 10 material of Semiconductor substrate can be silicon, germanium or silicon-on-insulator.Active area thereon
Can be N-type or p-type ion doped region.
During using being connected completely by metal silicide between above-mentioned test structure acquisition conductive plunger and Semiconductor substrate,
Between conductive plunger and conductive plunger and Semiconductor substrate the resistance of contact structures and principle be：
For first group of conductive plunger：Apply in two signals and apply current signal I1 on weld pads 15, current signal I1 from
The end input of first conductive plunger 12, has by first conductive plunger 12, first conductive plunger 12 with Semiconductor substrate
The Semiconductor substrate active area of contact structures (not indicating), L1 length between source region, the second conductive plunger 13 are served as a contrast with semiconductor
It is flowed out after contact structures (not indicating), the second conductive plunger 13 between the active area of bottom, at this point, being measured by two detection welding pads 16
Two conductive plungers 12, the voltage difference V1 of 13 ends, you can the first conductive plunger 12, the first conductive plunger 12 are obtained according to V1/I1
The Semiconductor substrate active area of contact structures, L1 length between Semiconductor substrate active area, the second conductive plunger 13 and half
The resistance and R1 of contact structures, the second conductive plunger 13 between conductor substrate active area.
For second group of conductive plunger：Apply in two signals and apply current signal I2 on weld pads 15, current signal I2 from
The end input of second conductive plunger 13, has by second conductive plunger 13, second conductive plunger 13 with Semiconductor substrate
Semiconductor substrate active area, the third conductive plunger 14 of contact structures (not indicating), L2 length between source region are served as a contrast with semiconductor
It is flowed out after contact structures (not indicating), third conductive plunger 14 between the active area of bottom, at this point, being measured by two detection welding pads 16
Two conductive plungers 13, the voltage difference V2 of 14 ends, you can the second conductive plunger 13, the second conductive plunger 13 are obtained according to V2/I2
Semiconductor substrate active area, the third conductive plunger 14 and half of contact structures, L2 length between Semiconductor substrate active area
The resistance and R2 of contact structures, third conductive plunger 14 between conductor substrate active area.
It is understood that in every group of conductive plunger, current direction when current signal applies does not influence the group conduction and inserts
Fill in the voltage difference of two ends.
Since the resistance of conductive plunger in each group is all equal, the resistance of contact structures is also all equal, each conductive plunger with
The resistance of each contact structures and RC is denoted as, the resistivity of Semiconductor substrate active area unit cross-sectional area is ρ, two in first group
The length of Semiconductor substrate active area is L1 between conductive plunger 12,13, semiconductor between two conductive plungers 13,14 in second group
The length of substrate active area is L2.For first group of conductive plunger：V1/I1=2RC+ ρ * L1, for second group of conductive plunger：
V2/I2=2RC+ ρ * L2；The two simultaneous, you can obtain RC=(I1*L1*V2-I2*L2*V1)/[2 (L1-L2) * I1*I2].It can
To find out, in said program, the active area length L1 in first group of conductive plunger between two conductive plungers 12,13 is led with second group
Active area length L2 in electric plug between two conductive plungers 13,14 needs unequal.
In said program, two groups of conductive plungers are different in addition to active area length L1, L2 between every group of conductive plunger, applied
Current signal I1, I2 size added may be different, remaining structure all same, thus can be obtained by equation group simultaneous and each led
The resistance and RC of electric plug and each contact structures；In addition, for every group of conductive plunger, 4-Wire Kelvin Test method pair is utilized
Conductive plunger, contact structures, Semiconductor substrate active area, another contact structures, the resistance of another conductive plunger and acquisition are more
Accurately.Thus, the resistance and RC of each conductive plunger and each contact structures can accurately be obtained.
In order to further improve the accuracy that resistance and RC are obtained, during the test, two lead in first group of conductive plunger
The current signal I1 sizes that electric plug 12,13 is applied and the electricity that two conductive plungers 13,14 are applied in second group of conductive plunger
Stream signal I2 differs in size, and can so reduce the error in test process.
It is understood that in above-mentioned simultaneous equations, Semiconductor substrate active area unit cross-sectional area can also be obtained
Electricalresistivityρ=(V1*I2-V2*I1)/[I1*I2* (L1-L2)].
Based on above-mentioned test structure, the present embodiment also proposed the detection side of a kind of conductive plunger and active region contact performance
Method obtains passing through metallic silicon between conductive plunger and active area completely using the semi-conductor test structure described in above-mentioned any one
Compound connect when, the resistance of the conductive plunger and contact structures and, and with conductive plunger in detected semiconductor structure with
And contact structures resistance and compare, if the latter is more than the former, conductive plunger and active area in detected semiconductor structure
Contact performance is bad, conversely, conductive plunger is functional with active region contact.
This is because：Pass through metal silication completely between the conductive plunger and contact structures that are obtained due to above-mentioned test structure
Object 101 connects, thus be conductive plunger with contact good contact structures resistance and, if being led in detected semiconductor structure
Electric plug with and contact structures resistance and more than above-mentioned resistance and, then illustrate in detected semiconductor structure conductive plunger and
It is entirely metal silicide that metal silicide is had no between Semiconductor substrate or is not, i.e. the two contact performance is bad, conversely, two
Person's contact performance is good.
It should be noted that above-mentioned detected semiconductor structure in addition to conductive plunger and Semiconductor substrate active area it
Between be without metal silicide or not fully metal silicide, other structures all same.
In specific implementation process, can also set conductive plunger in detected semiconductor structure with and contact structures
Resistance and during more than being connected completely by metal silicide between conductive plunger and active area, the conductive plunger and contact structures
Resistance and certain value, judge that conductive plunger contact performance is bad in detected semiconductor structure, above-mentioned certain value is, for example,
When being connected completely by metal silicide between conductive plunger and active area, the resistance sum of the conductive plunger and contact structures
10%.
Fig. 3 is the sectional view for the test structure that another embodiment of the present invention provides.As can be seen that with the test in Fig. 2
Difference lies in test structure further includes structure：
4th conductive plunger 17, wherein, the first conductive plunger 12 and the second conductive plunger 13 are first group of conductive plunger, the
Three conductive plungers 14 and the 4th conductive plunger 17 are second group of conductive plunger, the 4th conductive plunger 17, the first conductive plunger 12, the
One end of two conductive plungers 13 and third conductive plunger 14 is connected to same selection transistor by the metal silicide 101
112 other end active area (not indicating)；The other end of 4th conductive plunger 17 also connects a signal and applies weld pad 15 and one
A detection welding pad 16.
In the present embodiment, with reference to shown in Fig. 3, for first group of conductive plunger：Apply in two signals and apply on weld pad 15
Current signal I1, current signal I1 are inputted from the end of the first conductive plunger 12, and by first conductive plunger 12, this first leads
The Semiconductor substrate active area of contact structures (not indicating), L1 length between electric plug 12 and Semiconductor substrate active area,
It is flowed out after contact structures (not indicating), the second conductive plunger 13 between two conductive plungers 13 and Semiconductor substrate active area, this
When, pass through two detection welding pads 16 measurement, two conductive plungers 12, the voltage difference V1 of 13 ends, you can obtain first according to V1/I1 and lead
Contact structures, the Semiconductor substrate of L1 length between electric plug 12, the first conductive plunger 12 and Semiconductor substrate active area have
The resistance and R1 of contact structures, the second conductive plunger 13 between source region, the second conductive plunger 13 and Semiconductor substrate active area.
For second group of conductive plunger：Apply in two signals and apply current signal I3 on weld pads 15, current signal I3 from
The end input of 4th conductive plunger 17, has by the 4th conductive plunger 17, the 4th conductive plunger 17 with Semiconductor substrate
Semiconductor substrate active area, the third conductive plunger 14 of contact structures (not indicating), L3 length between source region are served as a contrast with semiconductor
It is flowed out after contact structures (not indicating), third conductive plunger 14 between the active area of bottom, at this point, being measured by two detection welding pads 16
Two conductive plungers 14, the voltage difference V3 of 17 ends, you can the 4th conductive plunger 17, the 4th conductive plunger 17 are obtained according to V3/I3
Semiconductor substrate active area, the third conductive plunger 14 and half of contact structures, L3 length between Semiconductor substrate active area
The resistance and R3 of contact structures, third conductive plunger 14 between conductor substrate active area.
Since the resistance of conductive plunger in each group is all equal, the resistance of contact structures is also all equal, each conductive plunger with
The resistance of each contact structures and RC is denoted as, the resistivity of Semiconductor substrate active area unit cross-sectional area is ρ, two in first group
The length of Semiconductor substrate active area is L1 between conductive plunger, Semiconductor substrate active area between two conductive plungers in second group
Length be L3.For first group of conductive plunger：V1/I1=2RC+ ρ * L1, for second group of conductive plunger：V3/I3=2RC+
ρ*L3；The two simultaneous, you can obtain RC=(I1*L1*V3-I3*L3*V1)/[2 (L1-L3) * I1*I3].As can be seen that above-mentioned
In scheme, two in the active area length L1 and second group of conductive plunger in first group of conductive plunger between two conductive plungers 12,13
Active area length L3 between conductive plunger 14,15 needs unequal.
In said program, it is active to conductive plunger, contact structures, Semiconductor substrate that 4-Wire Kelvin Test method is utilized
Area, another contact structures, the resistance of another conductive plunger and acquisition are more accurate, pass through equation group simultaneous, you can accurate to obtain
Each conductive plunger and the resistance and RC of each contact structures.
It is understood that the test structure based on the present embodiment, can be used for conductive plunger and active region contact
The detection of energy, specific detection method is with reference to the detection method in a upper embodiment, and details are not described herein.
Fig. 4 is the sectional view for the test structure that further embodiment of the present invention provides.As can be seen that with the test in Fig. 3
Difference lies in the first conductive plunger 12 of first group of conductive plunger and one end of the second conductive plunger 13 pass through metal to structure respectively
Silicide 101 is connected to the other end active area (not indicating) of a selection transistor 112；The third of second group of conductive plunger is conductive
Plug 14 and one end of the 4th conductive plunger 17 are connected to the another of another selection transistor 112 ' by metal silicide 101 respectively
One end active area (does not indicate).
In the present embodiment, although two groups of conductive plungers are connected to the active area of different selection transistors, however, two groups
In addition to the active area length between every group of conductive plunger is different in conductive plunger, the current signal size applied may be different,
Remaining structure all same, thus can be obtained by equation group simultaneous each conductive plunger and each contact structures resistance and；
In addition, for every group of conductive plunger, 4-Wire Kelvin Test method, which is utilized, conductive plunger, contact structures, Semiconductor substrate
Source region, another contact structures, the resistance of another conductive plunger and acquisition are more accurate.Thus, it can accurately obtain each conductive slotting
Plug and the resistance of each contact structures and.
It is understood that for the test structure in Fig. 4, it can also be conductive in the first conductive plunger of connection 12, second
Another conductive plunger (not shown) is set on the selection transistor of plug 13, with the first conductive plunger 12, the second conductive plunger
Any one in 13 forms third group conductive plunger, in this way, can also (or second group of conduction is inserted by first group of conductive plunger
Plug) with third group conductive plunger simultaneous, obtain again each conductive plunger and each contact structures resistance and, above-mentioned two is electric
It hinders and is averaged, you can reduce the error in test process.It similarly, can also be for the test structure in Fig. 2 or Fig. 3
Another group of conductive plunger on another selection transistor is set, is obtained by multiple two groups of conductive plungers of simultaneous multiple each conductive slotting
It fills in and the resistance of each contact structures and and is averaged.
Above-mentioned conductive plunger is not limited to three groups, can be more multigroup, and every group of conductive plunger is not limited to be located at one or two choosing
It selects on transistor, it can more selection transistors.
The test structure of the present embodiment can be used for the detection of conductive plunger and active region contact performance, specific detection side
Method is with reference to the detection method in a upper embodiment, and details are not described herein.
Although present disclosure is as above, present invention is not limited to this.Any those skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (10)
1. a kind of semi-conductor test structure, the test structure is formed on a semiconductor substrate, is had in the Semiconductor substrate
NAND memory array, the unit of the NAND memory array include：The NAND formed using the double composition methods of autoregistration is stored
Unit string and the selection transistor for selecting the NAND memory cell strings；Wherein, one end of the selection transistor has
Source region is connect with one end active area of the NAND memory cell strings, which is characterized in that the test structure includes：
At least two groups of conductive plungers, every group of two conductive plungers, one end of each conductive plunger is connected by metal silicide in every group
Be connected to the other end active area of same selection transistor, the active area length in first group of conductive plunger between two conductive plungers with
Active area length in second group of conductive plunger between two conductive plungers is unequal；
Signal applies weld pad and detection welding pad, and the other end of each conductive plunger connects a signal and applies weld pad and a test
Weld pad.
2. semi-conductor test structure according to claim 1, which is characterized in that one end of first group of conductive plunger and second
One end of group conductive plunger is connected to the active area of same selection transistor.
3. semi-conductor test structure according to claim 2 a, which is characterized in that conduction in first group of conductive plunger
Plug is shared with a conductive plunger in second group of conductive plunger.
4. the semi-conductor test structure according to Claims 2 or 3, which is characterized in that further include third group conductive plunger, institute
The one end for stating third group conductive plunger is connected to the other end active area of another selection transistor by the metal silicide, the
It is active between two conductive plungers in active area length, first group of conductive plunger in three groups of conductive plungers between two conductive plungers
Active area length in section length and second group of conductive plunger between two conductive plungers is unequal.
5. semi-conductor test structure according to claim 1, which is characterized in that one end of first group of conductive plunger and second
One end of group conductive plunger is connected to the active area of different selection transistors.
6. semi-conductor test structure according to claim 1, which is characterized in that the selection transistor is brilliant for bit line selection
Body pipe, the active area with metal silicide are drain region.
7. semi-conductor test structure according to claim 1, which is characterized in that the selection transistor is brilliant for source line options
Body pipe, the active area with metal silicide are source region.
8. semi-conductor test structure according to claim 1, which is characterized in that two conductive plungers in first group of conductive plunger
The current signal size applied differs in size with the current signal that two conductive plungers are applied in second group of conductive plunger.
9. semi-conductor test structure according to claim 1, which is characterized in that the Semiconductor substrate is silicon, germanium or exhausted
Silicon on edge body.
10. a kind of conductive plunger and the detection method of active region contact performance, which is characterized in that appoint using in claim 1 to 9
When semi-conductor test structure described in one obtains connecting by metal silicide completely between conductive plunger and active area, each
The resistance of the conductive plunger and corresponding contact structures and, and with conductive plunger in detected semiconductor structure with and contact knot
The resistance of structure and compare, if the latter is more than the former, conductive plunger and active region contact performance in detected semiconductor structure
It is bad, conversely, conductive plunger is functional with active region contact.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5914512A (en) * | 1997-01-22 | 1999-06-22 | Taiwan Semicondutor Manufacturing Company, Ltd. | External contact to a MOSFET drain for testing of stacked-capacitor DRAMS |
| CN103107163A (en) * | 2011-11-11 | 2013-05-15 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor test structure and forming method and testing method thereof |
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| KR100399976B1 (en) * | 2001-11-23 | 2003-09-29 | 주식회사 하이닉스반도체 | Test pattern for measuring contact resistance and method of manufacturing the same |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5914512A (en) * | 1997-01-22 | 1999-06-22 | Taiwan Semicondutor Manufacturing Company, Ltd. | External contact to a MOSFET drain for testing of stacked-capacitor DRAMS |
| CN103107163A (en) * | 2011-11-11 | 2013-05-15 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor test structure and forming method and testing method thereof |
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