CN116344580A - 具有屏蔽背栅效应的高侧及低侧gan fet的单片集成 - Google Patents

具有屏蔽背栅效应的高侧及低侧gan fet的单片集成 Download PDF

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Publication number
CN116344580A
CN116344580A CN202211631318.0A CN202211631318A CN116344580A CN 116344580 A CN116344580 A CN 116344580A CN 202211631318 A CN202211631318 A CN 202211631318A CN 116344580 A CN116344580 A CN 116344580A
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China
Prior art keywords
gallium nitride
aluminum
nitride layer
gate
layer
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Pending
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CN202211631318.0A
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English (en)
Chinese (zh)
Inventor
李东燮
Q·法里德
S·赛特拉曼
J·乔
C·S·徐
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Texas Instruments Inc
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Texas Instruments Inc
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Publication of CN116344580A publication Critical patent/CN116344580A/zh
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/40FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H10D30/473High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having confinement of carriers by multiple heterojunctions, e.g. quantum well HEMT
    • H10D30/4732High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having confinement of carriers by multiple heterojunctions, e.g. quantum well HEMT using Group III-V semiconductor material
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149Source or drain regions of field-effect devices
    • H10D62/151Source or drain regions of field-effect devices of IGFETs 
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/015Manufacture or treatment of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113Isolations within a component, i.e. internal isolations
    • H10D62/115Dielectric isolations, e.g. air gaps
    • H10D62/116Dielectric isolations, e.g. air gaps adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/85Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
    • H10D62/8503Nitride Group III-V materials, e.g. AlN or GaN
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/0123Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/02Manufacture or treatment characterised by using material-based technologies
    • H10D84/05Manufacture or treatment characterised by using material-based technologies using Group III-V technology
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/343Gate regions of field-effect devices having PN junction gates

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  • Junction Field-Effect Transistors (AREA)
CN202211631318.0A 2021-12-22 2022-12-19 具有屏蔽背栅效应的高侧及低侧gan fet的单片集成 Pending CN116344580A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US17/559,635 2021-12-22
US17/559,635 US11888027B2 (en) 2021-12-22 2021-12-22 Monolithic integration of high and low-side GaN FETs with screening back gating effect

Publications (1)

Publication Number Publication Date
CN116344580A true CN116344580A (zh) 2023-06-27

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CN202211631318.0A Pending CN116344580A (zh) 2021-12-22 2022-12-19 具有屏蔽背栅效应的高侧及低侧gan fet的单片集成

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Country Link
US (2) US11888027B2 (https=)
EP (1) EP4203034A1 (https=)
JP (1) JP2023093410A (https=)
CN (1) CN116344580A (https=)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6500879B2 (ja) * 2016-08-30 2019-04-17 株式会社三洋物産 遊技機
JP7235153B2 (ja) * 2017-12-29 2023-03-08 株式会社三洋物産 遊技機
JP7235154B2 (ja) * 2018-02-15 2023-03-08 株式会社三洋物産 遊技機
JP7231076B2 (ja) * 2018-03-08 2023-03-01 株式会社三洋物産 遊技機
JP2020130466A (ja) * 2019-02-15 2020-08-31 株式会社三洋物産 遊技機
JP7234741B2 (ja) * 2019-03-28 2023-03-08 株式会社三洋物産 遊技機
JP7234740B2 (ja) * 2019-03-28 2023-03-08 株式会社三洋物産 遊技機
JP7234760B2 (ja) * 2019-04-11 2023-03-08 株式会社三洋物産 遊技機
JP7234761B2 (ja) * 2019-04-11 2023-03-08 株式会社三洋物産 遊技機
JP2023063369A (ja) * 2022-01-07 2023-05-09 株式会社三洋物産 遊技機
JP2023053387A (ja) * 2022-02-04 2023-04-12 株式会社三洋物産 遊技機
JP2023060270A (ja) * 2022-04-01 2023-04-27 株式会社三洋物産 遊技機
JP2023060269A (ja) * 2022-04-01 2023-04-27 株式会社三洋物産 遊技機

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JP5669119B1 (ja) 2014-04-18 2015-02-12 株式会社パウデック 半導体素子、電気機器、双方向電界効果トランジスタおよび実装構造体
JP2019505459A (ja) * 2015-12-10 2019-02-28 アイキューイー ピーエルシーIQE plc 増加した圧縮応力によってシリコン基板上で成長させたiii族窒化物構造物
US11049960B2 (en) 2019-03-06 2021-06-29 Texas Instruments Incorporated Gallium nitride (GaN) based transistor with multiple p-GaN blocks
US11211481B2 (en) 2020-01-13 2021-12-28 Cambridge Gan Devices Limited III-V semiconductor device
EP3905523B1 (en) 2020-04-30 2024-06-19 Infineon Technologies Austria AG Switching circuit, gate driver and method of operating a transistor device
US11362190B2 (en) * 2020-05-22 2022-06-14 Raytheon Company Depletion mode high electron mobility field effect transistor (HEMT) semiconductor device having beryllium doped Schottky contact layers

Also Published As

Publication number Publication date
EP4203034A1 (en) 2023-06-28
JP2023093410A (ja) 2023-07-04
US20240120383A1 (en) 2024-04-11
US20230197784A1 (en) 2023-06-22
US11888027B2 (en) 2024-01-30
US12520547B2 (en) 2026-01-06

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