CN116314153A - Mounting apparatus for semiconductor circuit and method of manufacturing semiconductor circuit - Google Patents

Mounting apparatus for semiconductor circuit and method of manufacturing semiconductor circuit Download PDF

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Publication number
CN116314153A
CN116314153A CN202111572353.5A CN202111572353A CN116314153A CN 116314153 A CN116314153 A CN 116314153A CN 202111572353 A CN202111572353 A CN 202111572353A CN 116314153 A CN116314153 A CN 116314153A
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China
Prior art keywords
mounting
semiconductor circuit
chip
circuit
finished product
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CN202111572353.5A
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Chinese (zh)
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冯宇翔
黄浩
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Guangdong Huizhi Precision Manufacturing Co ltd
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Guangdong Huizhi Precision Manufacturing Co ltd
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Priority to CN202111572353.5A priority Critical patent/CN116314153A/en
Publication of CN116314153A publication Critical patent/CN116314153A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4825—Connection or disconnection of other leads to or from flat leads, e.g. wires, bumps, other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4871—Bases, plates or heatsinks
    • H01L21/4882—Assembly of heatsink parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3672—Foil-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Die Bonding (AREA)

Abstract

The invention discloses a mounting device for a semiconductor circuit and a manufacturing method of the semiconductor circuit. The invention provides novel integrated mounting equipment for a semiconductor circuit, and the surface mounting of an electronic element of the semiconductor circuit can be realized through one mounting equipment. Therefore, compared with the existing surface mounting equipment which can be completed by a plurality of devices, the invention can reduce the transportation stroke of the semiconductor circuit products on the production line and improve the production efficiency; meanwhile, the problem that the production efficiency of equipment is affected due to the mismatching of UPH caused by different production procedures due to the fact that the quantity of materials used by the semiconductor circuit is different can be avoided.

Description

Mounting apparatus for semiconductor circuit and method of manufacturing semiconductor circuit
Technical Field
The invention relates to a mounting device for a semiconductor circuit and a manufacturing method of the semiconductor circuit, belonging to the technical field of application of the semiconductor circuit.
Background
The semiconductor circuit, i.e. the modularized intelligent power system MIPS (Module Intelligent Power System), not only integrates the power switch device and the driving circuit, but also is internally provided with fault detection circuits such as overvoltage, overcurrent, overheat and the like, and can send detection signals to the CPU or the DSP for interrupt processing. Semiconductor circuits are a type of power driven product that combine power electronics and integrated circuit technology. The traditional intelligent power module generally adopts a high-voltage driving chip to drive the IGBT, generally has six-path three-phase full-bridge driving, and is widely applied to the fields of industrial control, household appliances and the like. Most of these applications are subjected to harsh environmental conditions, such as high temperature, humidity, high pressure, etc. Since these devices are often used in exposed applications, the quality and reliability of the semiconductor circuit is critical.
In the mounting technology of electronic components, there are certain differences in mounting tools due to the variety of electronic components, and there is still a problem of low mounting efficiency, which needs to be solved urgently.
Disclosure of Invention
The invention aims to solve the technical problem of improving the mounting efficiency of electronic elements of the traditional semiconductor circuit.
Specifically, the invention discloses a mounting device for a semiconductor circuit, which is characterized in that the mounting device comprises a multifunctional joint, an automatic die bonding area and a surface mounting area are integrated in the mounting device, the mounting device can complete the mounting procedures of the automatic die bonding area and the surface mounting area through the multifunctional joint,
the automatic die bonding area comprises an HVIC bonding station, an IGBT bonding station and an FRD bonding station; the surface mounting area comprises a large radiating fin semi-finished product mounting station, a small radiating fin semi-finished product mounting station, a chip resistor mounting station and a chip capacitor mounting station.
Optionally, the multifunctional joint is a rotary integrated suction head.
Optionally, the multifunctional connector comprises a passive component rotating suction head for mounting the chip resistor and the chip capacitor, a radiating fin semi-finished product suction head for mounting the large radiating fin semi-finished product and the small radiating fin semi-finished product, an HVIC chip suction head for sucking an HVIC, an IGBT chip suction head for sucking an IGBT, and an FRD chip suction head for sucking an FRD.
Optionally, the HVIC paste number is 1, the IGBT paste number is 6, the FRD paste number is 6, the mounting number of the large heat sink semi-finished product is 1, the mounting number of the small heat sink semi-finished product is 1, and the mounting numbers of the chip resistor and the chip capacitor are both greater than 10.
Optionally, the chip resistor and the chip capacitor are reel materials, the HVIC, the IGBT and the FRD are all wafer materials, and the large heat sink semi-finished product and the small heat sink semi-finished product each include an auxiliary heat sink and a power chip.
Optionally, the mounting apparatus further comprises a transporting rail capable of carrying and transporting the circuit substrate of the semiconductor circuit, and the multifunctional joint is provided to one side of the rail.
In addition, the invention also provides a manufacturing method of the semiconductor circuit, which comprises the following steps:
step S100, providing a circuit substrate;
step 200, sequentially preparing an insulating layer and a circuit wiring layer on the mounting surface of the circuit substrate;
step S300, preparing pins, wherein one ends of a plurality of pins are connected with each other through connecting ribs;
step S400, configuring electronic elements and pins on the circuit wiring layer, wherein preset mounting positions for configuring the electronic elements are reserved on the circuit wiring layer, and solder paste or silver-dispensing glue is arranged on the preset mounting positions;
wherein the electronic component is mounted on the preset mounting position by using the mounting apparatus for semiconductor circuits described above; placing the pins at the corresponding preset mounting positions by a manipulator or manually, and then placing the whole semi-finished product into a reflow oven to solder the electronic element and the pins on the circuit substrate;
step S500, electrically connecting the electronic element and the circuit wiring layer through bonding wires;
step S600, injection molding is carried out on the circuit substrate provided with the electronic element and the pin through a packaging mould to form a sealing layer, wherein the sealing layer covers a mounting surface of the circuit substrate for mounting the electronic element;
and S700, cutting off the connecting ribs among the pins to form a semiconductor circuit to be tested, carrying out parameter test on the semiconductor circuit to be tested through test equipment, and if the test is qualified, bending and forming each pin of the semiconductor circuit to be tested, which is qualified, based on a preset pin shape to obtain the qualified semiconductor circuit.
Optionally, in step S400, the mounting apparatus sucks the HVIC, IGBT, FRD, the large heat sink semi-finished product, the small heat sink semi-finished product, the chip resistor and the chip capacitor onto the corresponding preset mounting positions on the circuit substrate one by one through the multifunctional connector of the mounting apparatus.
Alternatively, the HVIC, IGBT and FRD are all placed on a blue film or UV film after dicing through a bare chip.
Optionally, before step S400, an auxiliary heat sink and a functional chip are provided, and the functional chip is mounted on the auxiliary heat sink to complete the preliminary provision of the large heat sink semi-finished product and the small heat sink semi-finished product.
The embodiment of the invention provides novel mounting equipment for a semiconductor circuit, which comprises a multifunctional connector, wherein an automatic die bonding area and a surface mounting area are integrated in the mounting equipment, and the mounting equipment can complete the mounting procedures of the automatic die bonding area and the surface mounting area through the multifunctional connector. The automatic die bonding area comprises an HVIC bonding station, an IGBT bonding station and an FRD bonding station; the surface mounting area comprises a large radiating fin semi-finished product mounting station, a small radiating fin semi-finished product mounting station, a patch resistor mounting station and a patch capacitor mounting station. The invention provides novel integrated mounting equipment for a semiconductor circuit, which can mount surface components such as a bare chip, an auxiliary radiating fin semi-finished product, a passive component and the like, and can realize the surface mounting of an electronic element of the semiconductor circuit through one mounting equipment. Therefore, compared with the existing surface mounting equipment which can be completed by a plurality of equipment, the surface mounting equipment can save at least three surface mounting equipment, is beneficial to saving the production cost, can better improve the mounting precision, can reduce the transportation stroke of semiconductor circuit products on a production line and improves the production efficiency; meanwhile, the problem that the production efficiency of equipment is affected due to the mismatching of UPH caused by different production procedures due to the fact that the quantity of materials used by the semiconductor circuit is different can be avoided.
Drawings
Fig. 1 is a schematic view of a mounting apparatus for a semiconductor circuit according to an embodiment of the present invention in its operating environment;
fig. 2 shows a schematic structure of a mounting apparatus for a semiconductor circuit of an embodiment of the present invention for mounting components onto a circuit substrate;
FIG. 3 illustrates a process step in the manufacture of a semiconductor circuit, primarily showing schematic diagrams from the completion of mounting to the completion of the finished semiconductor circuit;
fig. 4 shows a schematic cross-sectional structure of a semiconductor circuit;
fig. 5 is a flowchart of a method of manufacturing a semiconductor circuit according to an embodiment of the present invention.
Reference numerals:
the multifunctional connector 1, a circuit substrate 2, a wafer 3, a semi-finished carrier 4, a reel 5, HVIC6, IGBT7, FRD8, a small heat sink semi-finished product 9, a large heat sink semi-finished product 10, a chip resistor 11, a chip capacitor 12, pins 13, a sealing layer 14, a fixing position 15, a passive component rotating suction head 101, a heat sink semi-finished product suction head 102, an HVIC chip suction head 103, an IGBT chip suction head 104, an FRD chip suction head 105, an insulating layer 30000 and a circuit wiring layer 400.
Detailed Description
In addition, in the case where the structure or the function is not conflicting, the embodiments of the present invention and the features in the embodiments may be combined with each other. The invention is described in detail below with reference to examples.
The invention provides a semiconductor circuit, which is a circuit module integrating a power switch device, a high-voltage driving circuit and the like and sealing and packaging the surfaces of the power switch device and the high-voltage driving circuit. The method is widely applied in the field of power electronics, such as the fields of frequency converters of driving motors, various inverter voltages, variable frequency speed regulation, metallurgical machinery, electric traction, variable frequency household appliances and the like. The semiconductor circuits herein have a variety of other names such as modular smart power systems (Modular Intelligent Power System, MIPS), smart power modules (Intelligent Power Module, IPM), or names known as hybrid integrated circuits, power semiconductor modules, power modules, etc.
In the existing manufacturing process of semiconductor circuits and the chip mounting production process of electronic components, automatic die bonding equipment is needed for chip mounting, and since bare chips are placed on blue films or UV films after dicing, the blue films or the UV films have certain adhesiveness to the chips, the chips cannot be normally sucked by common SMT equipment, and the chips on the blue films or the UV films can be sucked only by special automatic die bonding equipment. Because of the pipelining operation of the mounting process, in the existing mounting process, 3 automatic die bonding devices such as the chips HVIC, IGBT and FRD are required to be respectively mounted on corresponding preset mounting positions (also called substrate positions) of the circuit substrate, and then the mounting of other passive elements and the like is performed through the SMT device after all the chips are mounted. Thus, at least 4 mounting apparatuses are required to complete the mounting of the internal components of the existing semiconductor circuit. Because the number of HVICs 6, IGBTs and FRDs in one semiconductor circuit product is different, the UPH (unit hour production value of each device) of 3 automatic die bonder devices is unbalanced, and the device for mounting a small number of chips is always in a waiting state, and the mounting is performed after other chips are required to be mounted. In view of the above, the conventional electronic component chip mounting process UPH is not high, and improvements are still needed.
The embodiment of the invention provides novel mounting equipment for a semiconductor circuit, which comprises a multifunctional connector 1, wherein an automatic die bonding area and a surface mounting area are integrated in the mounting equipment, and the mounting equipment can complete the mounting procedures of the automatic die bonding area and the surface mounting area through the multifunctional connector 1. The automatic die bonding area comprises an HVIC bonding station, an IGBT bonding station and an FRD bonding station; the surface mounting area comprises a large radiating fin semi-finished product mounting station, a small radiating fin semi-finished product mounting station, a patch resistor 11 mounting station and a patch capacitor 12 mounting station.
The invention provides novel integrated mounting equipment for a semiconductor circuit, which can mount surface components such as a bare chip, an auxiliary radiating fin semi-finished product, a passive component and the like, and can realize the surface mounting of an electronic element of the semiconductor circuit through one mounting equipment. Therefore, compared with the existing surface mounting equipment which can be completed by a plurality of equipment, the surface mounting equipment can save at least three surface mounting equipment, is beneficial to saving the production cost, can better improve the mounting precision, can reduce the transportation stroke of semiconductor circuit products on a production line and improves the production efficiency; meanwhile, the problem that the production efficiency of equipment is affected due to the mismatching of UPH caused by different production procedures due to the fact that the quantity of materials used by the semiconductor circuit is different can be avoided.
Referring to fig. 1 and 2, fig. 1 is a schematic view of a mounting apparatus for a semiconductor circuit according to an embodiment of the present invention in its operating environment, and fig. 2 is a schematic view showing a structure of a mounting apparatus for a semiconductor circuit according to an embodiment of the present invention for mounting components on a circuit substrate. In some embodiments of the invention, the multifunctional adapter 1 may employ a rotary integrated tip. The multifunctional joint 1 includes a passive component rotation suction head 101 for mounting a chip resistor 11 and a chip capacitor 12, a fin half-product suction head 102 for mounting a large fin half-product 10 and a small fin half-product 9, an HVIC chip suction head 103 for sucking an HVIC6, an IGBT chip suction head 104 for sucking an IGBT7, and an FRD chip suction head 105 for sucking an FRD8, each suction head being switched by rotation. The passive component rotary suction head 101 has a plurality of types of specifications and types of passive components (the passive components generally refer to standard packages such as a chip resistor 11 and a chip capacitor 12) and have no special requirements, so that the passive component suction head can be designed into a rotary type, a plurality of suction nozzles are designed at the edge of the rotary suction head, and the rotary suction head can automatically select the corresponding suction nozzles to suck the corresponding passive components according to different specifications of products, thereby greatly improving the production efficiency. The fin semi-finished product suction head 102 can be designed into a plurality of fin semi-finished product suction heads 102 according to the different specifications and sizes or the number of the auxiliary fins, so that the suction is convenient and the efficiency is improved. For chip feeding, as the chip is fed by Wafer, and different chips are provided with independent Wafer 3 feeding mechanisms, the chip suction adopts the design of independent suction heads for improving the production efficiency and suction precision.
In some embodiments of the semiconductor circuit of the present invention, the chip resistor 11 and the chip capacitor 12 are reel materials and are disposed in the reel 5, the HVIC6, the IGBT7 and the FRD8 are wafer materials, and the large heat sink semi-finished product 10 and the small heat sink semi-finished product 9 each include auxiliary heat sinks and power chips, so that the feeding manners of the different chip materials are different, and the corresponding mounting processes and manners are different. The number of HVIC6 is 1, the number of IGBT7 is 6, the number of FRD8 is 6, the number of large heat-radiating fin semi-finished product 10 is 1, the number of small heat-radiating fin semi-finished product 9 is 1, and the number of chip resistor 11 and chip capacitor 12 is greater than 10. As can be seen, because the types of electronic components in the semiconductor circuit are various, and the number of each electronic component is different, in the existing pasting procedure, the chip HVIC6, the chip IGBT7 and the chip FRD8 are pasted to the corresponding substrate positions through 3 pieces of automatic die bonding equipment, and because only 1 HVIC6 is needed in one product, but 6 IGBTs 7 and 6 FRDs 8 are needed, 3 pieces of automatic die bonding equipment UPH are unbalanced, the equipment for pasting the HVIC6 chip is always waiting, and the pasting is carried out after 6 IGBTs 7 or 6 FRDs 8 are pasted; after all chips are mounted, the SMT equipment is used for mounting the semi-finished product of the radiating fin and the passive components, so that some mounting equipment always waits, and the UPH value of each equipment of the whole production line is not high. The mounting equipment solves the problem, and is independently completed by one integrated equipment, so that the waiting time waste is avoided for the single mounting equipment, and the production efficiency is greatly improved.
For surface mounting of electronic components of semiconductor circuits, in some embodiments, the mounting apparatus further comprises a transportation rail a capable of carrying and transporting the circuit substrate 2 of the semiconductor circuit, the multifunctional joint 1 being provided to the side of the rail a. The multifunctional connector 1 of the integrated suction head can effectively shorten the conveying distance of materials, is beneficial to shortening the conveying time length and improving the production efficiency.
In addition, the invention also provides a manufacturing method of the semiconductor circuit, referring to fig. 5, fig. 5 is a flowchart of the manufacturing method of the semiconductor circuit according to the embodiment of the invention, and the manufacturing method comprises the following steps:
step S100, providing a circuit substrate 2;
step S200, sequentially preparing an insulating layer 30000 and a circuit wiring layer 400 on the mounting surface of the circuit board 2;
step S300, preparing pins 13, wherein one ends of a plurality of pins 13 are connected with each other through connecting ribs;
step S400, configuring electronic elements and pins 13 on a circuit wiring layer 400, wherein preset mounting positions for configuring the electronic elements are reserved on the circuit wiring layer 400, and solder paste or silver paste is arranged on the preset mounting positions;
wherein, the electronic component is mounted on the preset mounting position by adopting the mounting equipment for the semiconductor circuit, the corresponding preset mounting position is placed on the pins 13 by a manipulator or manually, and then the whole semi-finished product is placed into a reflow oven to weld the electronic component and the pins 13 on the circuit substrate 2;
step S500, the electronic element and the circuit wiring layer 400 are electrically connected through bonding wires;
step S600, performing injection molding on the circuit substrate 2 provided with the electronic component and the pins 13 through a packaging mold to form a sealing layer 14, wherein the sealing layer 14 covers the mounting surface of the circuit substrate 2 on which the electronic component is mounted;
and S700, cutting off the connecting ribs among the pins 13 to form a semiconductor circuit to be tested, carrying out parameter test on the semiconductor circuit to be tested through test equipment, and if the test is qualified, bending and forming each pin 13 of the semiconductor circuit to be tested, which is qualified, based on the shape of the preset pin 13, so as to obtain the qualified semiconductor circuit.
According to the manufacturing method of the semiconductor circuit, the integrated mounting equipment can be used for improving the surface mounting efficiency of electronic elements, the automatic die bonding area and the surface mounting area are integrated in the mounting equipment, and the mounting equipment can complete the mounting procedures of the automatic die bonding area and the surface mounting area through the multifunctional connector 1. The automatic die bonding area comprises an HVIC bonding station, an IGBT bonding station and an FRD bonding station; the surface mounting area comprises a large radiating fin semi-finished product mounting station, a small radiating fin semi-finished product mounting station, a patch resistor 11 mounting station and a patch capacitor 12 mounting station. Therefore, the surface mounting system can mount surface components such as bare chips, auxiliary radiating fin semi-finished products, passive components and the like, and can realize the surface mounting of electronic elements of the semiconductor circuit through one mounting device. The UPH value of the surface mounting of the production line is improved, so that the production efficiency of manufacturing the whole semiconductor circuit is improved.
Referring to fig. 3 and 4, fig. 3 shows a process in the manufacturing process of the semiconductor circuit, mainly showing a schematic diagram from the completion of mounting to the completion of the finished semiconductor circuit, and fig. 4 shows a schematic diagram of a cross-sectional structure of the semiconductor circuit. The semiconductor circuit includes a circuit substrate 2, a circuit wiring layer 400, a plurality of electronic components, a plurality of pins 13, a sealing layer 14, a fixing bit 15, and the like. The circuit wiring layer 400 is provided on the mounting surface of the circuit board 2, and the circuit wiring layer 400 is provided with a plurality of predetermined mounting positions. The plurality of electronic components are disposed on the predetermined mounting positions of the circuit wiring layer 400. The circuit board 2 is made of a metal material, and includes an upper mounting surface and a lower heat dissipating surface, and may be a rectangular plate made of aluminum such as 1100 and 5052. An insulating layer 30000 (not shown in the drawing) is provided on the circuit substrate 2 to provide the circuit wiring layer 400 on the insulating layer 300, achieving electrical isolation between the circuit wiring layer 400 and the circuit substrate 2. The insulating layer 300 is made of a resin material such as epoxy resin and is filled with a filler such as alumina and aluminum carbide inside the resin material to cover at least one surface such as a mounting surface of the circuit substrate 2 to improve thermal conductivity. Meanwhile, in order to improve the thermal conductivity, the shape of these fillers may be angular, and in order to avoid the risk of the fillers damaging the contact surface of the electronic component provided on the surface thereof, the fillers may be spherical, angular or a mixture of angular and spherical. The circuit wiring layer 400 may be formed by copper foil etching or by printing a paste-like conductive medium, and the conductive medium may be a conductive material such as graphene, solder paste, or silver paste. Traces of the circuit are formed on the circuit wiring layer 400, and a plurality of connection pads for mounting the electronic components and the pins 13 are provided to connect the traces. The pins 13 are electrically connected and fixed to connection pads near the edge of the circuit board 2, and function to input and output signals from and to an external circuit connected to the MIPS, and as shown in fig. 4, a plurality of pins 13 are led out from one side of the circuit board 2. In other implementations it is also possible to lead from opposite sides of the circuit substrate 2. The leads 13 are generally made of metal such as copper, and a nickel-tin alloy layer is formed on the surface of the copper by electroless plating and electroplating, wherein the thickness of the alloy layer is generally 5 μm, and the plating layer can protect the copper from corrosion and oxidation and can improve solderability.
In general, as shown in fig. 4, the semiconductor circuit further includes a plurality of leads 13 and a sealing layer 14 for packaging the semiconductor circuit, the sealing layer 14 covers at least the mounting surface of the circuit board 2 and wraps the electronic component on the mounting surface, one ends of the plurality of leads 13 are electrically connected to the circuit wiring layer 400, and the other ends of the plurality of leads 13 can be exposed from the side surface of the sealing layer 14.
The sealing layer 14 may be formed of a resin, molded using a thermosetting resin by a transfer molding method, or molded using a thermoplastic resin by an injection molding method. The sealing layer 14 has two packaging structures, one is that the sealing layer 14 covers the upper and lower surfaces of the circuit substrate 2 and covers the electronic element arranged on the circuit substrate 2, and meanwhile, the pins 13 are also arranged at one end of the circuit substrate 2, so that the sealing layer 14 is completely covered; in another packaging method, the sealing layer 14 is coated on the upper surface of the circuit substrate 2, that is, the circuit substrate 2, the electronic component, and the leads 13 disposed at one end of the circuit substrate 2, and the lower surface of the circuit substrate 2, that is, the heat dissipation surface, is exposed to the sealing layer 14, so that a semi-coating method of the sealing layer 14 is formed. Fig. 3 shows a half-coating method of the sealing layer 14.
In some embodiments of the present invention, with continued reference to fig. 4, the semiconductor circuit further includes a plurality of bond wires connected between the plurality of electronic components, the circuit routing layer 400, and the plurality of leads 13. Such as bonding wires, may connect the electronic component to the electronic component, may connect the electronic component to the circuit wiring layer 400, and may connect the electronic component to the leads 13, and may connect the circuit wiring layer 400 to the leads 13. The electronic components are the first switching tube 10 and the first antiparallel diode 11, the second switching tube and the second freewheeling diode, the driving chip 6, and other passive components 9 such as the chip resistor 11, the chip capacitor 12, etc. mentioned in the above embodiments. The bonding wire is typically gold wire, copper wire, gold-copper hybrid wire, 38um or less thin aluminum wire, 100um or more thick aluminum wire. Bond wires are connected between the electronic components, such as between power devices, or between the power devices and the chip resistor 11 or the chip capacitor 12, in the space of the sealing layer 14 from the surface of the electronic components to the surface of the sealing layer 14. The surface of the circuit wiring layer 400 may also be coated with a green oil layer (not shown in the drawings) for protection. The green oil layer can prevent damage caused by short circuit between wirings of the circuit wiring layer 400, and also can prevent oxidation or contamination of the surface of the circuit wiring layer 400, thereby protecting.
The circuit board 2 which has been manufactured is put into a special-made carrier 4 (the carrier 4 can be a material which is resistant to high temperature of 200 ℃ or more, such as aluminum, synthetic stone, ceramic, PPS and the like), meanwhile, an auxiliary radiating fin is put into the special-made carrier (the carrier can be a material which is resistant to high temperature of 380 ℃ or more, such as aluminum, synthetic stone, ceramic, PPS and the like), and PFCIGBT, PFCFRD is welded on the auxiliary radiating fin through a soft solder die bonder to form a radiating fin semi-finished product, so that the preparation of the large radiating fin semi-finished product 10 and the small radiating fin semi-finished product 9 is completed. The method comprises the steps of mounting a reserved component mounting position on a copper foil circuit layer, mounting a chip HVIC6, a chip IGBT7, a chip FRD8, a resistor 11, a capacitor 12, a large radiating fin semi-finished product 9 and a small radiating fin semi-finished product 9 on a preset mounting position through brushing solder paste or dispensing silver paste, placing pins 13 on corresponding welding positions through a manipulator or manually, then welding all components on the corresponding mounting positions through a carrier 4 together through a reflow oven, detecting the welding quality of the components through visual inspection AOI equipment, removing foreign matters such as soldering flux and aluminum scraps remained on an insulating substrate through cleaning modes such as spraying, ultrasonic and the like, forming electric connection between an electronic component and circuit wiring through bonding wires, carrying out plastic packaging on the substrate circuit in a specific die through a packaging device, marking a product through laser marking, carrying out post-curing stress relief treatment on the product through a high-temperature oven, cutting ribs and dummy pins 13 into required shapes, and finally carrying out electrical parameter testing to form a qualified product.
In step S400, the mounting apparatus sucks HVIC6, IGBT7, FRD8, large heat sink semi-finished product 10, small heat sink semi-finished product 9, chip resistor 11 and chip capacitor 12 one by one onto corresponding preset mounting positions on the circuit substrate 2 through the multifunctional joint 1 of the mounting apparatus. The HVIC6, the IGBT7 and the FRD8 are placed on a blue film or a UV film after being diced through a bare chip in advance, so that the preparation work of chip material preparation is completed.
The material of the pin 13 can be C194 (-1/2H) plate (chemical components: cu (not less than 97.0), fe (2.4), P (0.03), zn (0.12)) or KFC (-1/2H) plate (chemical components: cu (not less than 99.6), fe (0.05-0.15) and P (0.03) (0.025-0.04)), and the C194 or KFC plate with the thickness of 0.5mm is processed by a stamping or etching process, and then nickel plating thickness is carried out on the surface by 0.1-0.5um, and then tin plating thickness is carried out by 2-5um; the extra connecting ribs of the pins 13 are cut off and shaped into a desired shape by a specific device.
In step S100, the circuit board 2 with a proper size may be designed according to the required circuit layout, for example, for a general semiconductor circuit, the size of the circuit board 2 may be 64mm×30mm. Taking the circuit substrate 2 as an aluminum substrate for example, the aluminum substrate is formed by directly carrying out milling treatment on aluminum material with the thickness of 1m multiplied by 1m, a milling cutter is made of high-speed steel, a motor is made of 5000 revolutions per minute, and the milling cutter and the plane of the aluminum material form a right angle for cutting; or may be formed by stamping. And the rugged texture can be formed on the back surface of the circuit substrate 2 by means of laser etching and polishing. Next, an insulating layer 300 is prepared on the surface of the circuit substrate 2, and the insulating layer 300 is used to connect the circuit wiring layer 400 and the circuit substrate 2 to cause a short circuit.
In step S200, a metal substrate such as copper foil may be laminated on the surface of the insulating layer 300, and then the surface of the metal substrate is processed, for example, by etching the copper foil, and the copper foil is partially removed to form the circuit wiring layer 400. A plurality of element mounting sites are formed on the circuit wiring layer 400, and pads are formed on the circuit wiring layer 400 at the portions of the first circuit substrate 2.
Further, a thinner green oil layer (not shown) may be further disposed on the surface of the circuit wiring layer 400, where the green oil layer coats the surface of the circuit wiring layer 400 except for the component mounting locations and the pads, to prevent damage caused by short circuit between the wirings of the circuit wiring layer 400, and to prevent oxidation and contamination of the surface of the circuit wiring layer 400, thereby protecting the circuit wiring layer 400.
In step S300, the lead 13 may be formed by preparing a copper substrate, for example, a strip shape with a length C of 25mm, a width K of 1.5mm, and a thickness H of 1mm, and then forming a nickel layer on the surface of the lead 13 by electroless plating: the nickel layer is formed on the surface of the copper material with a specific shape by mixing the nickel salt and the sodium hypophosphite and adding a proper complexing agent, the metal nickel has strong passivation capability, and an extremely thin passivation film can be rapidly formed, so that the corrosion of atmosphere, alkali and certain acid can be resisted. The nickel plating crystal is extremely fine, and the thickness of the nickel layer is generally 0.1 mu m; then, through an acidic sulfate process, the copper material with the formed shape and the nickel layer is immersed in a plating solution with positive tin ions at room temperature for electrifying, a nickel-tin alloy layer is formed on the surface of the nickel layer, the thickness of the nickel layer is generally controlled to be 5 mu m, and the formation of the nickel layer greatly improves the protectiveness and the weldability. In order to limit the space between the pins 13, a connecting rib is pressed at the second ends of the pins 13 through a specific die, so that a plurality of pins 13 can be conveniently and rapidly installed on the circuit substrate 2, and the preparation of the pins 13 is completed.
In step S400, the solder paste is applied to the preset mounting locations and pads of the circuit wiring of the circuit substrate 2 by a solder paste printer and a steel mesh, wherein the steel mesh may have a thickness of 0.13mm, and the preset mounting locations and pads are required to be soldered, such as soldering electronic components (including auxiliary heat dissipation plate semi-finished products) at the preset mounting locations. Or a silver paste dispenser, wherein a specific pattern is coated on a preset mounting position and a bonding pad by silver paste, and the electronic elements can be welded on the positions through the silver paste.
Then, electronic components and pins 13 are installed, the electronic components can be directly placed at preset installation positions, one ends of the pins 13 are to be placed on the bonding pads, the other ends of the pins need to be fixed by a carrier, the carrier is made of materials such as synthetic stone and stainless steel, and the pins 13 are conveniently fixed at the positions of the bonding pads due to the connection effect of reinforcing ribs. The special carrier may be made of a material resistant to high temperatures of 200 ℃ or more, such as aluminum, synthetic stone, ceramic, PPS, or the like. Then, the circuit board 2 placed on the carrier is cured by reflow soldering, solder paste or silver paste, and the electronic component (including the auxiliary heat dissipation plate semi-finished product) and the leads 13 are soldered to the predetermined mounting positions and pads, respectively.
In step S500, the step is a step of connecting the bonding wire traces. One of the drive bond pads of the drive chip traces in the electronic component may be directly connected to the gate bond pad of the power device, such as IGBT7, by a bond wire such as gold wire, copper wire, gold-copper hybrid wire, or a thin aluminum wire of 38um or less, and the other drive bond pad traces of the drive chip may be directly connected to the bond pad of the circuit wiring layer 400 by a bond wire such as gold wire, copper wire, gold-copper hybrid wire, a thin aluminum wire of 38um or less. The emitter bonding area of the IGBT7 is directly connected to the pad of the circuit wiring layer 400 through a thick aluminum line of 100um or more.
In step S600, this step is a step of forming the sealing layer 14. The circuit substrate 2 with the electronic components and pins 13 mounted in the process of the steps can be baked in an oxygen-free environment for not less than 2 hours, and the baking temperature can be 5 ℃. The circuit board 2 with the pins 13 disposed thereon is transferred to a packaging mold, and after mold clamping, sealing resin is injected. The sealing may be performed by transfer molding using a thermosetting resin or injection molding using a thermosetting resin. Finally, demolding is performed, after which the sealing resin is cured to form the sealing layer 14, and the free ends of the leads 13 are exposed from the sealing layer 14.
In step S700, first, a connecting rib (not shown) connecting the other ends of the plurality of pins 13 is cut off to form a semiconductor circuit to be tested, wherein the connecting rib is a residue generated during the preparation of the pins 13, and the connecting rib may cause a short circuit between the pins 13 and 13, so that the connecting rib needs to be cut off during the preparation of the semiconductor circuit. In one example, the connection ribs connecting the second ends of the plurality of pins 13 may be cut off by a specific device, so that the other ends of the pins 13 are disconnected from each other, and the semiconductor circuit to be tested is obtained, so that the semiconductor circuit to be tested is subjected to parameter test in the next step.
The test equipment can be used for carrying out parameter test on the semiconductor circuit to be tested, for example, the test equipment can send test signals to the semiconductor circuit to be tested and receive feedback signals fed back by the semiconductor circuit to be tested; the testing equipment processes the feedback signal to obtain corresponding feedback data, compares the feedback data with a preset threshold range, and judges that the semiconductor circuit to be tested is qualified when the feedback data meets the preset threshold range, so that each pin 13 of the semiconductor circuit to be tested, which is qualified in test, can be bent and molded based on the shape of the preset pin 13, and the qualified semiconductor circuit is obtained.
Further, before the testing device can be used for testing parameters of the semiconductor circuit to be tested, laser marking can be performed by the laser device to mark the surface of the sealing layer 14 of the semiconductor circuit, so that the semiconductor circuit product can be identified and managed conveniently.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings are merely for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the device or element being referred to must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the present invention.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present invention, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically defined otherwise.
In the present invention, unless explicitly specified and limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; either directly or indirectly, through intermediaries, or both, may be in communication with each other or in interaction with each other, unless expressly defined otherwise. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.
In the present invention, unless expressly stated or limited otherwise, a first feature "up" or "down" a second feature may be the first and second features in direct contact, or the first and second features in indirect contact via an intervening medium. Moreover, a first feature being "above," "over" and "on" a second feature may be a first feature being directly above or obliquely above the second feature, or simply indicating that the first feature is level higher than the second feature. The first feature being "under", "below" and "beneath" the second feature may be the first feature being directly under or obliquely below the second feature, or simply indicating that the first feature is less level than the second feature.
While embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and not to be construed as limiting the invention, and that variations, modifications, alternatives and variations may be made to the above embodiments by one of ordinary skill in the art within the scope of the invention.

Claims (10)

1. A mounting apparatus for semiconductor circuits is characterized in that the mounting apparatus comprises a multifunctional joint, an automatic die bonding area and a surface mounting area are integrated in the mounting apparatus, the mounting apparatus can complete the mounting procedures of the automatic die bonding area and the surface mounting area through the multifunctional joint,
the automatic die bonding area comprises an HVIC bonding station, an IGBT bonding station and an FRD bonding station; the surface mounting area comprises a large radiating fin semi-finished product mounting station, a small radiating fin semi-finished product mounting station, a chip resistor mounting station and a chip capacitor mounting station.
2. The mounting apparatus for semiconductor circuits of claim 1, wherein the multi-function header is a rotary integrated header.
3. The mounting apparatus for semiconductor circuits according to claim 2, wherein said multi-functional joints include a passive component rotation joint for mounting said chip resistor and chip capacitor, a heat sink semi-finished joint for mounting said large heat sink semi-finished product and said small heat sink semi-finished product, an HVIC chip joint for sucking HVIC, an IGBT chip joint for sucking IGBT, and an FRD chip joint for sucking FRD.
4. The mounting apparatus for a semiconductor circuit according to claim 1, wherein the HVIC number of pastes is 1, the IGBT number of pastes is 6, the FRD number of pastes is 6, the number of pastes of the large heat sink semi-finished product is 1, the number of pastes of the small heat sink semi-finished product is 1, and the number of pastes of the chip resistor and the chip capacitor are both greater than 10.
5. The mounting apparatus for semiconductor circuits of claim 4, said chip resistor and chip capacitor being reel materials, said HVIC, said IGBT and said FRD being wafer materials, said large heat spreader half-finished product and said small heat spreader half-finished product each comprising an auxiliary heat spreader and a power chip.
6. The mounting apparatus for semiconductor circuits according to any one of claims 1 to 5, further comprising a transportation rail capable of carrying and transporting a circuit substrate of the semiconductor circuit, the multifunctional joint being provided to one side of the rail.
7. A method of manufacturing a semiconductor circuit, the method comprising:
step S100, providing a circuit substrate;
step 200, sequentially preparing an insulating layer and a circuit wiring layer on the mounting surface of the circuit substrate;
step S300, preparing pins, wherein one ends of a plurality of pins are connected with each other through connecting ribs;
step S400, configuring electronic elements and pins on the circuit wiring layer, wherein preset mounting positions for configuring the electronic elements are reserved on the circuit wiring layer, and solder paste or silver-dispensing glue is arranged on the preset mounting positions;
wherein the electronic component is mounted onto the preset mounting position using the mounting apparatus for a semiconductor circuit according to any one of claims 1 to 6; placing the pins at the corresponding preset mounting positions by a manipulator or manually, and then placing the whole semi-finished product into a reflow oven to solder the electronic element and the pins on the circuit substrate;
step S500, electrically connecting the electronic element and the circuit wiring layer through bonding wires;
step S600, injection molding is carried out on the circuit substrate provided with the electronic element and the pin through a packaging mould to form a sealing layer, wherein the sealing layer covers a mounting surface of the circuit substrate for mounting the electronic element;
and S700, cutting off the connecting ribs among the pins to form a semiconductor circuit to be tested, carrying out parameter test on the semiconductor circuit to be tested through test equipment, and if the test is qualified, bending and forming each pin of the semiconductor circuit to be tested, which is qualified, based on a preset pin shape to obtain the qualified semiconductor circuit.
8. The method according to claim 7, wherein in step S400, the mounting apparatus sucks the HVIC, IGBT, FRD, the large-fin semi-finished product, the small-fin semi-finished product, the chip resistor and the chip capacitor one by one onto the corresponding preset mounting positions on the circuit substrate through the multifunctional joints of the mounting apparatus.
9. The method of manufacturing a semiconductor circuit according to claim 8, wherein the HVIC, IGBT and FRD are each placed on a blue film or a UV film after dicing by a bare chip.
10. The method of manufacturing a semiconductor circuit according to claim 7, wherein an auxiliary heat sink and a functional chip are provided and the functional chip is attached to the auxiliary heat sink to complete the preliminary provision of the large-fin semifinished product and the small-fin semifinished product, prior to step S400.
CN202111572353.5A 2021-12-21 2021-12-21 Mounting apparatus for semiconductor circuit and method of manufacturing semiconductor circuit Pending CN116314153A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202111572353.5A CN116314153A (en) 2021-12-21 2021-12-21 Mounting apparatus for semiconductor circuit and method of manufacturing semiconductor circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202111572353.5A CN116314153A (en) 2021-12-21 2021-12-21 Mounting apparatus for semiconductor circuit and method of manufacturing semiconductor circuit

Publications (1)

Publication Number Publication Date
CN116314153A true CN116314153A (en) 2023-06-23

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Family Applications (1)

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