CN114038812A

CN114038812A - Semiconductor circuit and method for manufacturing semiconductor circuit

Info

Publication number: CN114038812A
Application number: CN202111245287.0A
Authority: CN
Inventors: 冯宇翔
Original assignee: Guangdong Huixin Semiconductor Co Ltd
Current assignee: Guangdong Huixin Semiconductor Co Ltd
Priority date: 2021-10-26
Filing date: 2021-10-26
Publication date: 2022-02-11

Abstract

The present invention relates to a semiconductor circuit including a circuit substrate, a circuit wiring layer, an insulating layer, a plurality of electronic components, a plurality of pins, and a package, and a method of manufacturing the semiconductor circuit. The packaging body is used for covering and packaging the semiconductor circuit and can wrap a plurality of electronic elements on the mounting surface of the circuit substrate, the other ends of the pins can be exposed out of the packaging body, in addition, the packaging body also wraps one side of the heat dissipation surface of the circuit substrate, and the packaging body is provided with a heat dissipation surface step part on one side of the heat dissipation surface so as to increase the creepage distance between the pins and the radiator. According to the semiconductor circuit, the packaging body is wrapped on one side of the heat dissipation surface of the circuit substrate, and the step part of the heat dissipation surface is formed, so that the creepage distance between the pins and the heat sink is further increased, and the product voltage endurance capability of the semiconductor circuit is effectively improved.

Description

Semiconductor circuit and method for manufacturing semiconductor circuit

Technical Field

The invention relates to a semiconductor circuit and a manufacturing method of the semiconductor circuit, and belongs to the technical field of semiconductor circuit application.

Background

A semiconductor circuit is a power-driven type product that combines power electronics and integrated circuit technology. The outer surface of a semiconductor circuit is generally encapsulated with a resin material formed by injection molding to form an encapsulation, and an internal circuit board and an electronic component are encapsulated, and pins protrude from one side or both sides of the encapsulation. With the competitive demands of the market, miniaturization and low-cost competition, higher requirements are put forward on the high integration and high heat dissipation technology of the MIPS modular intelligent power system. In a conventional power semiconductor device, a large current or a high voltage is generally applied between pins, and along with the development of mainstream technology, the size of the device is often required to be sufficiently reduced to meet the requirement of lightness, and a corresponding negative effect is that an insulating material around the pins which are very close to each other is easily polarized, so that the insulating material presents a charging phenomenon to influence the normal operation of the device, a serious condition can bring about a safety hazard, and particularly under a severe environment of moisture or dust, the creepage phenomenon tends to be serious.

Disclosure of Invention

Based on this, the technical problems to be solved by the invention are: how to solve the problem that creepage occurs between a pin of a semiconductor circuit and a radiator to cause that the requirement under the high-voltage condition is not met.

Specifically, the present invention discloses a semiconductor circuit comprising:

a circuit substrate including a mounting surface and a heat dissipation surface;

an insulating layer disposed on the mounting surface;

the circuit wiring layer is arranged on the surface of the insulating layer and provided with a plurality of preset mounting positions;

a plurality of electronic components arranged on the preset mounting positions of the circuit wiring layer;

the pins are electrically connected with the circuit wiring layer at one ends respectively;

the packaging body, the packaging body is used for covering and encapsulating semiconductor circuit can wrap up circuit substrate the installation face a plurality of electronic component, it is a plurality of the other end of pin can be followed the packaging body exposes, and, the packaging body still wraps up circuit substrate one side of radiating surface, the packaging body is in radiating surface one side is provided with radiating surface step portion, in order to increase the creepage distance of pin and radiator.

Optionally, the heat dissipation surface step portion is tightened to the center of the heat dissipation surface, so that a protruding step in a convex shape is formed on the surface of the heat dissipation surface.

Optionally, the package body is provided with a step-shaped mounting surface step portion on one side of the mounting surface, and the mounting surface step portion and the heat dissipation surface step portion are symmetrically arranged on two sides of the package body.

Optionally, the package body is further provided with an assembly hole, and the assembly hole is a recessed countersunk hole and is disposed on two sides of the circuit substrate.

Optionally, the assembly hole penetrates through the thickness direction of the package body, and the assembly hole is radially communicated with the outside so as to form gaps at two ends of the package body.

Optionally, a plurality of the pins comprise:

the first ends of the first pins are respectively and electrically connected with the circuit wiring layer;

the first ends of the second pins are respectively and electrically connected with the circuit wiring layer;

the packaging body wraps the circuit wiring layer of each first pin and each second pin;

the second end of each first pin is led out from the first side surface of the packaging body, and first leading-out parts which correspond to each other one by one are formed on the first side surface of the packaging body; the second ends of the second pins are respectively led out from the first side surface of the packaging body, and second lead-out parts which are in one-to-one correspondence are formed on the first side surface of the packaging body; the first side of packaging body is equipped with a plurality of creepage recess, creepage recess is located adjacent first extraction portion with between the second extraction portion.

Optionally, the semiconductor circuit further includes a green oil layer that avoids the electronic element and the pin and is disposed on a surface of the circuit wiring layer.

Optionally, on the mounting surface side of the circuit substrate, the package body is provided with a positioning hole and a demolding hole,

the positioning hole is penetratingly arranged in the thickness direction of the packaging body and reaches the surface of the circuit substrate, so that the surface of the circuit substrate is exposed outwards from the bottom of the positioning hole;

the demolding hole is in a blind hole shape, the demolding hole and the positioning hole are both arranged on the periphery of the packaging body, and the positioning hole is arranged in a position which is deviated from the center of the packaging body relative to the demolding hole.

Optionally, the semiconductor circuit further comprises a plurality of bonding wires connected between the plurality of electronic elements, the circuit wiring layer and the plurality of pins.

In addition, the present invention provides a method of manufacturing a semiconductor circuit, the semiconductor circuit described above, the method including:

providing a circuit substrate which comprises a mounting surface and a heat dissipation surface;

preparing an insulating layer and a circuit wiring layer on the mounting surface of the circuit substrate in sequence;

preparing pins, wherein one ends of the pins are connected with each other through connecting ribs;

configuring electronic elements and pins on the circuit wiring layer;

electrically connecting the electronic element and the circuit wiring layer through a bonding wire;

performing injection molding on the circuit substrate provided with the electronic element and the pins through a packaging mold to form a packaging body, wherein the packaging body wraps a mounting surface of the circuit substrate for mounting the electronic element, assembling holes are formed at two ends of the packaging body, the surface of each assembling hole is lower than the surface of the packaging body and forms a countersunk hole, one side of the mounting surface of the circuit substrate is provided with a positioning hole with the bottom reaching the surface of the circuit substrate and a demolding hole which is closer to the middle part of the circuit substrate relative to the position where the positioning hole is arranged, the depth of the demolding hole is smaller than that of the positioning hole, the demolding hole and the positioning hole are both arranged at the peripheral part of the packaging body, and the circuit substrate is exposed relative to the packaging body at the bottom of the positioning hole;

the package body also covers the heat dissipation surface of the circuit substrate, an inward-folded heat dissipation surface stepped part is formed on one side of the heat dissipation surface, and a mounting surface stepped part with a cross section symmetrical to the heat dissipation surface stepped part relative to the middle section of the thickness direction of the package body is formed on the mounting surface of the circuit substrate;

and cutting off the connecting ribs among the pins to form a semiconductor circuit to be tested, performing parameter test on the semiconductor circuit to be tested through test equipment, and bending and molding the pins of the semiconductor circuit to be tested which are qualified in test based on a preset pin shape if the test is qualified according to the result of the parameter test to obtain the qualified semiconductor circuit.

The semiconductor circuit of the present invention includes a circuit substrate, a circuit wiring layer, an insulating layer, a plurality of electronic components, a plurality of pins, and a package. The packaging body is used for covering and packaging the semiconductor circuit, can wrap a plurality of electronic elements of the installation surface of the circuit substrate, can expose the other ends of a plurality of pins from the packaging body, and also wraps one side of the heat dissipation surface of the circuit substrate, and is provided with a heat dissipation surface step part on one side of the heat dissipation surface so as to increase the creepage distance between the pins and the radiator. According to the semiconductor circuit, the packaging body is wrapped on one side of the heat dissipation surface of the circuit substrate, and the step part of the heat dissipation surface is formed, so that the creepage distance between the pins and the heat sink is further increased, and the product voltage endurance capability of the semiconductor circuit is effectively improved.

Drawings

FIG. 1 is a perspective view of a semiconductor circuit in accordance with an embodiment of the present invention;

FIG. 2 is a top view of a semiconductor circuit according to an embodiment of the present invention;

FIG. 3 is a front view of a semiconductor circuit in accordance with an embodiment of the present invention;

FIG. 4 is a cross-sectional view of a semiconductor circuit in accordance with an embodiment of the present invention;

FIG. 5 is a perspective view of a semiconductor circuit mounting heat sink of an embodiment of the present invention;

FIG. 6 is a flow chart of a method of fabricating a semiconductor circuit in accordance with an embodiment of the present invention;

FIG. 7 is a diagram illustrating a method of forming a package during semiconductor circuit fabrication in accordance with one embodiment of the present invention.

Reference numerals:

package 10, assembly hole 11, positioning hole 12, demolding hole 13, creepage groove 14, heat dissipation surface step 15, mounting surface step 16, heat sink 20, circuit substrate 30, insulating layer 40, circuit wiring layer 50, pad 51, electronic component 60, bonding wire 70, pin 80, first pin 801, second pin 802, fastener 90, gate 201, thimble 202, upper die 203, lower die 204, fixing device 205, and exhaust port 206.

Detailed Description

It is to be noted that the embodiments and features of the embodiments may be combined with each other without conflict in structure or function. The present invention will be described in detail below with reference to examples.

The semiconductor circuit, namely the modular Intelligent Power system mips (modular Intelligent Power system), not only integrates the Power switch device and the driving circuit, but also embeds fault detection circuits such as overvoltage, overcurrent and overheat, and can send detection signals to a CPU or a DSP for interrupt processing. In a conventional semiconductor circuit, a pin for transmitting a high-voltage power output signal and a pin for transmitting a low-voltage logic control signal are both included in the same package. There is a large potential difference between the different types of pins, and also between the pin of the high voltage power output signal and the heat sink. Normally, the potential difference of 500-800V exists between the high-voltage pin and the low-voltage pin, and the potential difference of 500-800V exists between the high-voltage signal pin and the heat sink. However, due to the limitation of the individual size of the semiconductor circuit, it is difficult to satisfy the requirements of safe creepage distance at multiple positions on the semiconductor circuit, such as creepage distance between pins or creepage distance between pins and heat sink.

As shown in fig. 1 and 2, the semiconductor circuit includes a circuit substrate 30, a circuit wiring layer 50, an insulating layer 40, a plurality of electronic components 60, a plurality of leads 80, and a package 10. The circuit substrate 30 includes a mounting surface and a heat dissipation surface, the insulating layer 40 is disposed on the mounting surface, the circuit wiring layer 50 is disposed on the surface of the insulating layer 40, the circuit wiring layer 50 is provided with a plurality of preset mounting positions and pads 51, the plurality of electronic components 60 are disposed on the preset mounting positions of the circuit wiring layer 50, the plurality of pins 80 are disposed on at least one side of the circuit substrate 30, the package 10 is used for covering and packaging a semiconductor circuit, the plurality of electronic components 60 on the mounting surface of the circuit substrate 30 can be packaged, the other ends of the plurality of pins 80 can be exposed from the package 10, the package further packages one side of the heat dissipation surface of the circuit substrate 30, and the package 10 is provided with a heat dissipation surface step 15 on one side of the heat dissipation surface to increase a creepage distance between the pins 80 and the heat sink 20.

The semiconductor circuit of the invention not only wraps the packaging body 10 on one side of the heat dissipation surface of the circuit substrate 30, but also forms the step part 15 of the heat dissipation surface, so that the creepage distance between the pin 80 and the heat sink 20 (see figure 5) is further increased, and the voltage endurance capability of the semiconductor circuit product is effectively improved.

Among them, the circuit substrate 30 is used for carrying the electronic component 60 and the like in the semiconductor circuit, and the circuit substrate 30 includes both a mounting surface on the front surface and a heat radiation surface on the back surface for mounting a heat sink (see fig. 5) and the like. The circuit substrate 30 may be made of a metal material, such as a rectangular plate made of aluminum of 1100, 5052, etc., and the thickness of the rectangular plate is much thicker than other layers, generally 0.8mm to 2mm, and the common thickness is 1.5mm, so as to mainly achieve the heat conduction and heat dissipation effects on electronic components such as power devices, etc. For another example, the circuit board 30 may be made of other metal materials with good thermal conductivity, for example, a rectangular plate made of copper. The shape of the circuit board 30 of the present invention is not limited to a rectangular shape, and may be a circular shape, a trapezoidal shape, or the like. The heat dissipation surface of the circuit substrate 30 may be textured by laser etching or grinding (not shown) to enhance the bonding force with the middle package 10. The insulating layer 40 is disposed on the mounting surface of the circuit board 30, and the thickness of the insulating layer is thinner than that of the circuit board 30, generally 50um to 150um, and usually 110 um. The insulating layer 40 may be made of a resin material such as epoxy resin, and a filler such as alumina and aluminum carbide may be filled inside the resin material to improve thermal conductivity. In order to improve the thermal conductivity, the shape of these fillers may be angular, and in order to avoid the risk of the fillers damaging the contact surface of the electronic component 60 provided on the surface thereof, the fillers may be spherical, angular, or a mixture of angular and spherical.

Specifically, referring to fig. 1 to 3, in the specific structure of the package 10, optionally, the heat dissipation surface step portion 15 is arranged to be tightened toward the center of the heat dissipation surface, so as to form a protruding step in a "convex" shape on the surface of the heat dissipation surface. Certainly, the heat dissipating surface step portion 15 of this scheme can also form the protruding ladder that is evagination (i.e. the form of falling "protruding") and also be the protection scheme of this scheme, but compare, the heat dissipating surface step portion 15 that is the protruding ladder of "protruding" form more is favorable to practicing thrift the using material of packaging body 10, helps the requirement of the cost reduction of product. Of course, the step number of the raised step of the heat dissipation surface step 15 is not limited to one step, and may be two or more steps, which are all the protection schemes of the present invention.

Meanwhile, since the package 10 is wrapped around the outside of the semiconductor circuit, in order to ensure the aesthetic appearance of the semiconductor circuit, the package 10 is provided with a step-shaped mounting surface step 16 on one side of the mounting surface, and the mounting surface step 16 and the heat dissipation surface step 15 are symmetrically arranged on both sides of the package 10.

Compared with the prior art that the design of the assembly hole 11 is complex and an independent process is required in the process of a mold program, the assembly hole 11 and the package body 10 are integrally formed, so that the design and the formation of the assembly hole 11 can be completed synchronously with the process of the package body 10, the production process is effectively simplified, and the production efficiency of products is improved. Specifically, during the manufacturing process of the package 10 and the assembly holes 11, the circuit wiring layer 50 electrically connected to the plurality of pins 80 and the plurality of electronic components 60 may be plastically packaged in the package 10 by a plastic package mold through a plastic package process. The material of the package 10 may be thermosetting polymer, such as epoxy resin, phenolic resin, silica gel, amino group, unsaturated resin; in order to improve the heat dissipation capability, the package 10 may be a composite material containing powder or fiber of metal, ceramic, silicon oxide, graphene, or the like. In one example, the material used for the package 10 may be a molding compound prepared by mixing an epoxy resin as a matrix resin, a high-performance phenolic resin as a curing agent, silica powder and the like as fillers, and various additives.

The mounting holes 11 are recessed counter bores and are provided on both sides of the circuit board 30. The plastic package material at the position of the assembly hole 11 is thinner than the plastic package material at other positions, and after the fastener 90 (see fig. 5, such as a screw) is installed, the nut does not protrude and is placed in the recessed counter bore, so that the assembly and storage are convenient, and the consumption of raw materials of the package body 10 is reduced, and the material cost is reduced. And, once the fitting hole 11 is provided with a sunk countersunk hole, the step height of the mounting surface step portion 16 thereof can be maintained to be identical to the sunk height of the fitting hole 11, facilitating the manufacture, see fig. 1.

The circuit wiring layer 50 may be formed by etching a copper foil provided on the surface of the insulating layer 40, or may be formed by printing a paste-like conductive medium, which may be a conductive material such as graphene, solder paste, or silver paste. The thickness of the circuit wiring layer 50 is substantially equivalent to that of the insulating layer 40, and is relatively thin, for example, about 70 um. The surface of the circuit wiring layer 50 is provided with a plurality of preset mounting positions for mounting a plurality of electronic components 60, each electronic component 60 includes a power device and a driving chip, wherein the power device includes a switching tube such as an IGBT (Insulated Gate Bipolar Transistor) or a MOS (metal oxide semiconductor) and a freewheeling diode, and the power consumed by the operation of the power device is large and the amount of heat generated is large, so that the temperature of the whole semiconductor circuit is higher than the room temperature in the operation process. The electronic component 60 also includes passive devices such as resistors, capacitors, and the like. For the power device with very large calorific value, the power device is fixedly arranged at a preset mounting position through a metal radiating fin. The circuit wiring layer 50 and the plurality of electronic components 60 mounted on the circuit wiring layer 50 constitute the entire circuit of the semiconductor circuit.

The periphery of the surface of the circuit wiring layer 50 is also provided with a plurality of pads 51 to fix the pins 80, thereby transmitting signals to the internal circuit of the semiconductor circuit. The lead 80 is generally made of a metal such as copper, a nickel-tin alloy layer is formed on the surface of the copper by chemical plating and electroplating, the thickness of the alloy layer is generally 5 μm, and the copper can be protected from corrosion and oxidation by the plating layer and the solderability can be improved.

The lead 80 can be made of C194(-1/2H) plates (chemical components: Cu (97.0), Fe (2.4), P (0.03) and Zn (0.12)) or KFC (-1/2H) plates (chemical components: Cu (99.6), Fe (0.1-0.05) and P (0.03, 0.025-0.04)), the C194 or KFC plates with the thickness of 0.5mm are processed by a stamping or etching process, nickel plating thickness is 0.1-0.5um firstly, and tin plating thickness is 2-5um secondly; the excess connecting ribs of the pins 80 are cut and shaped into the desired shape by a special device.

In the semiconductor circuit of the present invention, as shown in fig. 1 to 3, the plurality of pins 80 includes:

a plurality of first pins 801, wherein first ends of the plurality of first pins 801 are electrically connected with the circuit wiring layer 50 respectively;

a plurality of second pins 802, wherein first ends of the plurality of second pins 802 are electrically connected to the circuit wiring layer 50, respectively;

the package 10 encloses the circuit wiring layer 50 of each first pin 801 and each second pin 802;

the second end of each first pin 801 is led out from the first side surface of the package body 10, and first lead-out portions corresponding to each other one by one are formed on the first side surface of the package body 10; the second end of each second pin 802 is led out from the first side surface of the package 10, and second lead-out portions corresponding to each other are formed on the first side surface of the package 10; a plurality of creepage grooves 14 are arranged on the first side surface of the packaging body 10, and the creepage grooves 14 are positioned between the adjacent first lead-out part and the second lead-out part. The first side surface of the package 10 is a side surface in which the thickness direction of the package 10 is located.

In the application, the creepage grooves 14 are arranged between the adjacent first lead-out parts and the adjacent second lead-out parts, namely the creepage grooves 14 are arranged on the package bodies 10 of the adjacent first pins 801 and the adjacent second pins 802. For example, the size of the creepage groove 14 is designed to be a depth h, the distance between the adjacent first pin 801 and the second pin 802 is a, after the creepage groove 14 is arranged, the creepage distance between the adjacent first pin 801 and the second pin 802 is increased to a +2h, so that the creepage distance of the intelligent power module is increased under the condition of meeting the overall size requirement of the intelligent power module, the safe creepage distance meeting the requirement is realized by the product, the voltage endurance of the product is improved, and the use cost of the plastic package material of the package body 10 is reduced.

Further, a thin layer of green oil (not shown) is disposed on the surface of the circuit wiring layer 50 where the predetermined mounting locations and the pads 51 are not disposed, and serves to prevent short circuits between the traces of the circuit wiring layer 50 and also to prevent oxidation and contamination of the surface of the circuit wiring layer 50, thereby protecting the circuit wiring layer.

In some embodiments of the present invention, as shown in fig. 1 to 3, the mounting holes 11 are communicated radially outward to form notches at both ends of the package body 10. Thus, in the semiconductor circuit of the present invention, the circuit substrate 30 may be a rectangular plate-shaped structure, and when the package body 10 is injection molded, the package body 10 is wrapped and formed on both sides of the circuit substrate 30, and the mounting holes 11 communicating radially outward are formed. This not only facilitates manufacture, but also facilitates installation and securement of the fastener.

Further, the cross-section of the fitting hole 11 may be selected to be U-shaped. Here, the cross section is a parallel plane with respect to the surface of the circuit substrate 30. Compared with the cross section of a bell mouth, the U-shaped cross section is more beneficial to the fastening installation of the fastener.

With continued reference to fig. 1 to 3, on the mounting surface side of the circuit substrate 3, the package body 10 is provided with a positioning hole 12 penetrating through the thickness direction thereof and reaching the surface of the circuit substrate 30, so that the surface of the circuit substrate 30 is exposed outward from the bottom of the positioning hole 12. The positioning holes 12 are formed by positioning the ejector pins 202 mounted on the mold for packaging on the surface of the circuit substrate 30 when the package 10 is formed. According to different design requirements, plastic package molds with different shapes can be designed, and then the sealing bodies 10 with different shapes and structures can be obtained through plastic package. For example, the circuit substrate 30, the circuit wiring layer 50, the electronic components 60 and the pins 80 are wrapped by an injection molding method using a thermoplastic resin or a transfer molding method using a thermosetting resin to protect them, in this process, the free end of the ejector pin 202 of the mold abuts against the surface of the circuit substrate 30 to position the circuit substrate 30 accurately, and then after the resin heated to a liquid state is injected into the cavity of the mold, the mold is removed and the ejector pin 202 is pulled out, and after the resin is hardened, the positioning hole 12 is formed at the position where the ejector pin 202 is pulled out from the resin. Since the ejector pins 202 are abutted against the surface of the circuit substrate 30, the bottom of the positioning holes 12 are exposed from the circuit substrate 30. The surface of the circuit substrate 30 exposed here may also be covered with the insulating layer 40, so that the surface of the metal layer of the circuit substrate 30 is not exposed, thereby ensuring proper insulating properties of the circuit substrate 30.

Further, regardless of the shape of the circuit board 30, in the semiconductor circuit of the present invention, the positioning hole 12 is optionally provided in the outer peripheral portion of the circuit board 30, and the circuit wiring layer 50 is not provided at the position of the positioning hole 12. This is because the circuit wiring layer 50 is not provided in a small area of the outer peripheral portion of the circuit substrate 30 to form a boundary. Typically, in manufacturing the circuit substrate 30, a plurality of circuit substrates 30 are disposed on a single piece of metal substrate, and boundary regions are disposed between each circuit substrate 30 to facilitate cutting by mechanical equipment at these boundary regions to separate each individual circuit substrate 30. During the formation of the package 10, the ejector pins 202 of the mold will abut against these boundary regions, and once the ejector pins 202 abut against the circuit wiring layer 50 region, the tips of the ejector pins 202 will contact the surface of the circuit wiring layer 50 or the surface of the electronic element 60, which may damage the circuit wiring layer 50 or damage the electronic element 60, so that the circuit wiring layer 50 cannot be disposed on the circuit substrate 30 corresponding to the tips of the ejector pins 202. If the thimble 202 does not abut against the outer edge area of the circuit substrate 30, a blank area without wires needs to be reserved in one way in the area where the circuit wiring layer 50 is located to serve as a position where the thimble 202 abuts against, which occupies the use area of the circuit wiring layer 50, and causes the area of the whole circuit substrate 30 to be too large, thereby causing waste and being inconvenient for miniaturization design. In the semiconductor circuit of the present invention, the thimble 202 abuts against the boundary region where the outer periphery of the circuit substrate 30 is located, and does not occupy the region of the circuit wiring layer 50, thereby improving the effective area utilization rate of the circuit wiring layer 50. Moreover, by observing the state of the circuit substrate 30 at the bottom of the positioning hole 12, it can be confirmed whether the position of the circuit substrate 30 in the package 10 reaches the standard, that is, whether the circuit substrate 30 moves when being disposed in the mold cavity during the formation of the package 10. If the circuit substrate 30 moves horizontally, so that the position where the thimble 202 abuts enters the area where the circuit wiring layer 50 is located, part or all of the circuit wiring layer 50 is exposed from the bottom of the positioning hole 12; or if the circuit substrate 30 moves vertically, the position of the ejector pin 202 may not be able to abut against the surface of the circuit substrate 30, so that the bottom of the positioning hole 12 does not expose the circuit substrate 30. Therefore, only the bottom of the positioning hole 12 exposes the surface of the circuit wiring layer 50, specifically, exposes the surface of the insulating layer 40 covered by the circuit wiring layer 50, and the position of the circuit substrate 30 in the package 10 can be determined to be qualified, so that the quality inspection efficiency of the whole semiconductor circuit can be improved.

Among them, the package 10 generally has two package structures. One is that the package 10 covers both sides of the circuit substrate 30, i.e. the mounting surface and the heat dissipation surface, specifically, the side on which the electronic component 60 is mounted and the heat dissipation surface of the circuit substrate 30, which are disposed on the circuit substrate 30, and the package 10 also covers a part of the length of the end of the pin 80 connected to the circuit substrate 30, which is a full-covering manner of the package 10, see fig. 1 to 3; in another package method, the package 10 covers only the upper surface of the circuit substrate 30, i.e. the mounting surface of the circuit substrate 30 and the electronic component 60, and the package 10 also covers a portion of the length of the pin 80 connected to one end of the circuit substrate 30, and the back surface of the circuit substrate 30, i.e. the heat dissipation surface, is exposed out of the package 10, thereby forming a half-package method of the package 10. In the full-coating mode, when the back surface of the circuit substrate 30 is provided with the texture, the bonding strength between the circuit substrate and the package body 10 can be effectively enhanced, so that the circuit substrate and the package body are not easy to separate.

In some embodiments of the present invention, as shown in fig. 1 to 3, on the mounting surface side of the circuit substrate 30, the package body 10 is further provided with a mold release hole 13 in a blind hole shape, the mold release hole 13 and the positioning hole 12 are both provided on the outer periphery of the package body 10, and the positioning hole 12 is provided further away from the center position of the package body 10 with respect to the mold release hole 13. Both the positioning hole 12 and the demolding hole 13 are disposed at the outer peripheral portion of the package body 10, and further, the depth of the demolding hole 13 is optionally smaller than the depth of the positioning hole 12. This is because the mold release hole 13 is generated when the package 10 is formed. In general, a protruded mold release column is further disposed in the mold cavity, and when the mold is removed after the resin heated to liquid state is injected into the mold cavity of the mold, the mold release column abuts against the surface of the resin, so that the molded resin is released from the mold cavity of the mold, and the package 10 is formed after the resin is hardened. When the demoulding column is pressed against the surface of the resin, the demoulding column can penetrate into the surface of the resin to form a groove, and when the resin is separated from the mould cavity, the groove forms a blind hole-shaped demoulding hole 13. Since the mold release column is only in contact with the surface of the resin and does not penetrate into the resin, the shallow groove is formed only on the surface thereof, and thus the depth thereof is much smaller than that of the positioning hole 12. Specifically, the diameter of the ejector pin 202 is much smaller than the diameter of the mold release column, so that the ejector pin 202 occupies as little area of the surface of the circuit substrate 30 as possible, and the boundary area is small, and a large contact force is formed when the mold release column with a larger thickness than the ejector pin 202 contacts the surface of the resin, thereby facilitating the resin to be released. Specifically, the depth of the die-release hole 13 is set to be generally 0.1mm to 0.7mm, for example, 0.3mm, the aperture of the die-release hole 13 is generally 2mm to 7mm, for example, 4mm, and the aperture of the positioning hole 12 is generally 0.2mm to 2mm, for example, 1.2 mm.

In some embodiments of the present invention, as shown in fig. 4, the semiconductor circuit further includes a plurality of bonding wires 70, the bonding wires 70 being connected between the plurality of electronic components 60, the circuit wiring layer 50, and the plurality of leads 80. For example, the bonding wire 70 may connect the electronic component 60 and the electronic component 60, may also connect the electronic component 60 and the circuit wiring layer 50, may also connect the electronic component 60 and the lead 80, and may also connect the circuit wiring layer 50 and the lead 80. The electronic components 60 are power devices such as IGBTs, freewheeling diodes, and driver chips mentioned in the above embodiments, and others such as resistors, capacitors, and the like. The bond wires 70 are typically gold wires, copper wires, hybrid gold and copper wires, 38um or thinner aluminum wires below 38um, 100um or thicker aluminum wires above 100 um.

In addition, the present invention also provides a method for manufacturing a semiconductor circuit, where the semiconductor circuit is the above-mentioned semiconductor circuit, as shown in fig. 6, the method comprising the steps of:

step S100, providing a circuit substrate 30, and preparing an insulating layer 40 on the surface of the circuit substrate 30;

step S200, preparing a circuit wiring layer 50 on the surface of the insulating layer 40;

step S300, preparing pins 80, wherein one ends of a plurality of pins 80 are connected with each other through connecting ribs;

step S400, disposing the electronic component 60 and the pin 80 in the circuit wiring layer 50;

step S500, electrically connecting the electronic component 60 and the circuit wiring layer 50 by a bonding wire 70;

step S600, performing injection molding on a circuit substrate 30 provided with an electronic component 60 and pins 80 through a packaging mold to form a packaging body 10, wherein the packaging body 10 covers a mounting surface of the circuit substrate 30 for mounting the electronic component 60, mounting holes 11 are formed at two ends of the packaging body 10, the surfaces of the mounting holes 11 are lower than the surface of the packaging body 10 and form countersunk holes, a positioning hole 12 with the bottom reaching the surface of the circuit substrate 30 and a demolding hole 13 which is arranged at a position close to the middle of the circuit substrate 30 relative to the positioning hole 12 are formed in the packaging body 10 on one side of the mounting surface of the circuit substrate 30, the depth of the demolding hole 13 is smaller than that of the positioning hole 12, the demolding hole 13 and the positioning hole 12 are both located at the periphery of the packaging body 10, and the circuit substrate 30 is exposed relative to the packaging body 10 at the bottom of the positioning hole 12;

the package 10 further covers the heat dissipation surface of the circuit board 30, and has a heat dissipation surface stepped portion 15 that is inwardly folded on the heat dissipation surface side, and the package 10 has a mounting surface stepped portion 16 that is symmetrical with the heat dissipation surface stepped portion 15 in cross section with respect to the thickness direction of the package 10. Therefore, in the package 10, the mounting-surface stepped portion 16 and the heat-dissipating-surface stepped portion 15 which are provided vertically symmetrically make the package 10 more beautiful and practical.

Step S700, cutting off connecting ribs among the pins 80 to form a semiconductor circuit to be tested, performing parameter test on the semiconductor circuit to be tested through test equipment, and bending and molding each pin 80 of the semiconductor circuit to be tested which is qualified according to the result of the parameter test and the preset shape of the pin 80 if the test is qualified, so as to obtain the qualified semiconductor circuit.

In step S100, the circuit substrate 30 with a suitable size can be designed according to the required circuit layout, for example, for a general semiconductor circuit, the size of the circuit substrate 30 can be selected to be 64mm × 30 mm. Taking the circuit substrate 30 as an aluminum substrate as an example, the aluminum substrate is formed by directly routing 1m × 1m aluminum, the routing knife uses high-speed steel as a material, the motor uses a rotating speed of 5000 rpm, and the routing knife is set at a right angle with the plane of the aluminum; or may be formed by stamping. And uneven textures can be formed on the back surface of the circuit substrate 30 by laser etching and polishing. Next, an insulating layer 40 is prepared on the surface of the circuit substrate 30, and the insulating layer 40 is used to put the circuit wiring layer 50 and the circuit substrate 30 in communication to cause a short circuit.

In step S200, a metal substrate such as copper foil may be laminated on the surface of the insulating layer 40, and then the surface of the metal substrate is processed, such as by etching the copper foil, and the copper foil is partially removed to form the circuit wiring layer 50. A plurality of element mounting sites are formed on the circuit wiring layer 50, and pads 51 are formed at portions of the circuit wiring layer 50 located on the first circuit substrate 30.

Further, a thin layer of green oil (not shown) may be disposed on the surface of the circuit wiring layer 50, and the green oil layer coats the surface of the circuit wiring layer 50 except for the component mounting locations and the pads 51, so as to prevent damage caused by transmission short circuit between the traces of the circuit wiring layer 50, and prevent oxidation and contamination of the surface of the circuit wiring layer 50, thereby protecting the circuit wiring layer.

In step S300, the lead 80 may be prepared from a copper substrate, for example, a strip with a length C of 25mm, a width K of 1.5mm and a thickness H of 1mm is prepared, and then a nickel layer is formed on the surface of the lead 80 by electroless plating: the nickel layer is formed on the surface of the copper material with a special shape by the mixed solution of nickel salt and sodium hypophosphite and adding a proper complexing agent, the metal nickel has strong passivation capability, a layer of extremely thin passivation film can be rapidly generated, and the corrosion of atmosphere, alkali and certain acid can be resisted. The nickel plating crystal is extremely fine, and the thickness of the nickel layer is generally 0.1 mu m; then, by an acid sulfate process, the copper material with the formed shape and the nickel layer is soaked in a plating solution with positive tin ions for electrifying at room temperature, a nickel-tin alloy layer is formed on the surface of the nickel layer, the thickness of the nickel layer is generally controlled to be 5 mu m, and the protection and the weldability are greatly improved by the formation of the nickel layer. In order to limit the spacing between the pins 80, the second ends of the pins 80 are pressed by a specific mold to form connecting ribs, so that the pins 80 can be rapidly mounted on the circuit substrate 30, and the preparation of the pins 80 is completed.

In step S400, the component mounting sites and the pads 51 of the circuit wiring of the circuit substrate 30 are first solder-paste-coated with a steel mesh, which can be used to a thickness of 0.13mm, by a solder-paste printer using the steel mesh, which is where solder-paste soldering is required, such as subsequent soldering of the electronic components 60 and the like at the component mounting sites. Or a silver paste dispenser, which applies a specific pattern with silver paste to the component mounting sites and the lands 51, by which soldering of the electronic components 60 at these sites can also be achieved.

Then, the electronic element 60 and the pin 80 are mounted, the electronic element 60 can be directly placed at an element mounting position, one end of the pin 80 is placed on the bonding pad 51, the other end of the pin 80 needs to be fixed by a carrier, the carrier is made of materials such as synthetic stone and stainless steel, and due to the connection effect of the reinforcing ribs, the pin 80 is conveniently fixed at the position of the bonding pad 51. Then, the circuit board 30 placed on the carrier is cured by reflow soldering, solder paste or silver paste, and the electronic component 60 and the lead 80 are solder-fixed to the component mounting site and the pad 51, respectively.

In step S500, the step is to connect the bonding wires 70 to route wires. One of the driving bonding pads of the driving chip traces in the electronic component 60 may be directly connected to the gate bonding region of the power device, such as the IGBT, through bonding wires 70, such as gold wires, copper wires, gold-copper hybrid wires, and thin aluminum wires below 38um or 38um, and the other driving bonding pads 51 of the driving chip traces may be directly connected to the pads 51 of the circuit wiring layer 50 through bonding wires 70, such as gold wires, copper wires, gold-copper hybrid wires, and thin aluminum wires below 38um or 38 um. The emitter bonding region of the IGBT is directly connected to the pad 51 of the circuit wiring layer 50 through a thick aluminum line of 100um or more.

In step S600, the step is a step of forming the package 10. Firstly, the circuit substrate 30 with the electronic element 60 and the pin 80 installed in the above steps can be baked in an oxygen-free environment, the baking time is not less than 2 hours, and the baking temperature can be selected to be 5 ℃. The circuit board 30 with the pins 80 arranged thereon is transferred to a package mold, and as shown in fig. 7, the package mold includes an upper mold 203 and a lower mold 204 which are vertically disposed, the pins 80 are fixedly disposed between the upper mold 203 and the lower mold 204, and the pins 80 fixed by welding to the circuit board 30 are brought into contact with a fixing device 205 provided on the lower mold 204 to position the circuit board 30. The top mold 203 is provided with a thimble 202, the free end of the thimble 202 abuts against the insulating layer 40 on the surface of the outer periphery of the circuit substrate 30, and the thimble 202 can be used for controlling the distance between the circuit substrate 30 and the lower mold 204 so as to realize the flat behavior of the bottoms of the circuit substrate 30 and the lower mold 204, the distance cannot be too far, otherwise, the heat dissipation performance is affected, the distance cannot be too close, otherwise, the situation of insufficient glue injection and the like can be caused. The diameter of the thimble 202 is preferably designed to be larger than the diameter of the contact point of the metal connector 18C by 0.1 mm.

Then, the package mold on which the circuit board 30 is placed is clamped, and the sealing resin is injected through the gate 201. The sealing method may employ transfer mold molding using thermosetting resin or injection mold molding using thermosetting resin. Also, the gas corresponding to the inside of the sealing resin cavity injected from the gate 201 is discharged to the outside through the exhaust port 206.

Specifically, for the packaging mold shown in fig. 7, the widths of the injection molding runners of the upper surface and the lower surface are different, and generally, the width of the runner of the upper surface is much larger than that of the runner of the lower surface.

Finally, demolding is carried out, specifically, the demolding column arranged on the lower mold 204 abuts against the surface of the dense resin, so that the sealing resin is separated from the inner surface of the lower mold 204, after demolding, the demolding column can penetrate into the surface of the sealing resin to form a groove when abutting against the surface of the dense resin, and the groove forms the demolding hole 13. When the upper mold 203 is removed, the thimble 202 is pulled out to form the positioning hole 12 in the sealing resin, and the thimble 202 abuts against the surface of the circuit board 30, so that the bottom of the positioning hole 12 is exposed from the circuit board 30. The sealing resin is thereafter cured to form the package 1012, and the free ends of the leads 80 are exposed from the package 1012.

In step S700, a connecting rib (not shown) connecting the other ends of the plurality of pins 80 is cut off to form a semiconductor circuit to be tested, wherein the connecting rib is a residue generated in the process of manufacturing the pins 80, and the connecting rib may cause a short circuit between the pins 80 and the pins 80, and therefore the connecting rib needs to be cut off in the process of manufacturing the semiconductor circuit. In one example, the connecting rib connecting the second ends of the plurality of pins 80 may be cut off by a specific device so that the other ends of the pins 80 are not connected to each other, so as to obtain the semiconductor circuit to be tested, so as to perform the parameter test on the semiconductor circuit to be tested in the next step.

The test equipment can be used for performing parameter test on the semiconductor circuit to be tested, for example, the test equipment can send a test signal to the semiconductor circuit to be tested and receive a feedback signal fed back by the semiconductor circuit to be tested; the test equipment processes the feedback signal to obtain corresponding feedback data, compares the feedback data with a preset threshold range, judges that the semiconductor circuit to be tested is qualified when the feedback data meet the preset threshold range, and then bends and molds each pin 80 of the semiconductor circuit to be tested which is qualified based on the shape of the preset pin 80, thereby obtaining the qualified semiconductor circuit.

Further, before the testing equipment can be used for carrying out parameter testing on the semiconductor circuit to be tested, laser marking can be carried out through the laser equipment so as to mark the surface of the packaging body 10 of the semiconductor circuit, and therefore identification and management of the semiconductor circuit product are facilitated.

In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

In the description of the present invention, it is to be understood that the terms "central," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the invention and to simplify the description, and are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed and operated in a particular orientation, and are therefore not to be considered limiting of the invention.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.

In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or they may be connected internally or in any other suitable relationship, unless expressly stated otherwise. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.

In the present invention, unless otherwise expressly stated or limited, the first feature "on" or "under" the second feature may be directly contacting the first and second features or indirectly contacting the first and second features through an intermediate. Also, a first feature "on," "over," and "above" a second feature may be directly or diagonally above the second feature, or may simply indicate that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature may be directly under or obliquely under the first feature, or may simply mean that the first feature is at a lesser elevation than the second feature.

Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.

Claims

1. A semiconductor circuit, comprising:

a circuit substrate (30), the circuit substrate (30) including a mounting surface and a heat dissipation surface;

an insulating layer (40), the insulating layer (40) being disposed on the mounting surface;

a circuit wiring layer (50), wherein the circuit wiring layer (50) is arranged on the surface of the insulating layer (40), and a plurality of preset mounting positions are arranged on the circuit wiring layer (50);

a plurality of electronic components (60) arranged on the predetermined mounting positions of the circuit wiring layer (50);

a plurality of pins (80), one ends of the plurality of pins (80) being electrically connected to the circuit wiring layer (50), respectively;

packaging body (10), packaging body (10) are used for covering and encapsulating semiconductor circuit can wrap up circuit substrate (30) a plurality of installation face electronic component (60), it is a plurality of the other end of pin (80) can be followed packaging body (10) exposes, and, packaging body (10) still wraps up circuit substrate (30) one side of radiating surface, packaging body (10) are in radiating surface one side is provided with radiating surface step portion (15), in order to increase the creepage distance of pin (80) and radiator (20).

2. The semiconductor circuit according to claim 1, wherein the heat dissipating surface step (15) is arranged to be tightened toward the center of the heat dissipating surface so as to form a protruding step in a "convex" shape on the surface of the heat dissipating surface.

3. The semiconductor circuit according to claim 1 or 2, wherein the package body (10) is provided with a stepped mounting-surface step portion (16) on the mounting-surface side, and the mounting-surface step portion (16) and the heat-dissipating-surface step portion (15) are symmetrically arranged on both sides of the package body (10).

4. The semiconductor circuit according to claim 3, wherein the package body (10) is further provided with a mounting hole (11), and the mounting hole (11) is a recessed countersunk hole and is disposed on two sides of the circuit substrate (30).

5. The semiconductor circuit according to claim 4, wherein the mounting hole (11) is disposed through a thickness direction of the package body (10), and the mounting hole (11) is radially communicated with the outside to form a gap at both ends of the package body (10).

6. The semiconductor circuit of claim 1, wherein the plurality of pins (80) comprises:

a plurality of first pins (801), wherein first ends of the plurality of first pins (801) are respectively electrically connected with the circuit wiring layer (50);

a plurality of second pins (802), wherein first ends of the second pins (802) are respectively electrically connected with the circuit wiring layer (50);

wherein the package body (10) wraps a circuit wiring layer (50) of each first pin (801) and each second pin (802);

the second end of each first pin (801) is led out from the first side face of the packaging body (10) respectively, and first lead-out parts corresponding to each other one by one are formed on the first side face of the packaging body (10); the second end of each second pin (802) is led out from the first side surface of the packaging body (10) respectively, and second lead-out parts which correspond to each other one by one are formed on the first side surface of the packaging body (10); a first side face of the packaging body (10) is provided with a plurality of creepage grooves (14), and the creepage grooves (14) are located between the adjacent first lead-out portion and the second lead-out portion.

7. The semiconductor circuit according to claim 1, further comprising a layer of green oil which avoids the electronic component (60) and the pin (80) and is provided on a surface of the circuit wiring layer (50).

8. The semiconductor circuit according to claim 1, wherein the package body (10) is provided with a positioning hole (12) and a mold release hole (13) on a mounting surface side of the circuit substrate (30),

the positioning hole (12) is penetratingly arranged in the thickness direction of the packaging body (10) and reaches the surface of the circuit substrate (30), so that the surface of the circuit substrate (30) is exposed outwards from the bottom of the positioning hole (12);

the demolding hole (13) is in a blind hole shape, the demolding hole (13) and the positioning hole (12) are both arranged on the periphery of the packaging body (10), and the positioning hole (12) is arranged in a position which is deviated from the center of the packaging body (10) relative to the demolding hole (13).

9. The semiconductor circuit of claim 1, further comprising a plurality of bond wires (70), the bond wires (70) connected between the plurality of electronic components (60), the circuit wiring layer (50), and the plurality of pins (80).

10. A method for manufacturing a semiconductor circuit according to any one of claims 1 to 9, the method comprising:

providing a circuit substrate (30) comprising a mounting surface and a heat dissipation surface;

preparing an insulating layer (40) and a circuit wiring layer (50) on the mounting surface of the circuit substrate (30) in sequence;

preparing pins (80), wherein one ends of a plurality of pins (80) are connected with each other through a connecting rib;

arranging an electronic component (60) and a pin (80) on the circuit wiring layer (50);

electrically connecting the electronic component (60) and the circuit wiring layer (50) by a bonding wire (70);

performing injection molding on the circuit substrate (30) provided with the electronic element (60) and the pins (80) through a packaging mold to form a packaging body (10), wherein the packaging body (10) covers a mounting surface of the circuit substrate (30) for mounting the electronic element (60), assembling holes (11) are formed at two ends of the packaging body (10), the surfaces of the assembling holes (11) are lower than the surface of the packaging body (10) and form countersunk holes, a positioning hole (12) with the bottom reaching the surface of the circuit substrate (30) and a demolding hole (13) which is closer to the middle part of the circuit substrate (30) relative to the positioning hole (12) are arranged at one side of the mounting surface of the circuit substrate (30), and the depth of the demolding hole (13) is smaller than the depth of the positioning hole (12), the demolding hole (13) and the positioning hole (12) are arranged at the peripheral part of the packaging body (10), and the circuit substrate (30) is exposed relative to the packaging body (10) at the bottom of the positioning hole (12);

the package (10) further covers the heat dissipation surface of the circuit board (30), and forms a heat dissipation surface stepped part (15) which is retracted inward on one side of the heat dissipation surface, and the package (10) forms a mounting surface stepped part (16) which is symmetrical to the heat dissipation surface stepped part (15) in cross section relative to the thickness direction of the package (10);

and cutting off the connecting ribs among the pins (80) to form a semiconductor circuit to be tested, performing parameter test on the semiconductor circuit to be tested through test equipment, and bending and molding each pin (80) of the semiconductor circuit to be tested which is qualified in test based on a preset pin shape if the test is qualified according to the result of the parameter test to obtain the qualified semiconductor circuit.