CN216213385U - Semiconductor circuit having a plurality of transistors - Google Patents

Abstract

The present invention relates to a semiconductor circuit including a circuit substrate, a circuit wiring layer, an insulating layer, a plurality of electronic components, a plurality of pins, and a sealing layer. The circuit substrate comprises a mounting surface and a radiating surface, the circuit wiring layer is provided with a plurality of preset mounting positions, the sealing layer is used for covering the sealed semiconductor circuit and at least wraps one side of the mounting surface of the circuit substrate, the other ends of the pins can be exposed out of the sealing layer, assembling holes penetrating through the thickness direction of the sealing layer are formed in the two ends of the sealing layer, a protruding portion along the periphery of the assembling holes is formed in the upper surface of the sealing layer, and the protruding portion is used for receiving and limiting a fastener mounted in the assembling holes. The semiconductor circuit of this application adds the bellying of integrated into one piece, and technology is more simple, and has thickened the empty material of sealing layer assembly thick correspondingly to can reduce the problem emergence that leads to the sealing layer fracture because of fastener moment of torsion increase.

Description

Semiconductor circuit having a plurality of transistors

Technical Field

The utility model relates to a semiconductor circuit, and belongs to the technical field of semiconductor circuit application.

Background

The semiconductor circuit is a Modular Intelligent Power System (MIPS), which not only integrates a Power switch device and a driving circuit, but also has a fault detection circuit for overvoltage, overcurrent, overheat, etc. built in, and can send the detection signal to a CPU or a DSP for interrupt processing. A semiconductor circuit is a power-driven type product that combines power electronics and integrated circuit technology. The surface of the semiconductor circuit is usually covered with a sealing layer formed by injection molding of a resin material, the sealing layer seals a circuit board, an electronic component, and the like inside the semiconductor circuit, and the leads protrude from one side or both sides of the sealing layer. Wherein, the both ends of sealing layer are provided with the pilot hole that is used for fixing usually, and present pilot hole design is more complicated, needs independent process, and takes place the phenomenon of breaing the sealing layer easily when the screw is beaten to pilot hole department, leads to influencing the production efficiency and the product quality of whole product.

SUMMERY OF THE UTILITY MODEL

Based on the technical problems to be solved by the utility model are the low production efficiency and the low product quality of the semiconductor circuit.

Specifically, the present invention discloses a semiconductor circuit comprising:

a circuit substrate including a mounting surface and a heat dissipation surface;

an insulating layer disposed on the mounting surface;

the circuit wiring layer is arranged on the surface of the insulating layer and provided with a plurality of preset mounting positions;

a plurality of electronic components configured on the preset mounting positions of the circuit wiring layer;

the pins are electrically connected with the circuit wiring layer at one ends respectively;

the sealing layer is used for covering and sealing the semiconductor circuit, and at least wraps up and sets the circuit substrate the installation face one side, it is a plurality of the other end of pin can be followed the sealing layer exposes, the both ends of sealing layer are provided with and run through the pilot hole of the thickness direction of sealing layer, the upper surface of sealing layer is formed with and follows the peripheral bellying of pilot hole, the bellying is used for accepting with spacing installation in the fastener in the pilot hole.

Optionally, the projection is formed on an upper surface of the sealing layer and provided as a plurality of spaced-apart bumps arranged along a periphery of the fitting hole.

Optionally, the height of the protrusion is 0.5mm to 2 mm.

Optionally, the assembly holes communicate radially outward to form notches at both ends of the seal layer.

Optionally, the cross section of the assembly hole is U-shaped.

Optionally, on the mounting surface side of the circuit substrate, the sealing layer is provided with a positioning hole penetrating through the thickness direction of the sealing layer and reaching the surface of the circuit substrate, so that the surface of the circuit substrate is exposed outwards from the bottom of the positioning hole.

Optionally, on the mounting surface side of the circuit substrate, the sealing layer is further provided with a blind hole-shaped demolding hole, the demolding hole and the positioning hole are arranged on the outer periphery of the sealing layer, and the demolding hole is arranged offset from the center of the sealing layer relative to the positioning hole.

Optionally, the semiconductor circuit further comprises a plurality of bonding wires connected between the plurality of electronic elements, the circuit wiring layer and the plurality of pins.

The semiconductor circuit of the present invention includes a circuit substrate, a circuit wiring layer, an insulating layer, a plurality of electronic components, a plurality of pins, and a sealing layer. The circuit substrate comprises a mounting surface and a radiating surface, the insulating layer is arranged on the mounting surface, the circuit wiring layer is arranged on the surface of the insulating layer, the circuit wiring layer is provided with a plurality of element mounting positions and a bonding pad, a plurality of electronic elements are arranged on the element mounting positions of the circuit wiring layer, a plurality of pins are arranged on at least one side of the circuit substrate, the sealing layer is used for covering and sealing a semiconductor circuit, at least one side of the mounting surface of the circuit substrate is wrapped and arranged, the other ends of the pins can be exposed out of the sealing layer, assembling holes penetrating through the thickness direction of the sealing layer are formed in the two ends of the sealing layer, a protruding portion along the periphery of the assembling holes is formed on the upper surface of the sealing layer, and the protruding portion is used for bearing and limiting a fastener arranged in the assembling holes. The semiconductor circuit of this application adds the bellying of integrated into one piece, and technology is more simple, and has thickened the empty material of sealing layer assembly thick correspondingly to can reduce the problem emergence that leads to the sealing layer fracture because of fastener moment of torsion increase.

Drawings

FIG. 1 is a perspective view of a semiconductor circuit according to one embodiment of the present invention;

FIG. 2 is a top view of the semiconductor circuit of FIG. 1;

FIG. 3 is a perspective view of a semiconductor circuit in accordance with another embodiment of the present invention;

FIG. 4 is a cross-sectional view in the direction A-A of the semiconductor circuit of FIG. 2;

FIG. 5 is a cross-sectional view in the direction B-B of the semiconductor circuit of FIG. 2;

FIG. 6 is a perspective view of a semiconductor circuit with a heat sink mounted thereon in accordance with one embodiment of the present invention;

FIG. 7 is a flow chart of a method of fabricating a semiconductor circuit in accordance with one embodiment of the present invention;

fig. 8 is a schematic diagram of a semiconductor circuit according to an embodiment of the present invention, prepared to form an encapsulation layer during the fabrication thereof.

Reference numerals:

the sealing layer 10, the assembly hole 11, the positioning hole 12, the mold release hole 13, the bump 14, the heat sink 20, the circuit substrate 30, the insulating layer 40, the circuit wiring layer 50, the pad 51, the electronic component 60, the bonding wire 70, the pin 80, the fastener 90, the gate 201, the ejector pin 202, the upper mold 203, the lower mold 204, the fixing device 205, and the exhaust port 206.

Detailed Description

It is to be noted that the embodiments and features of the embodiments may be combined with each other without conflict in structure or function. The present invention will be described in detail below with reference to examples.

The semiconductor circuit provided by the utility model is a circuit module which integrates a power switch device, a high-voltage driving circuit and the like and seals and encapsulates the surface of the power switch device and the high-voltage driving circuit. The method is widely applied to the field of power electronics, such as frequency converters of driving motors, various inverter voltages, variable frequency speed regulation, metallurgical machinery, electric traction, variable frequency household appliances and the like. The semiconductor circuit herein may be referred to by various other names, such as Modular Intelligent Power System (MIPS), Intelligent Power Module (IPM), or hybrid integrated circuit, Power semiconductor Module, Power Module, etc.

As shown in fig. 1 to 5, the semiconductor circuit according to the present invention includes a circuit substrate 30, a circuit wiring layer 50, an insulating layer 40, a plurality of electronic components 60, a plurality of leads 80, and a sealing layer 10. The circuit board 30 comprises a mounting surface and a heat dissipation surface, the insulating layer 40 is arranged on the mounting surface, the circuit wiring layer 50 is arranged on the surface of the insulating layer 40, the circuit wiring layer 50 is provided with a plurality of preset mounting positions and a bonding pad 51, a plurality of electronic elements 60 are arranged on the preset mounting positions of the circuit wiring layer 50, a plurality of pins 80 are arranged on at least one side of the circuit board 30, the sealing layer 10 is used for covering and sealing a semiconductor circuit and at least wraps one side of the mounting surface of the circuit board 30, the other ends of the pins 80 can be exposed out of the sealing layer 10, assembling holes 11 penetrating through the sealing layer in the thickness direction are formed in two ends of the sealing layer 10, a protruding portion 14 along the periphery of the assembling holes 11 is formed in the upper surface of the sealing layer 10, and the protruding portion 14 is used for receiving and limiting fasteners installed in the assembling holes 11.

It can be seen that, the integrated into one piece's bellying 14 has been set up in the semiconductor circuit of this application, and technology is simpler, is favorable to promoting work efficiency, and bellying 14 is along with the injection moulding of sealing layer 10, has thickened the empty material of sealing layer 10 assembly correspondingly thickly for the intensity of pilot hole 11 increases, thereby can reduce and lead to the problem emergence of sealing layer 10 fracture because of the increase of fastener moment of torsion.

The circuit substrate 30 is used for carrying electronic components 60 in a semiconductor circuit, and includes a mounting surface on a front surface and a heat dissipation surface on a back surface. The circuit substrate 30 may be made of a metal material, such as a rectangular plate made of aluminum of 1100, 5052, etc., and the thickness of the rectangular plate is much thicker than other layers, generally 0.8mm to 2mm, and the common thickness is 1.5mm, so as to mainly achieve the heat conduction and heat dissipation effects on electronic components such as power devices, etc. For another example, the circuit board 30 may be made of other metal materials with good thermal conductivity, for example, a rectangular plate made of copper. The shape of the circuit board 30 of the present invention is not limited to a rectangular shape, and may be a circular shape, a trapezoidal shape, or the like. The heat dissipation surface of the circuit substrate 30 may be textured by laser etching or grinding (not shown) to enhance the bonding force with the middle sealing layer 10. The insulating layer 40 is disposed on the mounting surface of the circuit board 30, and the thickness of the insulating layer is thinner than that of the circuit board 30, generally 50um to 150um, and usually 110 um. The insulating layer 40 may be made of a resin material such as epoxy resin, and a filler such as alumina and aluminum carbide may be filled inside the resin material to improve thermal conductivity. In order to improve the thermal conductivity, the shape of these fillers may be angular, and in order to avoid the risk of the fillers damaging the contact surface of the electronic component 60 provided on the surface thereof, the fillers may be spherical, angular, or a mixture of angular and spherical.

The circuit wiring layer 50 may be formed by etching a copper foil provided on the surface of the insulating layer 40, or may be formed by printing a paste-like conductive medium, which may be a conductive material such as graphene, solder paste, or silver paste. The thickness of the circuit wiring layer 50 is substantially equivalent to that of the insulating layer 40, and is relatively thin, for example, about 70 um. The surface of the circuit wiring layer 50 is provided with a plurality of preset mounting positions for mounting a plurality of electronic components 60, each electronic component 60 includes a power device and a driving chip, wherein the power device includes a switching tube such as an IGBT (Insulated Gate Bipolar Transistor) or a MOS (metal oxide semiconductor) and a freewheeling diode, and the power consumed by the operation of the power device is large and the amount of heat generated is large, so that the temperature of the whole semiconductor circuit is higher than the room temperature in the operation process. The electronic component 60 also includes passive devices such as resistors, capacitors, and the like. For the power device with very large calorific value, the power device is fixedly arranged at a preset mounting position through a metal radiating fin. The circuit wiring layer 50 and the plurality of electronic components 60 mounted on the circuit wiring layer 50 constitute the entire circuit of the semiconductor circuit.

The periphery of the surface of the circuit wiring layer 50 is also provided with a plurality of pads 51 to fix the pins 80, thereby transmitting signals to the internal circuit of the semiconductor circuit. The lead 80 is generally made of a metal such as copper, a nickel-tin alloy layer is formed on the surface of the copper by chemical plating and electroplating, the thickness of the alloy layer is generally 5 μm, and the copper can be protected from corrosion and oxidation by the plating layer and the solderability can be improved.

The lead 80 can be made of C194(-1/2H) plates (chemical components: Cu (97.0), Fe (2.4), P (0.03) and Zn (0.12)) or KFC (-1/2H) plates (chemical components: Cu (99.6), Fe (0.1-0.05) and P (0.03, 0.025-0.04)), the C194 or KFC plates with the thickness of 0.5mm are processed by a stamping or etching process, nickel plating thickness is 0.1-0.5um firstly, and tin plating thickness is 2-5um secondly; the excess connecting ribs of the pins 80 are cut and shaped into the desired shape by a special device.

Further, a thin layer of green oil (not shown) is disposed on the surface of the circuit wiring layer 50 where the predetermined mounting locations and the pads 51 are not disposed, and serves to prevent short circuits between the traces of the circuit wiring layer 50 and also to prevent oxidation and contamination of the surface of the circuit wiring layer 50, thereby protecting the circuit wiring layer.

Compared with the prior art that the design of the assembly hole 11 is complex, and an independent process is needed in the process of a mould program, the assembly hole 11 and the sealing layer 10 are integrally formed, so that the design and the forming of the assembly hole 11 only need to be completed synchronously with the program process of the sealing layer 10 body, the production process is effectively simplified, and the production efficiency of products is improved. Specifically, during the preparation process of the sealing layer 10 and the assembling holes 11, the circuit wiring layer 50 electrically connected with the plurality of pins 80 and the plurality of electronic components 60 can be plastically packaged in the sealing layer 10 by a plastic package mold through a plastic package process. The material of the sealing layer 10 may be thermosetting polymer such as epoxy resin, phenolic resin, silica gel, amino group, unsaturated resin; in order to improve heat dissipation, the sealing layer 10 may be a composite material containing powder or fiber of metal, ceramic, silicon oxide, graphene, or the like. In one example, the sealing layer 10 may be made of a molding compound prepared by mixing an epoxy resin as a matrix resin, a high-performance phenolic resin as a curing agent, silica powder and the like as fillers, and a plurality of additives.

Specifically, the shape of the protruding portion 11 may be various, and it is usually required to protrude from the surface of the sealing layer 10, and the top end of the protruding portion 14 has a bearing surface, and can be used for receiving and limiting the fastener installed in the assembling hole 11.

In some embodiments of the present invention, as shown in fig. 1, 2 and 4, the protruding portion 14 may be in the shape of a boss, which has a simple structure, and the forming mold is relatively simple, thereby facilitating production and manufacturing.

In some embodiments of the present invention, as shown in fig. 3, the protruding portion 14 may be further configured as a plurality of spaced protruding points arranged along the periphery of the assembly hole, and the protruding points may be understood as protruding hulls, and the top surfaces of the plurality of protruding hulls can be arranged in a structure having a certain bearing surface, so that the plurality of protruding hulls occupy less molding material, the molding mold is not complicated, and the production cost is low.

Further, in some embodiments of the present invention, optionally, the height of the protrusion 14 is 0.5mm to 2 mm. E.g., 0.5mm, 1mm, 1.2mm, 2mm, etc. Also, the protrusion 14 may be selected to have a suitable protrusion height depending on the actual production application.

In some embodiments of the utility model, as shown in fig. 1-3, the assembly holes 11 communicate radially outward to form notches at both ends of the seal layer 10. Thus, in the semiconductor circuit of the present invention, the circuit substrate 30 may be a rectangular plate-shaped structure, and the sealing layer 10 is formed on both sides of the circuit substrate 30 in a wrapping manner when the sealing layer 10 is injection molded, and the mounting holes 11 communicating radially outward are formed. This not only facilitates manufacture, but also facilitates installation and securement of the fastener.

Further, the cross-section of the fitting hole 11 may be selected to be U-shaped. It should be noted that the cross section described here is a parallel plane with respect to the surface of the circuit substrate 30, and it is understood that the cross section of the mounting hole 11 is the cross section of the boss 14. Compared with the cross section of a bell mouth, the U-shaped cross section is more beneficial to the fastening installation of the fastener.

With continued reference to fig. 1 to 3, on the mounting surface side of the circuit substrate 3, the sealing layer 10 is provided with positioning holes 12 penetrating through the thickness direction thereof and reaching the surface of the circuit substrate 30, so that the surface of the circuit substrate 30 is exposed outward from the bottoms of the positioning holes 12. The positioning hole 12 is formed by positioning the thimble 202 mounted on the mold for packaging on the surface of the circuit substrate 30 when the sealing layer 10 is formed. According to different design requirements, plastic package molds with different shapes can be designed, and then the sealing bodies 10 with different shapes and structures can be obtained through plastic package. For example, the circuit substrate 30, the circuit wiring layer 50, the electronic components 60 and the pins 80 are wrapped by an injection molding method using a thermoplastic resin or a transfer molding method using a thermosetting resin to protect them, in this process, the free end of the ejector pin 202 of the mold abuts against the surface of the circuit substrate 30 to position the circuit substrate 30 accurately, and then after the resin heated to a liquid state is injected into the cavity of the mold, the mold is removed and the ejector pin 202 is pulled out, and after the resin is hardened, the positioning hole 12 is formed at the position where the ejector pin 202 is pulled out from the resin. Since the ejector pins 202 are abutted against the surface of the circuit substrate 30, the bottom of the positioning holes 12 are exposed from the circuit substrate 30. The surface of the circuit substrate 30 exposed here may also be covered with the insulating layer 40, so that the surface of the metal layer of the circuit substrate 30 is not exposed, thereby ensuring proper insulating properties of the circuit substrate 30.

Further, regardless of the shape of the circuit board 30, in the semiconductor circuit of the present invention, the positioning hole 12 is optionally provided in the outer peripheral portion of the circuit board 30, and the circuit wiring layer 50 is not provided at the position of the positioning hole 12. This is because the circuit wiring layer 50 is not provided in a small area of the outer peripheral portion of the circuit substrate 30 to form a boundary. Typically, in manufacturing the circuit substrate 30, a plurality of circuit substrates 30 are disposed on a single piece of metal substrate, and boundary regions are disposed between each circuit substrate 30 to facilitate cutting by mechanical equipment at these boundary regions to separate each individual circuit substrate 30. In the formation process of the sealing layer 10, the ejector pins 202 of the mold will abut against these boundary regions, and once the ejector pins 202 abut against the circuit wiring layer 50 region, the tips of the ejector pins 202 will contact the surface of the circuit wiring layer 50 or the surface of the electronic element 60, which may damage the circuit wiring layer 50 or damage the electronic element 60, so that the circuit wiring layer 50 cannot be disposed on the circuit substrate 30 corresponding to the tips of the ejector pins 202. If the thimble 202 does not abut against the outer edge area of the circuit substrate 30, a blank area without wires needs to be reserved in one way in the area where the circuit wiring layer 50 is located to serve as a position where the thimble 202 abuts against, which occupies the use area of the circuit wiring layer 50, and causes the area of the whole circuit substrate 30 to be too large, thereby causing waste and being inconvenient for miniaturization design. In the semiconductor circuit of the present invention, the thimble 202 abuts against the boundary region where the outer periphery of the circuit substrate 30 is located, and does not occupy the region of the circuit wiring layer 50, thereby improving the effective area utilization rate of the circuit wiring layer 50. Further, by observing the state of the circuit substrate 30 at the bottom of the positioning hole 12, it can be confirmed whether the position of the circuit substrate 30 in the sealing layer 10 is up to standard, that is, whether the circuit substrate 30 moves when being set in the mold cavity in the process of forming the sealing layer 10. If the circuit substrate 30 moves horizontally, so that the position where the thimble 202 abuts enters the area where the circuit wiring layer 50 is located, part or all of the circuit wiring layer 50 is exposed from the bottom of the positioning hole 12; or if the circuit substrate 30 moves vertically, the position of the ejector pin 202 may not be able to abut against the surface of the circuit substrate 30, so that the bottom of the positioning hole 12 does not expose the circuit substrate 30. Therefore, only the bottom of the positioning hole 12 exposes the surface of the circuit wiring layer 50, specifically, exposes the surface of the insulating layer 40 covered by the circuit wiring layer 50, and the position of the circuit substrate 30 in the sealing layer 10 can be determined to be qualified, so that the quality inspection efficiency of the whole semiconductor circuit can be improved.

The sealing layer 10 has two kinds of package structures. One is that the sealing layer 10 covers both sides of the circuit substrate 30, i.e. the mounting surface and the heat dissipation surface, specifically, the side on which the electronic component 60 is mounted and the heat dissipation surface of the circuit substrate 30, which are disposed on the circuit substrate 30, are covered, and at the same time, the sealing layer 10 also covers a part of the length of the end of the pin 80 connected to the circuit substrate 30, and this kind of package is a full-covering mode of the sealing layer 10; in another packaging method, the sealing layer 10 covers only the upper surface of the circuit substrate 30, i.e. the mounting surface of the circuit substrate 30 and the electronic element 60, and the sealing layer 10 also covers a part of the length of the end of the lead 80 connected to the circuit substrate 30, and the back surface of the circuit substrate 30, i.e. the heat dissipation surface, is exposed out of the sealing layer 10, thereby forming a half-packaging method of the sealing layer 10. In the full-coating mode, when the back surface of the circuit substrate 30 is provided with the texture, the bonding strength between the circuit substrate and the sealing layer 10 can be effectively enhanced, so that the circuit substrate and the sealing layer are not easy to separate. In contrast, in the half-clad method, the back surface of the circuit board 30 may not be provided with any texture, and when the semiconductor circuit is mounted, as shown in fig. 6, the back surface of the circuit board 30 may be further provided with a heat sink 20, and the surface of the heat sink 20 is in close contact with the surface of the circuit board 30, so that heat generated by the circuit board 30 is better dissipated by the heat sink 20.

In some embodiments of the present invention, as shown in fig. 1 to 3, the sealing layer 10 is further provided with a blind hole-shaped mold release hole 13 on the mounting surface side of the circuit substrate 30, the mold release hole 13 and the positioning hole 12 are both provided on the outer peripheral portion of the sealing layer 10, and the mold release hole 13 is provided further away from the center position of the sealing layer 10 with respect to the positioning hole 12. Further, the depth of the knockout hole 13 is optionally smaller than the depth of the positioning hole 12. This is because the mold release hole 13 is generated when the sealing layer 10 is formed. Usually, a protruded stripping column is further disposed in the cavity of the mold, and when the mold is removed after the resin heated to liquid state is injected into the cavity of the mold, the stripping column abuts against the surface of the resin, so that the molded resin is separated from the cavity of the mold, and the sealing layer 10 is formed after the resin is hardened. When the demoulding column is pressed against the surface of the resin, the demoulding column can penetrate into the surface of the resin to form a groove, and when the resin is separated from the mould cavity, the groove forms a blind hole-shaped demoulding hole 13. Since the mold release column is only in contact with the surface of the resin and does not penetrate into the resin, the shallow groove is formed only on the surface thereof, and thus the depth thereof is much smaller than that of the positioning hole 12. Specifically, the diameter of the ejector pin 202 is much smaller than the diameter of the mold release column, so that the ejector pin 202 occupies as little area of the surface of the circuit substrate 30 as possible, and the boundary area is small, and a large contact force is formed when the mold release column with a larger thickness than the ejector pin 202 contacts the surface of the resin, thereby facilitating the resin to be released. Specifically, the depth of the die-release hole 13 is set to be generally 0.1mm to 0.7mm, for example, 0.3mm, the aperture of the die-release hole 13 is generally 2mm to 7mm, for example, 4mm, and the aperture of the positioning hole 12 is generally 0.2mm to 2mm, for example, 1.2 mm.

In some embodiments of the present invention, as shown in fig. 4, the semiconductor circuit further includes a plurality of bonding wires 70, the bonding wires 70 being connected between the plurality of electronic components 60, the circuit wiring layer 50, and the plurality of leads 80. For example, the bonding wire 70 may connect the electronic component 60 and the electronic component 60, may also connect the electronic component 60 and the circuit wiring layer 50, may also connect the electronic component 60 and the lead 80, and may also connect the circuit wiring layer 50 and the lead 80. The electronic components 60 are power devices such as IGBTs, freewheeling diodes, and driver chips mentioned in the above embodiments, and others such as resistors, capacitors, and the like. The bond wires 70 are typically gold wires, copper wires, hybrid gold and copper wires, 38um or thinner aluminum wires below 38um, 100um or thicker aluminum wires above 100 um.

In addition, the present invention also provides a method for manufacturing a semiconductor circuit, where the semiconductor circuit is the above-mentioned semiconductor circuit, as shown in fig. 7, the method comprising the steps of:

step S100, providing a circuit substrate 30, and preparing an insulating layer 40 on the surface of the circuit substrate 30;

step S200, preparing a circuit wiring layer 50 on the surface of the insulating layer 40;

step S300, preparing pins 80, wherein one ends of a plurality of pins 80 are connected with each other through connecting ribs;

step S400, disposing the electronic component 60 and the pin 80 in the circuit wiring layer 50;

step S500, electrically connecting the electronic component 60 and the circuit wiring layer 50 by a bonding wire 70;

step S600, performing injection molding on the circuit substrate 30 provided with the electronic component 60 and the pins 80 through a packaging mold to form a sealing layer 10, wherein the sealing layer 10 covers one surface of the circuit substrate 30, on which the electronic component 60 is mounted, the two ends of the sealing layer 10 are provided with assembly holes 11, a protruding part 14 is formed on the sealing layer 10, on which the upper surfaces of the assembly holes 11 are located, the sealing layer 10 is provided with a positioning hole 12 penetrating through the thickness direction of the sealing layer 10 and reaching the surface of the circuit substrate 30, the sealing layer 10 is further provided with a blind-hole-shaped demolding hole 13, and the depth of the demolding hole 13 is smaller than that of the positioning hole 12;

step S700, cutting off connecting ribs among the pins 80 to form a semiconductor circuit to be tested, performing parameter test on the semiconductor circuit to be tested through test equipment, and bending and molding each pin 80 of the semiconductor circuit to be tested which is qualified according to the result of the parameter test and the preset shape of the pin 80 if the test is qualified, so as to obtain the qualified semiconductor circuit.

In step S100, the circuit substrate 30 with a suitable size can be designed according to the required circuit layout, for example, for a general semiconductor circuit, the size of the circuit substrate 30 can be selected to be 64mm × 30 mm. Taking the circuit substrate 30 as an aluminum substrate as an example, the aluminum substrate is formed by directly routing 1m × 1m aluminum, the routing knife uses high-speed steel as a material, the motor uses a rotating speed of 5000 rpm, and the routing knife is set at a right angle with the plane of the aluminum; or may be formed by stamping. And uneven textures can be formed on the back surface of the circuit substrate 30 by laser etching and polishing. Next, an insulating layer 40 is prepared on the surface of the circuit substrate 30, and the insulating layer 40 is used to put the circuit wiring layer 50 and the circuit substrate 30 in communication to cause a short circuit.

In step S200, a metal substrate such as copper foil may be laminated on the surface of the insulating layer 40, and then the surface of the metal substrate is processed, such as by etching the copper foil, and the copper foil is partially removed to form the circuit wiring layer 50. A plurality of element mounting sites are formed on the circuit wiring layer 50, and pads 51 are formed at portions of the circuit wiring layer 50 located on the first circuit substrate 30.

Further, a thin layer of green oil (not shown) may be disposed on the surface of the circuit wiring layer 50, and the green oil layer coats the surface of the circuit wiring layer 50 except for the component mounting locations and the pads 51, so as to prevent damage caused by transmission short circuit between the traces of the circuit wiring layer 50, and prevent oxidation and contamination of the surface of the circuit wiring layer 50, thereby protecting the circuit wiring layer.

In step S300, the lead 80 may be prepared from a copper substrate, for example, a strip with a length C of 25mm, a width K of 1.5mm and a thickness H of 1mm is prepared, and then a nickel layer is formed on the surface of the lead 80 by electroless plating: the nickel layer is formed on the surface of the copper material with a special shape by the mixed solution of nickel salt and sodium hypophosphite and adding a proper complexing agent, the metal nickel has strong passivation capability, a layer of extremely thin passivation film can be rapidly generated, and the corrosion of atmosphere, alkali and certain acid can be resisted. The nickel plating crystal is extremely fine, and the thickness of the nickel layer is generally 0.1 mu m; then, by an acid sulfate process, the copper material with the formed shape and the nickel layer is soaked in a plating solution with positive tin ions for electrifying at room temperature, a nickel-tin alloy layer is formed on the surface of the nickel layer, the thickness of the nickel layer is generally controlled to be 5 mu m, and the protection and the weldability are greatly improved by the formation of the nickel layer. In order to limit the spacing between the pins 80, the second ends of the pins 80 are pressed by a specific mold to form connecting ribs, so that the pins 80 can be rapidly mounted on the circuit substrate 30, and the preparation of the pins 80 is completed.

In step S400, the component mounting sites and the pads 51 of the circuit wiring of the circuit substrate 30 are first solder-paste-coated with a steel mesh, which can be used to a thickness of 0.13mm, by a solder-paste printer using the steel mesh, which is where solder-paste soldering is required, such as subsequent soldering of the electronic components 60 and the like at the component mounting sites. Or a silver paste dispenser, which applies a specific pattern with silver paste to the component mounting sites and the lands 51, by which soldering of the electronic components 60 at these sites can also be achieved.

Then, the electronic element 60 and the pin 80 are mounted, the electronic element 60 can be directly placed at an element mounting position, one end of the pin 80 is placed on the bonding pad 51, the other end of the pin 80 needs to be fixed by a carrier, the carrier is made of materials such as synthetic stone and stainless steel, and due to the connection effect of the reinforcing ribs, the pin 80 is conveniently fixed at the position of the bonding pad 51. Then, the circuit board 30 placed on the carrier is cured by reflow soldering, solder paste or silver paste, and the electronic component 60 and the lead 80 are solder-fixed to the component mounting site and the pad 51, respectively.

In step S500, the step is to connect the bonding wires 70 to route wires. One of the driving bonding pads of the driving chip traces in the electronic component 60 may be directly connected to the gate bonding region of the power device, such as the IGBT, through bonding wires 70, such as gold wires, copper wires, gold-copper hybrid wires, and thin aluminum wires below 38um or 38um, and the other driving bonding pads 51 of the driving chip traces may be directly connected to the pads 51 of the circuit wiring layer 50 through bonding wires 70, such as gold wires, copper wires, gold-copper hybrid wires, and thin aluminum wires below 38um or 38 um. The emitter bonding region of the IGBT is directly connected to the pad 51 of the circuit wiring layer 50 through a thick aluminum line of 100um or more.

In step S600, this step is a step of forming the sealing layer 10. Firstly, the circuit substrate 30 with the electronic element 60 and the pin 80 installed in the above steps can be baked in an oxygen-free environment, the baking time is not less than 2 hours, and the baking temperature can be selected to be 5 ℃. The circuit board 30 with the pins 80 arranged thereon is transferred to a package mold, and as shown in fig. 8, the package mold includes an upper mold 203 and a lower mold 204 which are vertically disposed, the pins 80 are fixedly disposed between the upper mold 203 and the lower mold 204, and the pins 80 fixed by welding to the circuit board 30 are brought into contact with a fixing device 205 provided on the lower mold 204 to position the circuit board 30. The top mold 203 is provided with a thimble 202, the free end of the thimble 202 abuts against the insulating layer 40 on the surface of the outer periphery of the circuit substrate 30, and the thimble 202 can be used for controlling the distance between the circuit substrate 30 and the lower mold 204 so as to realize the flat behavior of the bottoms of the circuit substrate 30 and the lower mold 204, the distance cannot be too far, otherwise, the heat dissipation performance is affected, the distance cannot be too close, otherwise, the situation of insufficient glue injection and the like can be caused. The diameter of the thimble 202 is preferably designed to be larger than the diameter of the contact point of the metal connector 18C by 0.1 mm.

Then, the package mold on which the circuit board 30 is placed is clamped, and the sealing resin is injected through the gate 201. The sealing method may employ transfer mold molding using thermosetting resin or injection mold molding using thermosetting resin. Also, the gas corresponding to the inside of the sealing resin cavity injected from the gate 201 is discharged to the outside through the exhaust port 206.

Specifically, for the packaging mold shown in fig. 8, the widths of the injection molding runners of the upper surface and the lower surface are not the same, and generally, the width of the runner of the upper surface is much larger than that of the runner of the lower surface.

Finally, demolding is carried out, specifically, the demolding column arranged on the lower mold 204 abuts against the surface of the dense resin, so that the sealing resin is separated from the inner surface of the lower mold 204, after demolding, the demolding column can penetrate into the surface of the sealing resin to form a groove when abutting against the surface of the dense resin, and the groove forms the demolding hole 13. When the upper mold 203 is removed, the thimble 202 is pulled out to form the positioning hole 12 in the sealing resin, and the thimble 202 abuts against the surface of the circuit board 30, so that the bottom of the positioning hole 12 is exposed from the circuit board 30. The sealing resin is thereafter cured to form the sealing layer 10, and the free ends of the leads 80 are exposed from the sealing layer 10.

In step S700, a connecting rib (not shown) connecting the other ends of the plurality of pins 80 is cut off to form a semiconductor circuit to be tested, wherein the connecting rib is a residue generated in the process of manufacturing the pins 80, and the connecting rib may cause a short circuit between the pins 80 and the pins 80, and therefore the connecting rib needs to be cut off in the process of manufacturing the semiconductor circuit. In one example, the connecting rib connecting the second ends of the plurality of pins 80 may be cut off by a specific device so that the other ends of the pins 80 are not connected to each other, so as to obtain the semiconductor circuit to be tested, so as to perform the parameter test on the semiconductor circuit to be tested in the next step.

The test equipment can be used for performing parameter test on the semiconductor circuit to be tested, for example, the test equipment can send a test signal to the semiconductor circuit to be tested and receive a feedback signal fed back by the semiconductor circuit to be tested; the test equipment processes the feedback signal to obtain corresponding feedback data, compares the feedback data with a preset threshold range, judges that the semiconductor circuit to be tested is qualified when the feedback data meet the preset threshold range, and then bends and molds each pin 80 of the semiconductor circuit to be tested which is qualified based on the shape of the preset pin 80, thereby obtaining the qualified semiconductor circuit.

Further, before the testing equipment can be used for carrying out parameter testing on the semiconductor circuit to be tested, laser marking can be carried out through the laser equipment so as to mark the surface of the sealing layer 10 of the semiconductor circuit, and therefore identification and management of the semiconductor circuit product are facilitated.

In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the utility model. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

In the description of the present invention, it is to be understood that the terms "central," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the utility model and to simplify the description, and are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed and operated in a particular orientation, and are therefore not to be considered limiting of the utility model.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.

In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or they may be connected internally or in any other suitable relationship, unless expressly stated otherwise. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.

In the present invention, unless otherwise expressly stated or limited, the first feature "on" or "under" the second feature may be directly contacting the first and second features or indirectly contacting the first and second features through an intermediate. Also, a first feature "on," "over," and "above" a second feature may be directly or diagonally above the second feature, or may simply indicate that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature may be directly under or obliquely under the first feature, or may simply mean that the first feature is at a lesser elevation than the second feature.

Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.

Claims (9)

1. A semiconductor circuit, comprising:

a circuit substrate including a mounting surface and a heat dissipation surface;

an insulating layer disposed on the mounting surface;

the circuit wiring layer is arranged on the surface of the insulating layer and provided with a plurality of preset mounting positions;

a plurality of electronic components configured on the preset mounting positions of the circuit wiring layer;

the pins are electrically connected with the circuit wiring layer at one ends respectively;

the sealing layer is used for covering and sealing the semiconductor circuit, and at least wraps up and sets the circuit substrate the installation face one side, it is a plurality of the other end of pin can be followed the sealing layer exposes, the both ends of sealing layer are provided with and run through the pilot hole of the thickness direction of sealing layer, the upper surface of sealing layer is formed with and follows the peripheral bellying of pilot hole, the bellying is used for accepting with spacing installation in the fastener in the pilot hole.

2. The semiconductor circuit according to claim 1, wherein the convex portion is in a shape of a boss.

3. The semiconductor circuit according to claim 1, wherein the convex portion is formed on an upper surface of the sealing layer and provided as a plurality of spaced bumps arranged along a peripheral edge of the fitting hole.

4. The semiconductor circuit according to claim 2 or 3, wherein a projection height of the projection portion is 0.5mm to 2 mm.

5. The semiconductor circuit of claim 1, wherein said mounting holes communicate radially outward to form notches at both ends of said sealing layer.

6. The semiconductor circuit of claim 5, wherein the mounting hole is U-shaped in cross section.

7. The semiconductor circuit according to claim 1, wherein the sealing layer is provided with a positioning hole penetrating through a thickness direction thereof and reaching a surface of the circuit substrate on a mounting surface side of the circuit substrate, so that the surface of the circuit substrate is exposed outward from a bottom of the positioning hole.

8. The semiconductor circuit according to claim 7, wherein a blind hole-shaped release hole is provided in the sealing layer on the mounting surface side of the circuit board, the release hole and the positioning hole are provided in an outer peripheral portion of the sealing layer, and the release hole is provided at a position offset from a center of the sealing layer with respect to the positioning hole.

9. The semiconductor circuit of claim 1, further comprising a plurality of bond wires connected between the plurality of electronic components, the circuit wiring layer, and the plurality of pins.

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