CN113496965A - Semiconductor circuit and method for manufacturing semiconductor circuit - Google Patents

Semiconductor circuit and method for manufacturing semiconductor circuit Download PDF

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Publication number
CN113496965A
CN113496965A CN202110771025.1A CN202110771025A CN113496965A CN 113496965 A CN113496965 A CN 113496965A CN 202110771025 A CN202110771025 A CN 202110771025A CN 113496965 A CN113496965 A CN 113496965A
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CN
China
Prior art keywords
circuit
inner cavity
pin
substrate
layer
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Pending
Application number
CN202110771025.1A
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Chinese (zh)
Inventor
王敏
左安超
谢荣才
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Guangdong Huixin Semiconductor Co Ltd
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Guangdong Huixin Semiconductor Co Ltd
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Priority to CN202110771025.1A priority Critical patent/CN113496965A/en
Publication of CN113496965A publication Critical patent/CN113496965A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/49—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4885—Wire-like parts or pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Abstract

The invention relates to a semiconductor circuit and a preparation method of the semiconductor circuit, a circuit layer is arranged on a circuit substrate; the circuit frame body is provided with an inner cavity, the circuit substrate is arranged in the substrate mounting area, and the circuit layer is close to the opening of the inner cavity; the plurality of pins are respectively arranged in the pin mounting areas; the first ends of the pins are respectively electrically connected with the circuit layer; the filling piece covers the circuit layer connected with the pins and fills the inner cavity; the sealing cover is arranged at the opening of the inner cavity filled with the filling piece in a sealing way; the second ends of the pins are respectively led out from the openings of the inner cavities, so that the phenomenon of welding holes in the pin mounting area can be avoided, and the reliability of the product is improved; the pins are not required to be cut and shaped by rib cutting and forming equipment, so that the pin preparation process is simplified, and the phenomenon of copper leakage caused by pin cutting is avoided; the complicated stepped steel mesh is not used for printing, so that the equipment cost is reduced; the inner cavity of the circuit frame body is filled through the filling piece, and the opening of the inner cavity is sealed through the sealing cover, so that plastic package is not needed to be carried out by adopting plastic package equipment, and the preparation cost is reduced.

Description

Semiconductor circuit and method for manufacturing semiconductor circuit
Technical Field
The invention relates to a semiconductor circuit and a preparation method of the semiconductor circuit, and belongs to the technical field of power semiconductor devices.
Background
A semiconductor circuit is a power-driven type product that combines power electronics and integrated circuit technology. The semiconductor circuit integrates a power switching device and a high-voltage driving circuit, and incorporates a fault detection circuit for detecting an overvoltage, an overcurrent, an overheat, and the like. The semiconductor circuit receives the control signal of the CPU or the DSP to drive the subsequent circuit to work, and sends the state detection signal of the system back to the CPU or the DSP for processing. Compared with the traditional discrete scheme, the semiconductor circuit gains a bigger and bigger market with the advantages of high integration degree, high reliability and the like, is particularly suitable for frequency converters of driving motors and various inverter power supplies, and is an ideal power electronic device for variable-frequency speed regulation, metallurgical machinery, electric traction, servo drive and variable-frequency household appliances. The semiconductor circuit is composed of a high-speed low-power-consumption tube core, an optimized gate-level driving circuit and a quick protection circuit. Even if a load accident or improper use occurs, the semiconductor circuit itself can be prevented from being damaged. In general, a semiconductor circuit uses an IGBT as a power switching element, and has an integrated structure in which a current sensor and a driving circuit are incorporated. In the face of market miniaturization and low cost competition, higher requirements are put forward on high integration and high heat dissipation technology of semiconductor circuits.
In the implementation process, the inventor finds that at least the following problems exist in the conventional technology: in the existing semiconductor circuit, the pin preparation process is complicated, the pin is generally required to be cut and shaped by rib cutting and forming equipment, the semiconductor circuit preparation cost is high, the copper leakage phenomenon is easily generated due to the cutting of the pin, and the void phenomenon easily exists in the pin area welding.
Disclosure of Invention
Therefore, the problems that in the traditional design and semiconductor circuit preparation process, the pin preparation process is complicated, the pins are generally required to be cut and shaped by rib cutting forming equipment, the semiconductor circuit preparation cost is high, the copper leakage phenomenon is easily caused by the cutting of the pins, and the pin area welding is easily hollow are needed in the conventional semiconductor circuit are necessarily solved. A semiconductor circuit and a method of manufacturing a semiconductor circuit are provided.
Specifically, the present invention discloses a semiconductor circuit comprising:
a circuit substrate on which a circuit layer is provided;
the circuit board comprises a circuit frame body, wherein the circuit frame body is provided with an inner cavity, and the inner cavity is provided with a substrate mounting area and a pin mounting area; the circuit substrate is arranged in the substrate mounting area, and the circuit layer is close to the opening of the inner cavity;
the pins are respectively arranged in the pin mounting areas; the first ends of the pins are respectively electrically connected with the circuit layer;
the filling piece covers the circuit layer connected with the pins and fills the inner cavity;
the sealing cover is arranged at the opening of the inner cavity filled with the filling piece in a sealing manner;
wherein, the second end of each pin is respectively led out from the opening of the inner cavity.
Optionally, the substrate mounting region is located at the bottom of the inner cavity and is of a hollow structure; the substrate mounting area is provided with a first limiting frame edge and a second limiting frame edge; the first limit frame edge and the second limit frame edge are arranged oppositely.
Optionally, the first limiting frame edge is provided with a plurality of first clamping grooves, and the side wall of the inner cavity close to the first limiting frame edge is provided with a second clamping groove corresponding to the first clamping groove; each first clamping groove is communicated with each second clamping groove in a one-to-one correspondence manner; the second limiting frame edge is provided with a plurality of third clamping grooves, and the side wall of the inner cavity close to the second limiting frame edge is provided with a fourth clamping groove corresponding to the third clamping grooves; each third clamping groove is communicated with each fourth clamping groove in a one-to-one correspondence manner; and pin mounting areas are formed between each first clamping groove and each second clamping groove and between each third clamping groove and each fourth clamping groove.
Optionally, the pin includes a first pin segment and a second pin segment connected to the first pin segment; the first clamping groove and the third clamping groove are respectively used for accommodating corresponding first pin sections, and the second clamping groove and the fourth clamping groove are respectively used for accommodating corresponding second pin sections.
Optionally, each first pin segment is connected to the circuit layer through a metal wire; the height of each second pin section is higher than the height of the side wall of the inner cavity, and each second pin section is led out from the opening of the inner cavity respectively.
Optionally, the first lead segment is located between the substrate and the filling member, and the second lead segment is located between the sidewall of the inner cavity and the filling member.
Optionally, the first lead section is arranged perpendicular to the corresponding second lead section.
Optionally, an insulating layer is disposed on the circuit substrate, and the insulating layer is located between the circuit substrate and the circuit layer; the circuit layer comprises a circuit wiring layer and a circuit element arranged on the circuit wiring layer; the circuit wiring layer is provided on the insulating layer.
The invention also discloses a preparation method of the semiconductor circuit, which comprises the following steps:
providing a circuit substrate and a circuit frame body;
preparing a circuit layer on a circuit substrate;
arranging a plurality of pins in a pin mounting area of the circuit frame body, fixedly arranging a circuit substrate with a circuit layer in the substrate mounting area of the circuit frame body through an adhesive, and electrically connecting each pin with the circuit layer through a metal wire;
filling the filling piece into the inner cavity of the circuit frame body provided with the circuit substrate and the plurality of pins so that the circuit layer connected with the pins is covered with the filling piece, and the inner cavity is filled with the filling piece;
and arranging a sealing cover on the inner cavity filled with the filling piece, so that the sealing cover seals the opening of the inner cavity, and leading the second ends of the pins out of the opening of the inner cavity respectively to form a semiconductor circuit.
Alternatively, the step of fixing the circuit substrate having the circuit layer to the substrate mounting region of the circuit frame body by an adhesive may include:
coating adhesives on a first limiting frame edge and a second limiting frame edge of a substrate mounting area respectively, wherein the first limiting frame edge and the second limiting frame edge are arranged oppositely;
and placing the circuit substrate in a substrate mounting area so that the circuit substrate is bonded on the first limit frame edge and the second limit frame edge in a limiting way, and the circuit layer faces the opening of the inner cavity and is fixed on the circuit frame body by curing the adhesive.
One of the above technical solutions has the following advantages and beneficial effects:
in each of the embodiments of the semiconductor circuit described above, the circuit layer is provided on the circuit substrate; the circuit frame body is provided with an inner cavity, and the inner cavity is provided with a substrate mounting area and a pin mounting area; the circuit substrate is arranged in the substrate mounting area, and the circuit layer is close to the opening of the inner cavity; the plurality of pins are respectively arranged in the pin mounting areas; the first ends of the pins are respectively electrically connected with the circuit layer; the filling piece covers the circuit layer connected with the pins and fills the inner cavity; the sealing cover is arranged at the opening of the inner cavity filled with the filling piece in a sealing way; the second ends of the pins are respectively led out from the openings of the inner cavities, so that the phenomenon of welding holes in the pin mounting area can be avoided, and the reliability of the product is improved; the pins are not required to be cut and shaped by rib cutting and forming equipment, so that the pin preparation process is simplified, and the phenomenon of copper leakage caused by pin cutting is avoided; the complicated stepped steel mesh is not used for printing, so that the equipment cost is reduced; the inner cavity of the circuit frame body is filled through the filling piece, and the opening of the inner cavity is sealed through the sealing cover, so that plastic package is not needed to be carried out by adopting plastic package equipment, and the preparation cost is reduced.
Drawings
Fig. 1 is a schematic structural diagram of a pin according to an embodiment of the invention;
fig. 2 is a first view structural diagram of a circuit frame according to an embodiment of the invention;
fig. 3 is a second perspective structural view of the circuit frame according to the embodiment of the invention;
fig. 4 is a schematic view of a first view structure of a combination of a pin and a circuit frame body according to an embodiment of the invention;
fig. 5 is a second view structure diagram of the combination of the leads and the circuit frame body according to the embodiment of the invention;
FIG. 6 is a schematic structural diagram of a circuit substrate according to an embodiment of the invention;
fig. 7 is a schematic structural view of the combination of the circuit substrate, the circuit frame body and the pins according to the embodiment of the invention;
FIG. 8 is a schematic diagram of an internal structure of a semiconductor circuit according to an embodiment of the present invention;
FIG. 9 is a schematic view of a sealing cap according to an embodiment of the present invention;
FIG. 10 is an exploded view of a semiconductor circuit according to an embodiment of the present invention;
FIG. 11 is a first schematic view of a semiconductor circuit according to an embodiment of the present invention;
FIG. 12 is a second schematic view of a semiconductor circuit according to an embodiment of the present invention;
FIG. 13 is a schematic cross-sectional view taken along line A-A' of FIG. 12;
fig. 14 is a flow chart illustrating a method for manufacturing a semiconductor circuit according to an embodiment of the invention.
Reference numerals:
the semiconductor circuit comprises a semiconductor circuit 10, a circuit substrate 100, a circuit layer 200, a metal wire 220, a circuit frame body 300, an inner cavity 310, a first limit frame 320, a first clamping groove 322, a second limit frame 330, a second clamping groove 340, a pin 400, a first pin section 410, a second pin section 420, a filling member 500 and a sealing cover 600.
Detailed Description
In order to make the technical solutions better understood by those skilled in the art, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only partial embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It is to be noted that the embodiments and features of the embodiments may be combined with each other without conflict in structure or function. The present invention will be described in detail below with reference to the embodiments with reference to the attached drawings.
In order to overcome the above-mentioned problems of the conventional semiconductor circuit, in one embodiment, as shown in fig. 1 to 13, the present invention provides a semiconductor circuit 10, wherein the semiconductor circuit 10 includes a circuit substrate 100, a circuit frame body 300, a plurality of leads 400, a filling member 500, and a sealing cover 600. A circuit layer 200 is provided on the circuit substrate 100; the circuit frame body 300 is provided with an inner cavity 310, and the inner cavity 310 is provided with a substrate mounting area and a pin 400 mounting area; the circuit substrate 100 is disposed in the substrate mounting area, and the circuit layer 200 is close to the opening of the inner cavity 310; the plurality of pins 400 are respectively arranged in the pin 400 mounting areas; the first ends of the plurality of pins 400 are electrically connected to the circuit layer 200, respectively; the filling member 500 covers the circuit layer 200 connected with each pin 400 and fills the inner cavity 310; the sealing cap 600 is sealingly disposed at the opening of the inner cavity 310 filled with the packing member 500; wherein, the second end of each pin 400 is led out from the opening of the inner cavity 310.
The circuit substrate 100 may be used to support a high voltage driving circuit of the entire semiconductor circuit 10 and corresponding components. The circuit substrate 100 may be made of a metal material, such as a rectangular plate made of aluminum of 1100, 5052, etc., and the thickness of the rectangular plate is much thicker than other layers, generally 0.8mm to 2mm, and the common thickness is 1.5mm, so as to mainly achieve the heat conduction and heat dissipation effects on components such as power devices, etc. For another example, the circuit board 100 may be made of other metal materials with good thermal conductivity, for example, a rectangular plate made of copper. The shape of the circuit board 100 of the present invention is not limited to a rectangular shape, and may be a circular shape, a trapezoidal shape, or the like. The circuit board 100 is provided with a circuit layer 200, and the circuit layer 200 is provided with internal circuits such as a power switch device and a high-voltage driving circuit. The power switch device and the high-voltage driving circuit are electrically connected through a bonding metal wire.
The circuit frame body 300 can be prepared by injecting a non-metal material into a special mold, an inner cavity 310 is formed in the circuit frame body 300, a substrate mounting area and a pin 400 mounting area are arranged on the inner cavity 310, the shape of the substrate mounting area is the same as that of the circuit substrate 100, a mounting opening is formed in the substrate mounting area, and the size of the circuit substrate 100 is larger than that of the mounting opening. In one example, the circuit substrate 100 is bonded to the substrate mounting area by providing an adhesive on the peripheral edge of the mounting opening, and after the adhesive is cured, the circuit substrate 100 is firmly bonded to the substrate mounting area; in addition, the circuit layer 200 can penetrate the mounting opening such that the circuit layer 200 faces the opening of the internal cavity 310. The pin 400 mounting areas are arranged on two sides of the substrate mounting area, the pin 400 mounting areas are provided with a plurality of pin 400 mounting positions, and the pin 400 mounting positions are in a clamping groove structure. In one example, the depth of the slot of the pin 400 mounting site is greater than or equal to the thickness of the pin 400 so that the pin 400 can be snap-fit fully over the pin 400 mounting site. It should be noted that the thickness of the circuit frame body 300 may be determined according to the height of the internal components on the circuit layer 200, the height of the bonding metal wire arc, the dielectric strength, and the creepage distance design requirement, for example, the electrical clearance requirement generally requires that the size of the circuit frame body 300 is 3mm to 8 mm.
The pins 400 may be used to transmit signals to corresponding internal circuits on the circuit substrate 100 and signals output by corresponding internal circuits on the circuit layer 200 to an external module. The plurality of pins 400 may be divided into a plurality of low voltage pins 400 and a plurality of high voltage pins 400 according to the voltage level of the transmission signal. The low voltage pin 400 refers to a pin 400 terminal for transmitting a low voltage logic control signal, and is used for connecting a low voltage control circuit such as an MCU chip and an IC control circuit; for example, the first end of the low voltage pin 400 may be electrically connected to the detection circuit or the low voltage control circuit on the circuit layer 200 through a bonding metal wire, wherein the bonding metal wire may be a metal wire made of gold, aluminum, copper, or the like. The high voltage pin 400 refers to a terminal of the pin 400 for transmitting a high voltage power output signal, which is used to connect a high voltage driving circuit on the circuit layer 200; for example, the first end of the high voltage pin 400 may be electrically connected to the power switch device and the high voltage driving circuit on the circuit layer 200 through a bonding metal line, wherein the bonding metal line may be a metal line made of gold, aluminum, copper, or the like.
The lead 400 can be made of a C194(-1/2H) plate (chemical composition: Cu (97.0), Fe: 2.4, P: 0.03 and Zn: 0.12) or a KFC (-1/2H) plate (chemical composition: Cu (99.6), Fe: 0.1 (0.05-0.15) and P: 0.03 (0.025-0.04)), the C194 or KFC plate with the thickness of 0.5mm is processed through a stamping or etching process, nickel plating with the thickness of 0.1-0.5um is firstly performed on the surface, and tin plating with the thickness of 2-5um is performed on the surface.
It should be noted that the pin 400 is a discrete pin 400 structure, the pin 400 is disposed on a pin 400 mounting position of a pin 400 mounting area, a first end of the pin 400 is connected to a corresponding component on the circuit layer 200 through a bonding metal wire, a second end of the pin 400 is led out from an opening of the inner cavity 310, and a height of the second end of the pin 400 is greater than a height of a side wall of the inner cavity 310.
The filling member 500 may be soft silicone (i.e., heat conductive silicone), which is a high-end heat conductive compound, and has the characteristics of not solidifying and not conducting electricity, so as to avoid the risk of short circuit. For example, the filling member 500 is a heat-conductive adhesive sealing silicone rubber, which is a one-component, heat-conductive, room-temperature curing silicone adhesive sealing rubber. The water in the air is condensed to release low molecules to cause crosslinking and curing, and the low molecules are vulcanized into a high-performance elastomer, so that the filling member 500 has excellent cold and hot alternation resistance, aging resistance and electrical insulation performance. And has excellent moisture-proof, shock-proof, corona-resistant, electric leakage-resistant and chemical medium-resistant properties. Can be used in the temperature environment of-60 to 280 ℃, can keep the performance unchanged, does not swell, has good adhesion to most of metal and non-metal materials, and can have high adhesion performance and super-strong heat conduction effect on electronic components. The sealing cover 600 is made of a non-metal insulating material, the thickness of the sealing cover 600 may be 0.1mm-1mm, and the sealing cover 600 functions to seal the filling member 500 in the inner cavity 310 of the circuit frame body 300, so as to prevent the filling member 500 from leaking. The shape and size of the sealing cover 600 are the same as those of the opening of the cavity 310, and the sealing cover 600 can be sealed at the opening of the cavity 310 by arranging an adhesive at the opening of the cavity 310 of the circuit substrate 100, then bonding the sealing cover 600 to the opening of the cavity 310, and curing the adhesive. The sealing cover 600 may be used to seal the opening of the inner cavity 310 filled with the filling member 500, so that the circuit layer 200 of the circuit substrate 100, the first ends of the pins 400 and the filling member 500 are sealed in the inner cavity 310 of the circuit frame body 300, thereby protecting the internal circuits and being voltage-proof.
In the process of manufacturing the circuit frame body 300, the non-metal material may be injected into a special mold through a plastic package process, and the circuit frame body 300 is obtained through demolding. The non-metallic material can be thermosetting polymer, such as epoxy resin, phenolic resin, silica gel, amino, unsaturated resin; in order to improve heat dissipation, the non-metallic material may be a composite material containing powder or fiber of metal, ceramic, silicon oxide, graphene, or the like. In one example, the non-metallic material may be a molding compound prepared by mixing epoxy resin as a matrix resin, high-performance phenolic resin as a curing agent, silica powder and the like as fillers, and various additives. The special molds with different shapes can be designed according to different design requirements, and the circuit frame body 300 with different shapes and structures can be obtained by injection molding. For example, the circuit frame body 300 may have a rectangular parallelepiped structure.
Specifically, the circuit frame body 300 is obtained by injection molding through a special mold, so that the circuit frame body 300 has a substrate mounting area and a pin 400 mounting area; by providing the circuit layer 200 on the first board surface of the circuit substrate 100, the size of the first board surface is larger than that of the circuit layer 200, i.e., the periphery of the circuit layer 200 has a process edge bonded to the substrate mounting area. In the manufacturing process, each pin 400 is respectively arranged at the corresponding pin 400 mounting position on the pin 400 mounting areaOn the upper partA first end of each lead 400 is adjacent to the substrate mounting region, and a second end of each lead 400 extends from the opening of the inner cavity 310 of the circuit frame body 300. An adhesive is disposed on the rear side of the substrate mounting area of the circuit frame body 300, the circuit substrate 100 with the circuit layer 200 disposed thereon is placed on the substrate mounting area from the rear side of the bottom of the inner cavity 310 of the circuit frame body 300, and the circuit layer 200 is close to the opening of the inner cavity 310, so that the circuit substrate 100 and the substrate mounting area are firmly bonded by curing the adhesive. Then, the corresponding circuit elements on the circuit layer 200 are electrically connected to each other through the bonding metal lines, and the first end of each pin 400 is electrically connected to the corresponding circuit elements on the circuit layer 200 through the bonding metal lines. Then theThe filling member 500 is injected into the inner cavity 310 of the circuit frame body 300, so that the filling member 500 covers the circuit layer 200 and fills the inner cavity 310, for example, soft silica gel is filled into the inner cavity 310 of the circuit frame body 300 through filling and sealing equipment, so that the soft silica gel covers the circuit elements and bonding metal wires of the whole circuit layer 200, the electrical insulation is realized, and the shock resistance, the moisture resistance and the heat dissipation effect are achieved. Finally, the sealing cap 600 is covered on the surface of the filling member 500, so that the semiconductor circuit 10 of the embodiment of the present application is obtained, and the opening provided in the cavity 310 filled with the filling member 500 is sealed by the sealing cap 600, thereby preventing the filling member 500 from leaking.
Further, firstly, putting the prepared circuit substrate 100 into a special carrier (the carrier can be made of materials with high temperature resistance of more than 200 ℃ such as aluminum, synthetic stone, ceramics, PPS and the like), arranging a copper foil layer on the circuit substrate 100, pasting a power device chip on a component mounting position through automatic chip pasting equipment (DA machine) at the component mounting position reserved on the copper foil layer by brushing tin paste or point silver glue, pasting a resistor and a capacitor on the component mounting position through automatic SMT equipment, then welding all components on corresponding mounting positions through a reflow oven by the whole semi-finished product including the carrier, and detecting the welding quality of the components through visual inspection of AOI equipment; foreign matters such as flux and aluminum debris remaining on the circuit board 100 are removed by cleaning methods such as spraying and ultrasonic cleaning, and the circuit layer 200 is provided on the circuit board 100.
In the above embodiment, the circuit layer 200 is disposed on the circuit substrate 100; the circuit frame body 300 is provided with an inner cavity 310, and the inner cavity 310 is provided with a substrate mounting area and a pin 400 mounting area; the circuit substrate 100 is disposed in the substrate mounting area, and the circuit layer 200 is close to the opening of the inner cavity 310; the plurality of pins 400 are respectively arranged in the pin 400 mounting areas; the first ends of the plurality of pins 400 are electrically connected to the circuit layer 200, respectively; the filling member 500 covers the circuit layer 200 connected with each pin 400 and fills the inner cavity 310; the sealing cap 600 is sealingly disposed at the opening of the inner cavity 310 filled with the packing member 500; the second end of each pin 400 is respectively led out from the opening of the inner cavity 310, so that the welding cavity phenomenon of the pin 400 mounting area can be avoided, the pin 400 does not need to be electrically connected with the circuit layer 200 through welding, the production process is simplified, and the production efficiency and the product reliability are improved; the pin 400 does not need to be welded with the circuit layer 200, and no stress exists in the middle, so that the risk of layering of the insulating layer 210 is reduced; unnecessary dummy pins 400 and reinforcing ribs are not required to be cut by rib cutting forming equipment, the preparation process of the pins 400 is simplified, and the phenomenon of copper leakage caused by cutting of the pins 400 is avoided; welding paint does not need to be coated on a welding position in advance, and a step steel mesh with a complex process is not used for printing, so that the process is simplified, and the equipment cost is reduced; through the inner chamber 310 of filler 500 embedment circuit support body 300, and through the opening of sealed 600 sealed inner chamber 310, need not to adopt plastic envelope equipment to carry out the plastic envelope, mould and equipment have been reduced to traditional plastic envelope technology relatively, do not have the encapsulation gas pocket risk, have reduced manufacturing cost.
In some embodiments of the present invention, as shown in fig. 2 and 3, the substrate mounting region is located at the bottom of the inner cavity 310 and has a hollow structure; the substrate mounting area is provided with a first limit frame edge 320 and a second limit frame edge 330; the first limiting frame edge 320 is opposite to the second limiting frame edge 330.
The substrate mounting area is a hollow structure, that is, the bottom of the inner cavity 310 is provided with a mounting opening, and the shape and the size of the mounting opening are the same as those of the circuit layer 200; for example, the mounting opening may be, but is not limited to, rectangular. The first limiting frame 320 and the second limiting frame 330 are respectively close to the sidewall of the inner cavity 310 of the circuit frame 300, the back surface (i.e., the surface far away from the inner cavity 310) of the first limiting frame 320 is step-shaped, and the back surface (i.e., the surface far away from the inner cavity 310) of the second limiting frame 330 is step-shaped. During assembly, a layer of adhesive is brushed on the first limiting frame edge 320 and the second limiting frame edge 330, the circuit substrate 100 is assembled from the bottom back of the circuit frame body 300, the technical edge on the circuit substrate 100 is attached to the first limiting frame edge 320 and the second limiting frame edge 330 in a limiting mode, and the circuit layer 200 on the circuit substrate 100 penetrates through the mounting opening and is open towards the inner cavity 310. The process edge on the circuit substrate 100 refers to a part of the substrate edge at the periphery of the circuit layer 200. For example, one side of the circuit substrate 100 is divided into a circuit layer 200 area and a process edge area located at the periphery of the circuit layer 200, the circuit layer 200 is disposed in the circuit layer 200 area, and the process edge area is used for being attached to the first limiting frame edge 320 and the second limiting frame edge 330.
In some embodiments of the present invention, as shown in fig. 2 and 10, the first limiting frame 320 is provided with a plurality of first engaging slots 322, and the sidewall of the inner cavity 310 near the first limiting frame 320 is provided with a second engaging slot 340 corresponding to the first engaging slot 322; each first card slot 322 is communicated with each second card slot 340 in a one-to-one correspondence manner; the second limiting frame 330 is provided with a plurality of third slots (not shown), and a fourth slot (not shown) corresponding to the third slot is arranged on the side wall of the inner cavity 310 close to the second limiting frame 330; each third clamping groove is communicated with each fourth clamping groove in a one-to-one correspondence manner; the pin 400 mounting area is formed between each first card slot 322 and each second card slot 340, and between each third card slot and each fourth card slot.
A plurality of first slots 322 are disposed on the front surface (i.e., the surface close to the opening of the inner cavity 310) of the first limiting frame 320, and the distance between the first slots 322 can be determined according to the layout of circuit elements on the circuit layer 200 and the requirement of creepage distance. A plurality of second engaging grooves 340 are formed on the side wall of the inner cavity 310 close to the first limiting frame 320, each second engaging groove 340 corresponds to each first engaging groove 322 one by one, and the first engaging grooves 322 are communicated with the corresponding second engaging grooves 340. In one example, first card slot 322 and corresponding second card slot 340 are perpendicular to each other.
A plurality of third slots are disposed on the front surface (i.e., the surface close to the opening of the inner cavity 310) of the second limiting frame 330, and the distance between the third slots can be determined according to the layout of circuit elements on the circuit layer 200 and the requirement of creepage distance. A plurality of fourth clamping grooves are formed in the side wall of the inner cavity 310 close to the second limiting frame 330, each third clamping groove and each fourth clamping groove are arranged in a one-to-one correspondence manner, and the third clamping grooves are communicated with the corresponding fourth clamping grooves. In one example, the third card slot is orthogonal to the corresponding fourth card slot.
Further, as shown in fig. 1 and 4, the pin 400 includes a first pin segment 410, and a second pin segment 420 connected to the first pin segment 410; the first card slot 322 and the third card slot are respectively used for accommodating the corresponding first pin section 410, and the second card slot 340 and the fourth card slot are respectively used for accommodating the corresponding second pin section 420.
The lead 400 can be divided into a first lead section 410 and a second lead section 420, the size of the first lead section 410 is matched with the size of the groove of the first card slot 322, and the size of the second lead section 420 is matched with the size of the groove of the second card slot 340. In one example, the lead 400 can be bent such that the first lead segment 410 is perpendicular to the second lead segment 420. When the lead 400 is assembled, the first lead section 410 of a part of the lead 400 is aligned with the first card slot 322, the second lead section 420 is aligned with the second card slot 340, and pressure is respectively applied to the first lead section 410 and the second lead section 420, so that the first lead section 410 is clamped into the first card slot 322, and the second lead section 420 is clamped into the second card slot 340. In addition, the first lead segment 410 of the other part of the lead 400 may be aligned with the third card slot, and the second lead segment 420 may be aligned with the fourth card slot, so as to apply pressure to the first lead segment 410 and the second lead segment 420, respectively, so that the first lead segment 410 is clamped into the third card slot, and the second lead segment 420 is clamped into the fourth card slot.
Further, each first lead segment 410 is connected to the circuit layer 200 through a metal wire; the height of each second lead segment 420 is higher than the height of the side wall of the inner cavity 310, and each second lead segment 420 is led out from the opening of the inner cavity 310.
After the pin 400 is disposed in the pin 400 mounting area, the first pin segment 410 can be electrically connected to the corresponding circuit element on the circuit layer 200 through a metal wire (i.e., a bonding metal wire). The height of the second lead segment 420 is higher than the height of the side wall of the inner cavity 310, that is, the part of the second lead segment 420 is not filled with the filling member 500, so that the second lead segment 420 can be led out from the opening of the inner cavity 310 (that is, part of the second lead segment 420 is led out from the second card slot 340, and the other part of the second lead segment 420 is led out from the fourth card slot), and the connection of the second lead segment 420 and an external module is facilitated.
Further, the first lead section 410 is located between the substrate and the filling member 500, so that the first lead section 410 is limited between the substrate and the filling member 500, and the first lead section 410 is prevented from moving; the second lead segment 420 is located between the sidewall of the inner cavity 310 and the filling member 500, so that the first lead segment 410 is limited between the substrate and the filling member 500, and the first lead segment 410 is prevented from moving, thereby fixing the circuit frame body 300 and the lead 400.
In the above embodiment, the discrete pins 400 are arranged on the corresponding pin 400 mounting positions of the circuit frame body 300, the circuit substrate 100 is arranged on the corresponding substrate mounting positions of the circuit frame body 300, the pins 400 are electrically connected with the circuit layer 200 through bonding metal wires, the filling member 500 is filled in the inner cavity 310 and is hermetically arranged at the opening of the inner cavity 310 filled with the filling member 500 through the sealing cover 600, and the second ends of the pins 400 are led out from the opening of the inner cavity 310, so as to obtain the semiconductor circuit 10 in the embodiment of the application, the unnecessary dummy pins 400 and reinforcing ribs do not need to be cut off by using a rib cutting molding device, so that the device cost is reduced; the pin 400 mode does not need to be electrically connected with the circuit layer 200 through welding, so that the risk of welding holes is avoided, the production process is simplified, and the production efficiency is improved; welding paint does not need to be coated on the welding position in advance, and a step steel mesh is not used, so that the process is simplified, and the cost is reduced; the pin 400 does not need to be welded with the copper foil layer, no stress exists in the middle, and the risk of layering of the insulating layer 210 is reduced; and plastic packaging is not required to be performed by adopting plastic packaging equipment, so that compared with the traditional plastic packaging process, the die and equipment are reduced, the risk of packaging air holes is avoided, and the preparation cost is reduced.
It should be noted that the circuit frame body 300 is further provided with screw mounting holes, and the screw mounting holes are located on the outer side of the circuit frame body. In one example, the screw mounting hole is an open hole.
In some embodiments of the present invention, an insulating layer (not shown) is disposed on the circuit substrate 100, and the insulating layer is located between the circuit substrate 100 and the circuit layer 200; the circuit layer 200 includes a circuit wiring layer, and circuit elements disposed on the circuit wiring layer; the circuit wiring layer is provided on the insulating layer.
The insulating layer may be used to prevent the circuit layer 200 from conducting with the circuit substrate 100. The insulating layer is disposed on the surface of the circuit substrate 100, and the thickness of the insulating layer is thinner than that of the circuit substrate 100, generally 50um to 150um, and usually 110 um. The circuit layer 200 is provided on the insulating layer so that the circuit layer 200 is insulated from the circuit substrate 100. The circuit wiring layer is made of metal such as copper and insulated from the circuit board 100, and includes circuit lines made of etched copper foil, and the thickness of the circuit layer is also thin, for example, about 70 um. In one example, the circuit wiring layer further includes pads disposed near the side edge of the circuit substrate 100, which may be formed using 2 ounce copper foil. And finally, a thin green oil layer can be coated on the circuit wiring layer to play a role in circuit isolation and to separate the circuit lines from the circuit lines. The circuit elements are arranged on the circuit wiring layer, and the circuit elements or the circuit elements and the circuit wiring layer can be electrically connected through bonding metal wires; the circuit element may be fixed to the circuit wiring layer by soldering.
In one example, the circuit element may employ an active element such as a transistor or a diode, or a passive element such as a capacitor or a resistor. Further, elements such as power elements having a large heat generation amount may be fixed to the circuit board 100 by a heat sink made of copper or the like. The insulating layer is formed to cover at least one surface of the circuit substrate 100. And the resin material such as epoxy resin and the like forming the sealing layer can be filled with fillers such as alumina, silicon aluminum carbide and the like at high concentration to improve the heat conductivity, the fillers can be angular in order to improve the heat conductivity, and the fillers can be spherical in order to avoid the risk that the fillers damage the surface of the circuit element.
In some embodiments of the present invention, as shown in fig. 14, there is also provided a method of manufacturing the semiconductor circuit according to the above-mentioned embodiments, the method including the steps of:
step S100, providing a circuit substrate and a circuit frame body.
Step S200, preparing a circuit layer on the circuit substrate.
Step S300, disposing a plurality of pins in the pin mounting area of the circuit frame body, fixing the circuit substrate having the circuit layer in the substrate mounting area of the circuit frame body by using an adhesive, and electrically connecting each pin with the circuit layer by using a metal wire.
And S400, filling a filling piece into an inner cavity of the circuit frame body provided with the circuit substrate and the plurality of pins, so that the circuit layer connected with the pins is covered with the filling piece, and the inner cavity is filled with the filling piece.
Step S500, a sealing cap is disposed on the cavity filled with the filler, so that the sealing cap seals the opening of the cavity, and the second ends of the pins are respectively led out from the opening of the cavity to form the semiconductor circuit.
Specifically, the semiconductor circuit is specifically prepared by the following steps: the circuit substrate and the circuit frame body with proper sizes are designed according to the required circuit layout, and for a common semiconductor circuit, the size of one circuit can be selected to be 64mm multiplied by 30 mm; putting the prepared circuit substrate into a special carrier (the carrier can be made of materials with high temperature resistance of more than 200 ℃ such as aluminum, synthetic stone, ceramics, PPS and the like), preparing an insulating layer on the circuit substrate, then laminating a copper foil on the surface of the insulating layer, etching the copper foil, and locally taking out the copper foil to form a circuit wiring layer; mounting a power device chip on a component mounting position reserved in a circuit layer through automatic die bonding equipment (DA machine) by brushing solder paste or dispensing silver paste, mounting a resistance element and a capacitance element on the component mounting position through automatic SMT equipment, placing pins on corresponding mounting positions through a manipulator or manually, and fixing the pins through a carrier; then with whole semi-manufactured goods including the carrier on reflow oven welds all components and parts to corresponding installation position together, detect components and parts welding quality through visual inspection AOI equipment, through washing modes such as spraying, supersound, clear away and remain foreign matter such as scaling powder and aluminium bits on the aluminium base metal board, through bonding the metal wire, form between circuit element and the circuit wiring and be connected, and then form the circuit layer on circuit substrate. The circuit frame body can be prepared from non-metal materials, a preset special die is adopted, the non-metal materials are injected into the special die, and the circuit frame body is formed after demolding, so that an inner cavity is formed in the circuit frame body, and a substrate mounting area and a pin mounting area are arranged in the inner cavity.
All the pins (such as each low-voltage pin and each high-voltage pin) are made of a metal base material such as a copper base material, such as a strip with the length C of 25mm, the width K of 1.5mm and the thickness H of 1mm, and the pins are bent and shaped into a first pin section and a second pin section (wherein the length of the first pin section is smaller than that of the second pin section) for the convenience of assembly, and the first pin section and the second pin section are perpendicular to each other. And then forming a nickel layer on the surface of the pin by an electroless plating method: the nickel layer is formed on the surface of the copper material with a special shape by the mixed solution of nickel salt and sodium hypophosphite and adding a proper complexing agent, the metal nickel has strong passivation capability, a layer of extremely thin passivation film can be rapidly generated, and the corrosion of atmosphere, alkali and certain acid can be resisted. The nickel plating crystal is extremely fine, and the thickness of the nickel layer is generally 0.1 mu m; then, by an acid sulfate process, the copper material with the formed shape and the nickel layer is soaked in a plating solution with positive tin ions for electrifying at room temperature, a nickel-tin alloy layer is formed on the surface of the nickel layer, the thickness of the nickel layer is generally controlled to be 5 mu m, and the protection and the weldability are greatly improved by the formation of the nickel layer. Thereby completing the pin preparation. And then, respectively clamping each pin into a corresponding pin mounting position on the pin mounting area.
After the pin is installed, the circuit frame body is placed upside down, the bottom of the inner cavity of the circuit frame body faces upwards, one layer of adhesive is brushed on the limiting frame edge of the substrate installation area, then the circuit substrate provided with the circuit layer is placed in the substrate installation area, the process edge of the circuit substrate is attached to the limiting frame edge through the adhesive, meanwhile, the circuit layer penetrates through the installation opening in the substrate installation area, and the circuit substrate is fixed on the circuit frame body through solidification of the adhesive. And then, the first pin sections of the pins are respectively electrically connected with the corresponding circuit elements on the circuit layer through bonding metal wires.
Then, a filling part (such as soft silica gel) is filled into the inner cavity of the circuit frame body through filling and sealing equipment by adopting a filling and sealing process, so that the filling part covers the components, the bonding wires and parts of the pins of the whole circuit in the inner cavity, namely, the circuit wiring, the circuit components and the metal wires are at least sealed through the filling part (such as soft silica gel); at least the connection portion of the lead and the circuit wiring is sealed by a filler (e.g., soft silicone rubber), and at least a portion of the lead extending outward is exposed without being sealed by the filler (e.g., soft silicone rubber). And finally, the sealing cover covers the surface of the filling part, namely covers the opening of the inner cavity, and seals the opening of the inner cavity through the sealing cover to prevent the filling part from leaking.
Finally, forming a semi-finished packaging product after a marking process; and carrying out electrical performance test on the packaged semi-product through an electrical parameter tester so as to form the semiconductor circuit.
In the above embodiment, the circuit layer is prepared on the circuit substrate; the circuit substrate is arranged in the substrate mounting area of the circuit frame body, and the circuit layer is close to the opening of the inner cavity; the plurality of pins are respectively arranged in the pin mounting areas; the first ends of the pins are respectively electrically connected with the circuit layer; the filling piece covers the circuit layer connected with the pins and fills the inner cavity; the sealing cover is arranged at the opening of the inner cavity filled with the filling piece in a sealing way; the second ends of the pins are respectively led out from the openings of the inner cavities, so that the welding cavity phenomenon of the pin mounting area can be avoided, the pins do not need to be electrically connected with the circuit layer through welding, the production process is simplified, and the production efficiency and the product reliability are improved; the pins do not need to be welded with the circuit layer, no stress exists in the middle, and the risk of layering of the insulating layer is reduced; unnecessary false pins and reinforcing ribs are not required to be cut by rib cutting and forming equipment, the pin preparation process is simplified, and the phenomenon of copper leakage caused by pin cutting is avoided; welding paint does not need to be coated on a welding position in advance, and a step steel mesh with a complex process is not used for printing, so that the process is simplified, and the equipment cost is reduced; the inner cavity of the circuit frame body is filled and sealed by the filling piece, the opening of the inner cavity is sealed by the sealing cover, plastic packaging is not needed by adopting plastic packaging equipment, and compared with the traditional plastic packaging process, the plastic packaging process has the advantages that the number of dies and equipment is reduced, the risk of packaging air holes is avoided, and the preparation cost is reduced. In addition, by adopting the encapsulation process of the embodiment of the application, the encapsulation stress is not generated like the traditional plastic package, the PMC post-curing is not needed, and the processing procedures are reduced; and moreover, the potting process is adopted, so that the line punching phenomenon cannot be generated, and the reliability of the semiconductor circuit preparation is improved.
In some embodiments of the present invention, the step of fixing the circuit substrate having the circuit layer to the substrate mounting region of the circuit frame body by the adhesive includes:
coating adhesives on a first limiting frame edge and a second limiting frame edge of a substrate mounting area respectively, wherein the first limiting frame edge and the second limiting frame edge are arranged oppositely;
and placing the circuit substrate in a substrate mounting area so that the circuit substrate is bonded on the first limit frame edge and the second limit frame edge in a limiting way, and the circuit layer faces the opening of the inner cavity and is fixed on the circuit frame body by curing the adhesive.
Particularly, brush a layer of adhesive on first spacing frame limit, the spacing frame edge of second, assemble circuit substrate from the bottom back of circuit support body for the spacing laminating in first spacing frame limit, the spacing frame limit of second of technological limit on the circuit substrate, the circuit layer on the circuit substrate passes the installing port, and towards the inner chamber opening. The process edge on the circuit substrate refers to a part of the substrate edge at the periphery of the circuit layer. For example, one side surface of the circuit substrate is divided into a circuit layer area and a process edge area positioned on the periphery of the circuit layer, the circuit layer is arranged on the circuit layer area, and the process edge area is used for being attached to the first limiting frame edge and the second limiting frame edge. The first limiting frame edge and the second limiting frame edge are respectively close to the side wall of the inner cavity of the circuit frame body, the back face (namely, the face far away from the inner cavity) of the first limiting frame edge is in a step shape, and the back face (namely, the face far away from the inner cavity) of the second limiting frame edge is in a step shape.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
In the description of the present invention, it is to be understood that the terms "central," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the invention and to simplify the description, and are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed and operated in a particular orientation, and are therefore not to be considered limiting of the invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.
In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or they may be connected internally or in any other suitable relationship, unless expressly stated otherwise. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
In the present invention, unless otherwise expressly stated or limited, the first feature "on" or "under" the second feature may be directly contacting the first and second features or indirectly contacting the first and second features through an intermediate. Also, a first feature "on," "over," and "above" a second feature may be directly or diagonally above the second feature, or may simply indicate that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature may be directly under or obliquely under the first feature, or may simply mean that the first feature is at a lesser elevation than the second feature.
Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.

Claims (10)

1. A semiconductor circuit, comprising:
a circuit substrate on which a circuit layer is disposed;
the circuit board comprises a circuit frame body, a circuit board and a circuit board, wherein the circuit frame body is provided with an inner cavity, and the inner cavity is provided with a substrate mounting area and a pin mounting area; the circuit substrate is arranged in the substrate mounting area, and the circuit layer is close to the opening of the inner cavity;
the pins are respectively arranged in the pin mounting areas; the first ends of the pins are respectively electrically connected with the circuit layer;
the filling piece covers the circuit layer connected with the pins and fills the inner cavity;
a sealing cover which is arranged in a sealing way at the opening of the inner cavity filled with the filling piece;
and the second end of each pin is led out from the opening of the inner cavity.
2. The semiconductor circuit according to claim 1, wherein the substrate mounting region is located at a bottom of the inner cavity and has a hollow structure; the substrate mounting area is provided with a first limiting frame edge and a second limiting frame edge; the first limiting frame edge and the second limiting frame edge are arranged oppositely.
3. The semiconductor circuit according to claim 2, wherein the first limiting frame is provided with a plurality of first slots, and a second slot corresponding to the first slot is provided on a sidewall of the inner cavity near the first limiting frame; each first clamping groove is communicated with each second clamping groove in a one-to-one correspondence manner; the second limiting frame edge is provided with a plurality of third clamping grooves, and the side wall of the inner cavity close to the second limiting frame edge is provided with a fourth clamping groove corresponding to the third clamping grooves; each third card slot is communicated with each fourth card slot in a one-to-one correspondence manner; the pin mounting area is formed between each first card slot and each second card slot, and between each third card slot and each fourth card slot.
4. The semiconductor circuit of claim 1, wherein the pin comprises a first pin segment, and a second pin segment connected to the first pin segment; the first card slot and the third card slot are respectively used for accommodating the corresponding first pin section, and the second card slot and the fourth card slot are respectively used for accommodating the corresponding second pin section.
5. The semiconductor circuit of claim 4, wherein each of the first lead segments is connected to the circuit layer by a metal line; the height of each second pin section is higher than that of the side wall of the inner cavity, and each second pin section is led out from the opening of the inner cavity respectively.
6. The semiconductor circuit of claim 5, wherein the first lead segment is located between the substrate and the filler and the second lead segment is located between the inner cavity sidewall and the filler.
7. The semiconductor circuit of claim 6, wherein the first lead segment is disposed perpendicular to the corresponding second lead segment.
8. The semiconductor circuit according to any one of claims 1 to 7, wherein an insulating layer is provided on the circuit substrate, the insulating layer being located between the circuit substrate and the circuit layer; the circuit layer comprises a circuit wiring layer and a circuit element arranged on the circuit wiring layer; the circuit wiring layer is arranged on the insulating layer.
9. A method for manufacturing a semiconductor circuit according to any one of claims 1 to 8, comprising the steps of:
providing a circuit substrate and a circuit frame body;
preparing a circuit layer on the circuit substrate;
arranging a plurality of pins in the pin mounting area of the circuit frame body, fixedly arranging the circuit substrate with the circuit layer in the substrate mounting area of the circuit frame body through an adhesive, and electrically connecting the pins with the circuit layer through metal wires respectively;
filling a filling piece into an inner cavity of the circuit frame body provided with the circuit substrate and the pins so that the filling piece covers the circuit layer connected with the pins and the inner cavity is filled with the filling piece;
and arranging a sealing cover on the inner cavity filled with the filling piece, so that the sealing cover seals the opening of the inner cavity, and leading the second end of each pin out of the opening of the inner cavity to form the semiconductor circuit.
10. A method for manufacturing a semiconductor circuit according to claim 9, wherein the step of fixing the circuit substrate having the circuit layer to the substrate mounting area of the circuit frame body by an adhesive comprises:
respectively coating adhesives on a first limiting frame edge and a second limiting frame edge of the substrate mounting area, wherein the first limiting frame edge and the second limiting frame edge are arranged oppositely;
and placing the circuit substrate in the substrate mounting area so that the circuit substrate is bonded on the first limiting frame edge and the second limiting frame edge in a limiting manner, the circuit layer faces the opening of the inner cavity, and the circuit substrate is fixed on the circuit frame body by curing the adhesive.
CN202110771025.1A 2021-07-08 2021-07-08 Semiconductor circuit and method for manufacturing semiconductor circuit Pending CN113496965A (en)

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Application Number Priority Date Filing Date Title
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115547964A (en) * 2022-11-29 2022-12-30 广东汇芯半导体有限公司 Power device with discrete pins and manufacturing method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115547964A (en) * 2022-11-29 2022-12-30 广东汇芯半导体有限公司 Power device with discrete pins and manufacturing method thereof

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