CN114220806B - Semiconductor circuit with rectifier circuit and method for manufacturing semiconductor circuit - Google Patents
Semiconductor circuit with rectifier circuit and method for manufacturing semiconductor circuit Download PDFInfo
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- CN114220806B CN114220806B CN202111574546.4A CN202111574546A CN114220806B CN 114220806 B CN114220806 B CN 114220806B CN 202111574546 A CN202111574546 A CN 202111574546A CN 114220806 B CN114220806 B CN 114220806B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of AC power input into DC power output; Conversion of DC power input into AC power output
- H02M7/003—Constructional details, e.g. physical layout, assembly, wiring or busbar connections
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Abstract
本发明涉及一种具有整流电路的半导体电路和半导体电路的制备方法，包括第一电路基板和第二电路基板、第一电路布线层和第二电路布线层、多个电子元件、多个引脚和密封层。其中第一电路基板和第二电路基板左右间隔设置，二者之间相隔一定间距，多个电子元件分别设置在第一电路布线层和第二电路布线层，其中第一电路布线层和设置其上的电子元件形成整流电路区，第二电路布线层和设置其上的电子元件形成驱动和逆变电路区，通过将这两个电路区设置在相互间隔设置的两个电路基板上，使得二者之间保持一段的电气隔离的间隙，使得整流电路区产生的电磁干扰无法基于电路布线层传导至容易受干扰的驱动和逆变电路区，有效的提升整个半导体电路的工作可靠性。
The present invention relates to a semiconductor circuit with a rectifier circuit and a method for preparing the semiconductor circuit, comprising a first circuit substrate and a second circuit substrate, a first circuit wiring layer and a second circuit wiring layer, a plurality of electronic components, a plurality of pins and a sealing layer. The first circuit substrate and the second circuit substrate are arranged at intervals from left to right, and a certain distance is between the two. The plurality of electronic components are arranged in the first circuit wiring layer and the second circuit wiring layer respectively, wherein the first circuit wiring layer and the electronic components arranged thereon form a rectifier circuit area, and the second circuit wiring layer and the electronic components arranged thereon form a drive and inverter circuit area. By arranging the two circuit areas on two circuit substrates arranged at intervals from each other, an electrically isolated gap is maintained between the two, so that the electromagnetic interference generated by the rectifier circuit area cannot be transmitted to the drive and inverter circuit area that is easily interfered based on the circuit wiring layer, and the working reliability of the entire semiconductor circuit is effectively improved.
Description
Technical Field
The invention relates to a semiconductor circuit with a rectifying circuit and a preparation method of the semiconductor circuit, and belongs to the technical field of semiconductor circuit application.
Background
Semiconductor circuits are a type of power driven product that combine power electronics and integrated circuit technology. In a traditional variable frequency motor servo control main control board, in order to meet the miniaturization requirement of the main control board, a rectifier bridge stack is integrated in a semiconductor circuit, so that the occupied space for assembling a motor cavity is reduced, and the integral miniaturization of the motor is facilitated. However, the rectifier bridge stack is high in power consumption and high in current transmission, so that electromagnetic interference and heat conduction are easily generated to other circuits of the semiconductor, such as a driving circuit, and the working reliability of the whole semiconductor circuit is affected.
Disclosure of Invention
The invention aims to solve the technical problem that the working reliability of the traditional semiconductor circuit is affected by electromagnetic interference and heat transfer after the rectifier bridge is integrated.
Specifically, the present invention discloses a semiconductor circuit comprising:
The first circuit substrate and the second circuit substrate are arranged at intervals left and right and respectively comprise a first mounting surface, a first radiating surface, a second mounting surface and a second radiating surface;
The first circuit wiring layer is arranged on the first mounting surface, the second circuit wiring layer is arranged on the second mounting surface, and a plurality of element mounting positions and a plurality of bonding pads are respectively arranged on the first mounting surface and the second mounting surface. ;
A plurality of electronic components respectively arranged on the first circuit wiring layer and the second circuit wiring layer, wherein the first circuit wiring layer and the electronic components arranged thereon form a rectifying circuit, and the second circuit wiring layer and the electronic components arranged thereon form an inverter circuit and a driving circuit;
a plurality of pins, one ends of which are electrically connected with the first circuit wiring layer and the second circuit wiring layer respectively;
And the sealing layer is used for wrapping at least one surface of the first circuit substrate and one surface of the second circuit substrate, on which the electronic element is arranged, and the other ends of the pins are exposed from the sealing layer.
Optionally, the heat dissipation surface of the first circuit substrate is exposed from the sealing layer, and the heat dissipation surface of the second circuit substrate is covered by the sealing layer.
Optionally, a gap between the first circuit substrate and the second circuit substrate is in a range of 0.5-4mm.
Optionally, the area of the first circuit substrate is less than 1/2 of the area of the second circuit substrate.
Optionally, a first insulating layer is further disposed between the first circuit substrate and the first circuit wiring layer, and a second insulating layer is further disposed between the second circuit substrate and the second circuit wiring layer.
Optionally, a green oil layer is further disposed on the surfaces of the first circuit wiring layer and the second circuit wiring layer where the component mounting positions and the pads are not disposed.
Optionally, the semiconductor circuit further comprises a plurality of bonding wires for connecting the plurality of electronic components.
Optionally, the bonding wire is gold wire, copper wire, gold-copper mixed wire, 38um or less thin aluminum wire, 100um or more thick aluminum wire.
Optionally, an alloy layer is disposed on the surface of the pin, and the thickness of the alloy layer is 5 μm.
The invention also provides a preparation method of the semiconductor circuit, which comprises the following steps:
Providing a first circuit substrate and a second circuit substrate, and respectively preparing a first insulating layer and a second insulating layer on the surfaces of the first circuit substrate and the second circuit substrate;
preparing a first circuit wiring layer and a second circuit wiring layer on the surfaces of the first insulating layer and the second insulating layer respectively;
preparing pins, wherein one ends of the pins are connected with each other through connecting ribs;
disposing electronic components and pins on the first circuit wiring layer and the second circuit wiring layer;
the electronic element and the circuit wiring layer are electrically connected through a bonding wire;
Injection molding the first circuit substrate and the second circuit substrate provided with the electronic element and the pins through a packaging mold to form a sealing layer, wherein the sealing layer covers one surface of the first circuit substrate on which the electronic element is mounted, the other surface of the first circuit substrate is exposed from the sealing layer, the sealing layer protects two surfaces of the second circuit substrate, and the other ends of the plurality of pins are exposed from the sealing layer;
Cutting off the connecting ribs among the pins to form a semiconductor circuit to be tested, carrying out parameter test on the semiconductor circuit to be tested through test equipment, and if the test is qualified, bending and forming each pin of the semiconductor circuit to be tested which is qualified according to the preset pin shape to obtain the qualified semiconductor circuit.
The semiconductor circuit of the present invention includes a first circuit substrate and a second circuit substrate, a first circuit wiring layer and a second circuit wiring layer, a plurality of electronic elements, a plurality of pins, and a sealing layer. The first circuit substrate and the second circuit substrate are arranged at left and right intervals, a certain distance is reserved between the first circuit substrate and the second circuit substrate, a plurality of electronic elements are respectively arranged on the first circuit wiring layer and the second circuit wiring layer, the first circuit wiring layer and the electronic elements arranged on the first circuit wiring layer form a rectifying circuit area, the second circuit wiring layer and the electronic elements arranged on the second circuit wiring layer form a driving circuit area and an inversion circuit area, the two circuit areas are arranged on the two circuit substrates which are arranged at intervals, a section of electric isolation gap is kept between the two circuit areas, electromagnetic interference generated by the rectifying circuit area cannot be conducted to the driving circuit area and the inversion circuit area which are easy to be interfered based on the circuit wiring layer, and the working reliability of the whole semiconductor circuit is effectively improved.
Drawings
Fig. 1 is a front view of a semiconductor circuit according to an embodiment of the present invention;
fig. 2 is a cross-sectional view of the semiconductor circuit of fig. 1 in the X-X direction;
FIG. 3 is a view of the semiconductor circuit of FIG. 1 with the encapsulation layer on the mounting surface of the circuit substrate removed to expose the electronic components;
FIG. 4 is a simplified schematic diagram of a semiconductor circuit according to an embodiment of the present invention;
FIG. 5 is a flow chart of a method for fabricating a semiconductor circuit according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of a pin manufactured in the manufacturing process of the semiconductor circuit according to the embodiment of the invention.
Reference numerals:
the first circuit substrate 11, the second circuit substrate 12, the first insulating layer 21, the second insulating layer 21, the first circuit wiring layer 31, the second circuit wiring layer 32, the rectifier diode 41, the frd42, the igbts 43, the driving chip 44, the sealing layer 50, the bonding wire 60, the pin 70, the connection rib 71, the bonding pad 81, the element mounting site 82, the gap 90, the rectifier circuit region 101, and the driving and inverting circuit region 102.
Detailed Description
In addition, in the case where the structure or the function is not conflicting, the embodiments of the present invention and the features in the embodiments may be combined with each other. The invention is described in detail below with reference to examples.
The semiconductor circuit is a circuit module which integrates a power switch device, a high-voltage driving circuit and the like and performs sealing and encapsulation on the appearance, and is widely applied to the power electronics field, such as the fields of frequency converters of driving motors, various inversion voltages, variable-frequency speed regulation, metallurgical machinery, electric traction, variable-frequency household appliances and the like. The semiconductor circuits herein have a variety of other names such as modular smart power systems (Modular Intelligent Power System, MIPS), smart power modules (INTELLIGENT POWER MODULE, IPM), or names known as hybrid integrated circuits, power semiconductor modules, power modules, etc.
As shown in fig. 1 to 4, the semiconductor circuit with the rectifying circuit according to the present invention includes the first circuit substrate 11 and the second circuit substrate 12, the first circuit wiring layer 31 and the second circuit wiring layer 32, a plurality of electronic components, a plurality of pins 70, and a sealing layer 50. The first circuit substrate 11 and the second circuit substrate 12 are arranged at left and right intervals, a certain interval is reserved between the first circuit substrate 11 and the second circuit substrate 12, and the first circuit substrate 11 and the second circuit substrate 12 respectively comprise a first mounting surface, a first radiating surface, a second mounting surface and a second radiating surface; the first circuit wiring layer 31 is provided on the first mounting surface, and the second circuit wiring layer 32 is provided on the second mounting surface; the plurality of electronic components are respectively arranged on the first circuit wiring layer 31 and the second circuit wiring layer 32, wherein the first circuit wiring layer 31 and the electronic components arranged thereon form a rectifying circuit, and the second circuit wiring layer 32 and the electronic components arranged thereon form an inverter circuit and a driving circuit; one ends of the plurality of pins 70 are electrically connected to the first circuit wiring layer 31 and the second circuit wiring layer 32, respectively; the sealing layer 50 wraps at least one surface of the first circuit board 11 and the second circuit board 12 on which the electronic components are mounted, and the other ends of the plurality of leads 70 are exposed from the sealing layer 50. In this way, the rectifying circuit with the circuit wiring layers on the first circuit substrate 11 is formed into the rectifying circuit area 101, the other circuits on the second circuit substrate 12 are formed into the driving and inverting circuit area 102 by the circuit wiring layers on the second circuit substrate 12, because the input and output ends of the rectifying circuit area 101 and the inverting circuit area are not connected on the circuit, and the two circuit wiring layers do not need to be provided with metal connecting wires such as bonding wires 60, by arranging the two circuit areas on the two circuit substrates which are arranged at intervals, a gap 90 with a certain electric isolation is kept between the two circuit areas, so that the electromagnetic interference generated by the rectifying circuit area 101 working in a high-current environment cannot be conducted to the weak-current working circuit of the driving and inverting circuit area 102 which is easy to receive interference, such as the low-voltage working area in the driving circuit in the circuit area, and the heat generated by the high-power device in the rectifying circuit cannot be conducted to the other circuits directly through the circuit wiring layers due to the existence of the gap 90, thereby effectively reducing the temperature rise of the other low-temperature working elements such as the driving chip 44, greatly reducing the electromagnetic interference generated by the rectifying circuit and the whole electromagnetic interference, and improving the heat conduction of the whole semiconductor circuit.
In some embodiments of the present invention, the first circuit substrate 11 and the second circuit substrate 12 are used for carrying electronic components in the semiconductor circuit, and each includes a first mounting surface on the front surface and a first heat dissipation surface on the back surface, and a second mounting surface on the front surface and a second heat dissipation surface on the back surface, where the first circuit substrate 11 and the second circuit substrate 12 may be made of a metal material or other materials, for example, a rectangular plate made of aluminum such as 1100, 5052, etc. with a thickness substantially thicker than other layers, typically 0.8mm to 2mm, and a common thickness of 1.5mm. In particular, the first circuit substrate 11 may preferably be a copper-clad substrate DBC (Direct Bonding Copper) frame structure, and the second circuit substrate 12 may preferably be an aluminum substrate IMS (Insulated Metal Substrate) frame structure, with the copper-clad substrate having better thermal conductivity than other substrate materials. Moreover, as can be seen from fig. 2, the copper-clad substrate is much thinner than the aluminum substrate in thickness, so that the heat generated by the power device on the surface is more favorably conducted to the back surface, and the back surface is exposed to the outside air or is connected with the radiator again, so that the heat generated by the power device of the rectifying circuit with large heat generation is timely transferred, the working temperature of the power device is effectively ensured to be increased in a safe range, and the working reliability of the power device is further improved. Further, the first heat dissipating surface and the second heat dissipating surface may be textured (not shown) by laser etching and polishing, and the bonding force with the sealing layer 50 may be enhanced by the texturing.
Further, insulating layers, namely, a first insulating layer 21 and a second insulating layer 21, may be provided between the first circuit substrate 11 and the first circuit wiring layer 31, and between the second circuit substrate 12 and the second circuit wiring layer 32, respectively, to realize electrical insulation between the mounting surface of the metallic circuit substrate and the metallic circuit wiring layer, and to prevent wiring short-circuiting on the circuit wiring layers. The thickness of the first insulating layer 21 and the second insulating layer 21 is relatively thin compared with the circuit substrate, generally 50um to 150um, and usually 110um. The first insulating layer 21 and the second insulating layer 21 may be made of a resin material such as epoxy resin, and fillers such as alumina and aluminum carbide may be filled inside the resin material to improve thermal conductivity. The shape of these fillers may be angular in order to increase the thermal conductivity, and spherical, angular or a mixture of angular and spherical in order to avoid the risk of the fillers damaging the contact surfaces of the electronic components arranged on the surface thereof.
The first circuit wiring layer 31 and the second circuit wiring layer 32 may be formed by etching copper foil provided on the surface of the first insulating layer 21 and the surface of the second insulating layer 21, respectively, or may be formed by printing a paste-like conductive medium, and the conductive medium may be a conductive material such as graphene, solder paste, or silver paste. The thickness of the circuit wiring layer is also substantially thinner than the insulating layer, e.g., about 70 um. The surface of the circuit wiring layer is provided with a plurality of element mounting sites 82 for mounting a plurality of electronic elements including a power device including a switching transistor such as an IGBT43 (Insulated Gate Bipolar Transistor ) or a MOS transistor (metal oxide semiconductor, metal oxide semiconductor) or the like, and a rectifier diode 41 and an FRD42 for freewheeling. Wherein the electronic component mounted on the first circuit wiring layer 31 is mainly a rectifier diode 41; the electronic components mounted on the second circuit wiring layer 32 mainly include a switching transistor and a driving chip 44, and also include other passive devices such as a resistor, a capacitor, and the like. The temperature of the whole semiconductor circuit is higher than the room temperature in the working process because the power consumed by the working of the power device is large and the heating value is large. The power device is also fixedly mounted to the component mounting locations 82 by means of metal heat sinks. These circuit wiring layers and a plurality of electronic components mounted on the circuit wiring layers constitute the entire circuit of the semiconductor circuit.
The periphery of the surfaces of the first circuit wiring layer 31 and the second circuit wiring layer 32 is also provided with a plurality of pads 81 to fix the pins 70, thereby transmitting signals to the internal circuits of the semiconductor circuit. The leads 70 are typically made of a metal such as copper, and the copper surface is formed with a nickel-tin alloy layer, typically 5 μm thick, by electroless plating and electroplating, which protects the copper from corrosion and oxidation and improves solderability.
The material of the pin 70 can be C194 (-1/2H) plate (chemical components: cu (not less than 97.0), fe (2.4), P (0.03), zn (0.12)) or KFC (-1/2H) plate (chemical components: cu (not less than 99.6), fe (0.05-0.15) and P (0.03) (0.025-0.04)), and the C194 or KFC plate with the thickness of 0.5mm is processed by a stamping or etching process, and then the surface is plated with nickel with the thickness of 0.1-0.5um and then plated with tin with the thickness of 2-5um; the excess web of pins 70 is cut and shaped to the desired shape by a specific device.
Further, a thin green oil layer (not shown) is further provided on the surfaces of the first circuit wiring layer 31 and the second circuit wiring layer 32 where the element mounting locations 82 and the pads 81 are not provided, which serves to prevent short-circuiting between the wirings of the two circuit wiring layers, and also serves to prevent oxidation and contamination of the surfaces of the circuit wiring layers, thereby protecting the surfaces.
Wherein the sealing layer 50 may be formed of a resin, molded using a thermosetting resin by a transfer molding method or molded using a thermoplastic resin by an injection molding method. The sealing layer 50 has two packaging structures, one is that the sealing layer 50 covers the surface and the back of the first circuit substrate 11 and the second circuit substrate 12, namely one surface of an electronic element arranged on the two circuit substrates and the back of the circuit substrate, and the sealing layer 50 covers the part of the length of the pin 70 connected to one end of the circuit substrate, so that the packaging is a full-coating mode of the sealing layer 50; in another packaging mode, the sealing layer 50 covers the upper surfaces of the first circuit substrate 11 and the second circuit substrate 12, namely, the surfaces of the circuit substrates and the electronic components, meanwhile, the sealing layer 50 covers part of the length of the end of the lead 70 connected to the circuit substrate, and the back surface of the circuit substrate, namely, the heat dissipation surface is exposed out of the sealing layer 50, so that a semi-coating mode of the sealing layer 50 is formed. When the texture is provided on the back surface of the circuit substrate in the full-coating manner, the bonding strength with the sealing layer 50 can be effectively enhanced, so that the circuit substrate and the sealing layer are not easy to separate. For the semi-cladding mode, the back surface of the circuit substrate is not provided with textures, and when the semiconductor circuit is used and installed, the back surface of the circuit substrate is also provided with a radiator (not shown in the figure), so that the surface of the radiator is in close contact with the surface of the circuit substrate, and the heat of the power device is radiated better through the radiator.
Preferably, in order to facilitate the heat dissipation of the power device of the rectifying circuit on the first circuit substrate 11, as shown in fig. 2, the heat dissipation surface of the first circuit substrate 11 is exposed from the sealing layer 50, that is, the sealing layer 50 is in a half-coating manner on the first circuit substrate 11, and the sealing layer 50 is in a full-coating manner on the second circuit substrate 12, because the heat dissipation density on the second circuit substrate 12 is greater than that on the first circuit substrate 11, the heat dissipation of the second circuit substrate 12 is not as high as that of the first circuit substrate 11, and therefore the full-coating manner of the sealing layer 50 on the second circuit substrate 12 can also meet the heat dissipation requirement of the second circuit substrate 12, so as to better protect the electronic components such as the driving chip 44 on the second circuit substrate 12.
Preferably, the width of the gap 90 between the first circuit substrate 11 and the second circuit substrate 12 is 0.5-4mm, e.g. 0.7mm, so that good electrical and thermal conduction isolation is maintained between the two, and it is ensured that the gap 90 does not occupy too much space inside the semiconductor circuit.
In some embodiments of the present invention, as shown in fig. 2 and 3, the semiconductor circuit further includes a plurality of bonding wires 60, and the bonding wires 60 are connected between the plurality of electronic components, the first circuit wiring layer 31 or the second circuit wiring layer 32, and the plurality of leads 70. For example, the bonding wire 60 may connect an electronic component and an electronic component, may connect an electronic component and a circuit wiring layer, and may connect an electronic component and a lead 70, and may connect a circuit wiring layer and a lead 70. The electronic components are the power devices mentioned in the above embodiments, such as the IGBT43, the flywheel diode, and the driver chip 44, and others, such as resistors, capacitors, and the like. Bond wire 60 is typically a gold wire, copper wire, gold-copper hybrid wire, a 38um or less thin aluminum wire, a 100um or more thick aluminum wire.
In some embodiments of the present invention, as shown in fig. 4, the rectifying circuit formed by the first circuit wiring layer and the electronic components disposed thereon includes a rectifying bridge stack composed of four rectifying diodes 301 to 304, having four pins. The connection point of the cathodes of the two rectifying diodes 303 and 304 is that a full-bridge direct current output end is connected with an anode output pin, the connection point of the anodes of the two rectifying diodes 301 and 302 is that a full-bridge direct current output end is connected with a cathode output pin, a common node of the cathode of the rectifying diode 302 and the anode of the rectifying diode 303 is connected with a first alternating current input pin, and a common node of the cathode of the rectifying diode 301 and the anode of the rectifying diode 304 is connected with a second alternating current input pin.
The circuit composed of the second circuit wiring layer and the electronic components arranged thereon includes a driving circuit and an inverter circuit, the driving circuit includes a driving chip 44, and the driving chip 44 is provided with at least one of an over-temperature protection switching circuit, an under-voltage protection circuit, an over-current protection circuit, and an over-voltage protection circuit (not shown in the figure). Wherein 6 IGBTs 305-310 and freewheeling diodes form an inverter circuit, the inverter circuit mainly comprises 3 groups of inverter units of an upper bridge arm and a lower bridge arm, each inverter unit comprises a three-stage transistor, in FIG. 4, an IGBT (IGBT), a MOS (metal oxide semiconductor) transistor, wherein the IGBT is a group of a triode 305 and a triode 308, a group of a triode 306 and a triode 309, a group of a triode 307 and a triode 310, each group of two triodes is divided into an upper bridge arm and a lower bridge arm, wherein the triode 305 is an upper bridge arm, the triode 308 is a lower bridge arm, the triode 306 is an upper bridge arm, the triode 309 is a lower bridge arm, the triode 307 is an upper bridge arm, the triode 310 is a lower bridge arm, the collector of the triode 305 of the upper bridge arm is connected with a high voltage input end P of the module, the emitter of the triode transistor 305 of the upper bridge arm is connected with the collector of the triode transistor 308 of the lower bridge arm, the emitter of the triode transistor 308 of the lower bridge arm is connected with the end of the module external pin UN, the grid electrodes of the two triode transistors are connected with the driving chip 44, the emitter of the triode transistor 306 of the upper bridge arm is connected with the collector of the triode transistor 309 of the lower bridge arm, the emitter of the triode transistor 309 of the lower bridge arm is connected with the end of the module external pin VN, the grid electrodes of the two triode transistors are connected with the driving chip 44, the emitter of the triode transistor 307 of the upper bridge arm is connected with the collector of the triode transistor 310 of the lower bridge arm, the emitter of the triode transistor 310 of the lower bridge arm is connected with the end of the module external pin WN, and the grid electrodes of the two triode transistors are connected with the driving chip 44.
The present invention also proposes a manufacturing method of the semiconductor circuit mentioned based on the above embodiment, as shown in fig. 5, the manufacturing method comprising the steps of:
step S100, providing a first circuit substrate and a second circuit substrate, and respectively preparing a first insulating layer and a second insulating layer on the surfaces of the first circuit substrate and the second circuit substrate;
step S200, preparing a first circuit wiring layer and a second circuit wiring layer on the surfaces of the first insulating layer and the second insulating layer respectively;
Step S300, preparing pins, wherein one ends of a plurality of pins are connected with each other through connecting ribs;
step S400, electronic components and pins are configured on the first circuit wiring layer and the second circuit wiring layer;
Step S500, the electronic element and the circuit wiring layer are electrically connected through bonding wires;
Step S600, the first circuit substrate and the second circuit substrate provided with the electronic element and the pins are subjected to injection molding through a packaging mold to form a sealing layer, wherein the sealing layer covers one surface of the first circuit substrate on which the electronic element is mounted, the other surface of the first circuit substrate is exposed from the sealing layer, the sealing layer protects the two surfaces of the second circuit substrate, and the other ends of the pins are exposed from the sealing layer;
and S700, cutting off connecting ribs among the pins to form a semiconductor circuit to be tested, carrying out parameter test on the semiconductor circuit to be tested through test equipment, and if the test is qualified, bending and forming each pin of the semiconductor circuit to be tested, which is qualified, based on a preset pin shape to obtain the qualified semiconductor circuit.
In step S100, the first circuit board 11 and the second circuit board 12 with appropriate sizes may be designed according to the required circuit layout. The first circuit substrate 11 is a copper-clad substrate DBC, and the second substrate is an aluminum substrate IMS, and the two substrates are different in thickness due to different materials, wherein the copper-clad substrate DBC is much thinner than the aluminum substrate IMS, and is more conducive to heat conduction. The two boards are different, and the areas are also different, wherein the first circuit substrate 11 is provided with only the rectifying circuit, and the area occupied by the circuit is much smaller than that of the second circuit substrate provided with the driving circuit and the inverting circuit, so that the area of the first circuit substrate 11 is smaller than that of the second circuit substrate 12, and the area of the first circuit substrate 11 is generally smaller than 1/2 of that of the second circuit substrate 12. The two are required to be processed respectively, for example, the first circuit substrate 11 can be set to be 20mm multiplied by 30mm, the second circuit substrate 12 can be set to be 40 mm multiplied by 30mm, the second circuit substrate 12 is processed for example, a gong tool can be used for carrying out gong board processing on the aluminum material with the size of 1m multiplied by 1m, the gong tool is made of high-speed steel, a motor is at a rotation speed of 5000 revolutions per minute, and the gong tool and the plane of the aluminum material form a right angle for cutting; or may be formed by stamping. Since the heat radiation surface, which is the back surface, of the second circuit board 12 is also covered with the sealing layer 50, the back surface of the second circuit board 12 may be textured with irregularities by laser etching or polishing, so that the bonding force between the back surface of the second circuit board 12 and the sealing layer 50 is enhanced by the texturing. After the first circuit substrate 11 and the second circuit substrate 12 are prepared, the first insulating layer 21 and the second insulating layer 21 are then prepared on the surfaces of the first circuit substrate 11 and the second circuit substrate 12, that is, the first mounting surface and the second mounting surface, respectively, so as to realize electrical insulation between the mounting surface of the metal circuit substrate and the metal circuit wiring layer and prevent wiring short-circuit on the circuit wiring layer. The first insulating layer 21 and the second insulating layer 21 may be made of a resin material such as epoxy resin, and fillers such as alumina and aluminum carbide may be filled inside the resin material to improve thermal conductivity.
In step S200, a metal substrate such as copper foil may be laminated on the surfaces of the first insulating layer 21 and the second insulating layer 21, respectively, and then the surface of the metal substrate is processed, for example, the copper foil is processed by etching, and the copper foil is partially removed to form the first circuit wiring layer 31 and the second circuit wiring layer 32, respectively. A plurality of element mounting sites 82 and a plurality of pads 81 are provided on these circuit wiring layers.
Further, a thinner green oil layer (not shown) may be disposed on the surfaces of the first circuit wiring layer 31 and the second circuit wiring layer 32, and the green oil layer is coated on the surfaces of these circuit wiring layers except for the component mounting locations 82 and the pads 81, so as to protect the wiring surfaces in the circuit wiring layers from oxidation and contamination, and to realize protection.
In step S300, the lead 70 may be formed by preparing a copper substrate, for example, by forming a strip shape with a length C of 25mm, a width K of 1.5mm, and a thickness H of 1mm, and then forming a nickel layer on the surface of the lead 70 by electroless plating: the nickel layer is formed on the surface of the copper material with a specific shape by mixing the nickel salt and the sodium hypophosphite and adding a proper complexing agent, the metal nickel has strong passivation capability, and an extremely thin passivation film can be rapidly formed, so that the corrosion of atmosphere, alkali and certain acid can be resisted. The nickel plating crystal is extremely fine, and the thickness of the nickel layer is generally 0.1 mu m; then, through an acidic sulfate process, the copper material with the formed shape and the nickel layer is immersed in a plating solution with positive tin ions at room temperature for electrifying, a nickel-tin alloy layer is formed on the surface of the nickel layer, the thickness of the nickel layer is generally controlled to be 5 mu m, and the formation of the nickel layer greatly improves the protectiveness and the weldability. As shown in fig. 6, in order to limit the spacing between the pins 70, a specific mold is used to press the second ends of the pins 70 to form the connection ribs 71, so that a plurality of pins 70 can be quickly installed on the circuit substrate, thereby completing the preparation of the pins 70.
In step S400, first, the surfaces of the component mounting locations 82 and the pads 81 of the first circuit wiring layer 31 and the second circuit wiring layer 32 are solder-coated by a solder paste printer using a steel mesh, which may be used with a thickness of 0.13mm, where the component mounting locations 82 and the pads 81 need to be solder-soldered, such as the component mounting locations 82 for soldering electronic components, the pads 81 for soldering the pins 70, and the like. Or a silver paste dispenser, a specific pattern is coated on the element mounting position 82 and the bonding pad 81 by silver paste, and the electronic element and the pin 70 can be welded on the positions by silver paste.
Then, electronic components and pins 70 are mounted, the electronic components can be directly placed at the component mounting positions 82, one ends of the pins 70 are to be placed on the bonding pads 81, the other ends of the pins need to be fixed by a carrier, the carrier is made of materials such as synthetic stone and stainless steel, and the pins 70 are conveniently fixed at the positions of the bonding pads 81 due to the connection effect of the reinforcing ribs. Then, the first circuit substrate 11 and the second circuit substrate 12 placed on the carrier are cured by reflow soldering, solder paste or silver paste, and the electronic component and the leads 70 are soldered to the component mounting sites 82 and the pads 81, respectively.
In step S500, the step is a step of connecting the bonding wire 60. One of the drive bond pads 81 of the drive chip 44 traces in the electronic component may be directly connected to the gate bond pad of the power device such as IGBT43 by a wire 60 of gold, copper, gold-copper, 38um or less, and the like, and the other drive bond pads 81 of the drive chip 44 may be directly connected to the bond pad 81 of the circuit wiring layer by a wire 60 of gold, copper, gold-copper, 38um or less, and the like. The emitter bonding area of the IGBT43 is directly connected to the pad 81 of the circuit wiring layer through a thick aluminum line of 100um or more. Through these steps, the rectifying circuit region 101 is constituted by the first circuit substrate 11, the first insulating layer 21, the first circuit wiring layer 31, and the electronic components provided on the circuit wiring layer, and the driving and inverting circuit region 102 is constituted by the second circuit substrate 12, the second insulating layer 21, the second circuit wiring layer 32, and the electronic components provided on the circuit wiring layer.
In step S600, this step is a step of forming the sealing layer 50. The first circuit substrate 11 and the second circuit substrate 12 on which the electronic components, the pins 70, are mounted during the above steps may be baked first in an oxygen-free atmosphere. The first circuit board 11 and the second circuit board 12 on which the leads 70 are disposed are then carried into a packaging mold composed of an upper mold and a lower mold by means of a carrier, the leads 70 are fixedly disposed between the upper mold and the lower mold, then the packaging mold in which these circuit boards are placed is clamped, a mold cavity is formed in the packaging mold, sealing resin is sealed in the mold cavity by means of a gate, and finally, the mold is released, after the mold release, the sealing resin is cured to form the sealing layer 50, and the free ends of the leads 70 are exposed from the sealing layer 50.
In step S700, the connection rib 71 connecting the other ends of the plurality of pins 70 is cut off to form the semiconductor circuit to be tested, wherein the connection rib 71 is a residue generated during the preparation of the pins 70, and the connection rib 71 may cause a short circuit between the pins 70 and 70, so that the connection rib 71 needs to be cut off during the preparation of the semiconductor circuit. In one example, the connection rib 71 connecting the second ends of the plurality of pins 70 may be cut off by a specific device so that the other ends of the pins 70 are not connected to each other, and the semiconductor circuit to be tested is obtained, so that the semiconductor circuit to be tested is subjected to parameter test in the next step.
The test equipment can be used for carrying out parameter test on the semiconductor circuit to be tested, for example, the test equipment can send test signals to the semiconductor circuit to be tested and receive feedback signals fed back by the semiconductor circuit to be tested; the test equipment processes the feedback signal to obtain corresponding feedback data, compares the feedback data with a preset threshold range, and judges that the semiconductor circuit to be tested is qualified when the feedback data meets the preset threshold range, so that each pin 70 of the semiconductor circuit to be tested, which is qualified in test, can be bent and molded based on the shape of the preset pin 70, and a qualified semiconductor circuit is obtained.
Further, before the testing device can be used for testing parameters of the semiconductor circuit to be tested, laser marking can be performed by the laser device to mark the surface of the sealing layer 50 of the semiconductor circuit, so that the semiconductor circuit product can be identified and managed conveniently.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings are merely for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the device or element being referred to must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the present invention.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present invention, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically defined otherwise.
In the present invention, unless explicitly specified and limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; either directly or indirectly, through intermediaries, or both, may be in communication with each other or in interaction with each other, unless expressly defined otherwise. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.
In the present invention, unless expressly stated or limited otherwise, a first feature "up" or "down" a second feature may be the first and second features in direct contact, or the first and second features in indirect contact via an intervening medium. Moreover, a first feature being "above," "over" and "on" a second feature may be a first feature being directly above or obliquely above the second feature, or simply indicating that the first feature is level higher than the second feature. The first feature being "under", "below" and "beneath" the second feature may be the first feature being directly under or obliquely below the second feature, or simply indicating that the first feature is less level than the second feature.
While embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and not to be construed as limiting the invention, and that variations, modifications, alternatives and variations may be made to the above embodiments by one of ordinary skill in the art within the scope of the invention.
Claims (10)
1. A semiconductor circuit having a rectifying circuit, comprising:
The first circuit substrate and the second circuit substrate are arranged at intervals left and right and respectively comprise a first mounting surface, a first radiating surface, a second mounting surface and a second radiating surface;
A first circuit wiring layer and a second circuit wiring layer, wherein the first circuit wiring layer is arranged on the first mounting surface, the second circuit wiring layer is arranged on the second mounting surface, and a plurality of element mounting positions and a plurality of bonding pads are respectively arranged on the first mounting surface and the second mounting surface;
A plurality of electronic components respectively arranged on the first circuit wiring layer and the second circuit wiring layer, wherein the first circuit wiring layer and the electronic components arranged thereon form a rectifying circuit, and the second circuit wiring layer and the electronic components arranged thereon form an inverter circuit and a driving circuit;
a plurality of pins, one ends of which are electrically connected with the first circuit wiring layer and the second circuit wiring layer respectively;
A sealing layer which wraps at least one surface of the first circuit substrate and the second circuit substrate on which the electronic component is disposed, and from which the other ends of the plurality of leads are exposed;
the rectifying circuit consists of a first circuit wiring layer and electronic elements arranged on the first circuit wiring layer, and comprises a rectifying bridge stack consisting of four rectifying diodes, and four leading-out pins are arranged on the rectifying circuit; the connection point of the cathodes of the two rectifying diodes is a full-bridge direct-current output end which is connected with an anode output pin, the connection point of the anodes of the two rectifying diodes is a full-bridge direct-current output end which is connected with a cathode output pin, the common node of the cathodes of the rectifying diodes and the anodes of the rectifying diodes is connected with a first alternating-current input pin, and the common node of the cathodes of the rectifying diodes and the anodes of the rectifying diodes is connected with a second alternating-current input pin.
2. The semiconductor circuit of claim 1, wherein,
The heat dissipation surface of the first circuit substrate is exposed from the sealing layer, and the heat dissipation surface of the second circuit substrate is covered by the sealing layer.
3. The semiconductor circuit of claim 1, wherein,
The gap between the first circuit substrate and the second circuit substrate is in the range of 0.5-4mm.
4. The semiconductor circuit of claim 1, wherein,
The area of the first circuit substrate is smaller than 1/2 of the area of the second circuit substrate.
5. The semiconductor circuit according to claim 1, wherein a first insulating layer is further provided between the first circuit substrate and the first circuit wiring layer, and a second insulating layer is further provided between the second circuit substrate and the second circuit wiring layer.
6. The semiconductor circuit according to claim 1, wherein a green oil layer is further provided on surfaces of the first circuit wiring layer and the second circuit wiring layer where no component mounting position and pad are provided.
7. The semiconductor circuit of claim 1, further comprising a plurality of bond wires for connecting the plurality of electronic components.
8. The semiconductor circuit of claim 7, wherein the bond wire is gold wire, copper wire, gold-copper hybrid wire, 38um or less fine aluminum wire, 100um or more coarse aluminum wire.
9. The semiconductor circuit according to claim 1, wherein the surface of the pin is provided with an alloy layer having a thickness of 5 μm.
10. A method for manufacturing a semiconductor circuit according to any one of claims 1 to 9, characterized in that the method comprises:
Providing a first circuit substrate and a second circuit substrate, and respectively preparing a first insulating layer and a second insulating layer on the surfaces of the first circuit substrate and the second circuit substrate;
preparing a first circuit wiring layer and a second circuit wiring layer on the surfaces of the first insulating layer and the second insulating layer respectively;
preparing pins, wherein one ends of the pins are connected with each other through connecting ribs;
disposing electronic components and pins on the first circuit wiring layer and the second circuit wiring layer;
the electronic element and the circuit wiring layer are electrically connected through a bonding wire;
Injection molding the first circuit substrate and the second circuit substrate provided with the electronic element and the pins through a packaging mold to form a sealing layer, wherein the sealing layer covers one surface of the first circuit substrate on which the electronic element is mounted, the other surface of the first circuit substrate is exposed from the sealing layer, the sealing layer protects two surfaces of the second circuit substrate, and the other ends of the plurality of pins are exposed from the sealing layer;
Cutting off the connecting ribs among the pins to form a semiconductor circuit to be tested, carrying out parameter test on the semiconductor circuit to be tested through test equipment, and if the test is qualified, bending and forming each pin of the semiconductor circuit to be tested which is qualified according to the preset pin shape to obtain the qualified semiconductor circuit.
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| CN113314515B (en) * | 2021-06-09 | 2024-09-27 | 广东汇芯半导体有限公司 | Semiconductor circuit and method for manufacturing semiconductor circuit |
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