CN116313750A - Method for protecting high-temperature annealing surface of silicon carbide chip - Google Patents
Method for protecting high-temperature annealing surface of silicon carbide chip Download PDFInfo
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- CN116313750A CN116313750A CN202310012548.7A CN202310012548A CN116313750A CN 116313750 A CN116313750 A CN 116313750A CN 202310012548 A CN202310012548 A CN 202310012548A CN 116313750 A CN116313750 A CN 116313750A
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- silicon carbide
- temperature annealing
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- 238000000137 annealing Methods 0.000 title claims abstract description 49
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 47
- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 46
- 238000000034 method Methods 0.000 title claims abstract description 38
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims abstract description 42
- 229910052799 carbon Inorganic materials 0.000 claims abstract description 41
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 22
- 238000005468 ion implantation Methods 0.000 claims abstract description 19
- 230000008569 process Effects 0.000 claims abstract description 17
- 150000002500 ions Chemical class 0.000 claims abstract description 13
- 239000012535 impurity Substances 0.000 claims abstract description 10
- 238000004528 spin coating Methods 0.000 claims abstract description 9
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 16
- 239000004065 semiconductor Substances 0.000 claims description 13
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 8
- 229910052757 nitrogen Inorganic materials 0.000 claims description 8
- 239000013078 crystal Substances 0.000 claims description 6
- 230000007547 defect Effects 0.000 claims description 5
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 claims description 4
- 229910052786 argon Inorganic materials 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 4
- 230000005669 field effect Effects 0.000 claims description 3
- 229910044991 metal oxide Inorganic materials 0.000 claims description 3
- 150000004706 metal oxides Chemical class 0.000 claims description 3
- 230000015556 catabolic process Effects 0.000 abstract description 3
- 230000006872 improvement Effects 0.000 abstract description 3
- 229910052710 silicon Inorganic materials 0.000 abstract description 3
- 239000010703 silicon Substances 0.000 abstract description 3
- 238000000859 sublimation Methods 0.000 abstract description 3
- 230000008022 sublimation Effects 0.000 abstract description 3
- 238000006731 degradation reaction Methods 0.000 abstract description 2
- 239000011241 protective layer Substances 0.000 description 7
- 239000010410 layer Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 238000007788 roughening Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 230000004913 activation Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 125000004432 carbon atom Chemical group C* 0.000 description 1
- 238000003763 carbonization Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000004134 energy conservation Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 229910021389 graphene Inorganic materials 0.000 description 1
- 238000005087 graphitization Methods 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 230000005596 ionic collisions Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000010295 mobile communication Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 238000005979 thermal decomposition reaction Methods 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
- H01L21/0455—Making n or p doped regions or layers, e.g. using diffusion
- H01L21/046—Making n or p doped regions or layers, e.g. using diffusion using ion implantation
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The invention relates to a method for protecting a high-temperature annealing surface of a silicon carbide chip, which comprises the following steps: spin coating photoresist on the front surface of the silicon carbide chip before high-temperature annealing after ion implantation; baking and curing, and spin-coating the other surface; forming uniform carbon films on the front and back sides of the wafer by an annealing method; the wafer on which the carbon film is deposited is annealed at a high temperature to activate impurity ions. The invention provides a high-temperature annealing surface protection method for a silicon carbide chip, which effectively inhibits the sublimation and redeposition processes of silicon on the surface of a silicon carbide wafer and slows down the degradation of the appearance of the silicon carbide surface in high-temperature annealing after ion implantation; compared with a sample without carbon film protection, the surface morphology after annealing is obviously improved, and the improvement of the device performance is facilitated.
Description
Technical Field
The invention belongs to the field of semiconductors, and particularly relates to a method for protecting a high-temperature annealing surface of a silicon carbide chip.
Background
The third-generation semiconductor material represented by silicon carbide (SiC) has the advantages of large forbidden bandwidth, high breakdown electric field, high thermal conductivity, high electron saturation drift rate, strong radiation resistance and the like, is a 'core' of a solid-state light source, a power electronic and microwave radio frequency device, has wide application prospect in the fields of semiconductor illumination, new-generation mobile communication, high-speed rail transit, new energy automobiles, consumer electronics and the like, is expected to break through the bottleneck of the traditional semiconductor technology, is complementary with the first-generation and second-generation semiconductor technology, and plays an important role in energy conservation and emission reduction, industrial transformation upgrading, and new economic growth promotion.
The doping method of the semiconductor device mainly comprises diffusion and ion implantation, wherein charged ions with certain energy are doped into silicon carbide, the implantation energy is between 1keV and 1MeV, and the corresponding average ion distribution depth ranges from 10nm to 10 um. Compared with the diffusion process, the ion implantation has the main advantages that the impurity doping amount can be controlled accurately, good repeatability is maintained, and meanwhile, the processing process temperature of the ion implantation is lower than that of diffusion. The energetic ions, after entering the semiconductor, eventually end up at a depth within the lattice. The negative effects of ion implantation are mainly due to breakage or damage of the semiconductor lattice caused by ion collisions, so that an annealing treatment must be performed in a subsequent process to eliminate such damage.
The mobility and lifetime of the semiconductor are severely affected by lattice damage caused by high-energy ion implantation, and most of ions are not in place during implantation, so that the semiconductor must be annealed at a proper time and temperature in order to activate the implanted ions and recover mobility and other relevant parameters.
In the preparation process of the silicon carbide chip, the activation of doped impurities after ion implantation and the damage of a crystal structure caused in the implantation process are required to be carried out at an annealing process temperature of more than 1400-1900 ℃. However, at such high temperatures, silicon atoms in the silicon carbide will overflow from the silicon carbide in a sublimating manner, leaving carbon atoms in the form of graphene remaining on the crystal face of the silicon carbide, thereby causing surface carbonization and roughening of the surface with steps or gully textures, which is a major defect caused by the high-temperature annealing process after the silicon carbide ion implantation; further, the surface roughening further worsens with an increase in the annealing temperature.
Disclosure of Invention
In view of the above, an object of the present invention is to provide a method for protecting a silicon carbide wafer surface by high-temperature annealing, which is capable of depositing a carbon film protective layer on the silicon carbide wafer surface to solve the problems of sublimation of silicon, surface graphitization and surface roughening during high-temperature annealing.
In order to achieve the above purpose, the following technical scheme is adopted:
a method for high temperature annealing surface protection of silicon carbide chips, comprising the steps of:
spin coating photoresist on the front surface of the silicon carbide chip before high-temperature annealing after ion implantation;
baking and curing, and spin-coating the other surface;
forming uniform carbon films on the front and back sides of the wafer by an annealing method;
the wafer on which the carbon film is deposited is annealed in a high-temperature annealing furnace to activate impurity ions.
Preferably, the silicon carbide chip is a schottky diode or a metal-oxide semiconductor field effect transistor.
Preferably, the photoresist is positive photoresist or negative photoresist, the low-temperature baking temperature is 150-180 ℃, and the baking time is 5-10 minutes.
Preferably, the process of depositing the carbon film is as follows:
baking the photoresist on the front side and the back side of the silicon carbide chip in a high-temperature annealing furnace at 800-1000 ℃ for 30-60 minutes to form a uniform carbon film;
the annealing process in the high-temperature annealing furnace is performed under the protection of vacuum argon and high-purity nitrogen.
Preferably, the silicon carbide chip deposited with the carbon film is annealed in a high-temperature annealing furnace at 1400-1900 ℃ for 20-40 minutes to recover the crystal structure and eliminate defects and activate impurity ions.
Preferably, the carbon film on the front and back surfaces is removed by a dry photoresist remover, and the process environment is baking for 600-900s under the pure oxygen and high-purity nitrogen environment at 50-100 ℃ so that the carbon film is completely oxidized, and finally the carbon film is removed.
The beneficial effects of the invention are as follows:
the invention provides a high-temperature annealing surface protection method for a silicon carbide chip, which effectively inhibits the sublimation and redeposition processes of silicon on the surface of a silicon carbide wafer and slows down the degradation of the appearance of the silicon carbide surface in high-temperature annealing after ion implantation; compared with a sample without carbon film protection, the surface morphology after annealing is obviously improved, and the improvement of the device performance is facilitated.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention. In the drawings:
fig. 1 is a schematic structure of a silicon carbide schottky diode of the present invention with a carbon film deposited after ion implantation and before high temperature annealing.
Wherein, the reference numerals are as follows: 11-front carbon film protective layer, 2-P+ ion implantation region, 3-N-epitaxial layer, 4-N+ silicon carbide substrate, 12-back carbon film protective layer.
Detailed Description
It should be noted that, in the case of no conflict, the embodiments and features in the embodiments may be combined with each other. The invention will be described in detail below with reference to the drawings in connection with embodiments.
In order to make the present application solution better understood by those skilled in the art, the following description will be made in detail and with reference to the accompanying drawings in the embodiments of the present application, it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, shall fall within the scope of the present application.
A method for high temperature annealing surface protection of silicon carbide chips, comprising the steps of:
spin coating photoresist on the front surface of the silicon carbide chip before high-temperature annealing after ion implantation;
baking and curing, and spin-coating the other surface;
forming uniform carbon films on the front and back sides of the wafer by an annealing method;
the wafer on which the carbon film is deposited is annealed at a high temperature to activate impurity ions.
The silicon carbide chip is a schottky diode or a metal-oxide semiconductor field effect transistor.
The photoresist is positive photoresist or negative photoresist, the low-temperature baking temperature is 150-180 ℃, and the baking time is 5-10 minutes.
The process for depositing the carbon film comprises the following steps:
baking the photoresist on the front side and the back side of the silicon carbide chip in a high-temperature annealing furnace at 800-1000 ℃ for 30-60 minutes to form a uniform carbon film;
the annealing process in the high-temperature annealing furnace is performed under the protection of vacuum argon and high-purity nitrogen.
The silicon carbide chip deposited with the carbon film is annealed in a high-temperature annealing furnace at 1400-1900 ℃ for 20-40 minutes to recover the crystal structure, eliminate defects and activate impurity ions.
And (3) removing the carbon films on the front and back surfaces by using a dry photoresist remover, wherein the process environment is baking for 600-900s under the pure oxygen and high-purity nitrogen environment at 50-100 ℃ so that the carbon films are completely oxidized, and finally removing the carbon films.
Examples:
in the preparation process of the silicon carbide Schottky diode, an active region and a field limiting ring are subjected to an ion implantation doping process, a carbon film is deposited on the surface of a wafer for protection, and then high-temperature annealing is carried out at the temperature of 1750 ℃.
In this embodiment, the silicon carbide epitaxial wafer adopts N-type doped epitaxy, the ion implantation region is P-type doped, as shown in the schematic cross-sectional view of the process steps shown in fig. 1, 3 is an N-type epitaxial layer, and 2 is a P-type ion implantation region.
In this embodiment, the photoresist on the front and back sides of the silicon carbide chip after ion implantation is spin-coated respectively, and the thickness is 2.6 micrometers. The front surface is coated first and baked at 180 ℃ for 10 minutes.
And spin-coating photoresist on the back surface, and then placing the silicon carbide chip into a high-temperature annealing furnace for annealing, wherein the temperature is 800 ℃ and the temperature is kept for 45 minutes. A dense carbon film protective layer is formed on the front surface carbon film protective layer 11 and the back surface carbon film protective layer 12 of the silicon carbide chip by thermal decomposition.
And annealing the silicon carbide chip deposited with the carbon film protective layer for 30 minutes at 1750 ℃ in a vacuum, argon and high-purity nitrogen protective environment so as to recover the structure of the crystal, eliminate defects and activate impurity ions.
After high-temperature annealing, pure oxygen and high-purity nitrogen are introduced into a dry photoresist remover at 70 ℃ and baked for 780s, so that the carbon film is completely oxidized, and finally the carbon films of the front carbon film protection layer 11 and the back carbon film protection layer 12 of the silicon carbide chip are removed.
The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (6)
1. A method for high temperature annealing surface protection of silicon carbide chips, comprising the steps of:
spin coating photoresist on the front surface of the silicon carbide chip before high-temperature annealing after ion implantation;
baking and curing, and spin-coating the other surface;
forming uniform carbon films on the front and back sides of the wafer by an annealing method;
the wafer on which the carbon film is deposited is annealed in a high-temperature annealing furnace to activate impurity ions.
2. The method of claim 1, wherein the silicon carbide chip is a schottky diode or a metal-oxide semiconductor field effect transistor.
3. The method for protecting a high-temperature annealed surface of a silicon carbide chip according to claim 1, wherein the photoresist is positive photoresist or negative photoresist, the low-temperature baking temperature is 150-180 ℃, and the baking time is 5-10 minutes.
4. The method of claim 1, wherein the process of depositing the carbon film is:
baking the photoresist on the front side and the back side of the silicon carbide chip in a high-temperature annealing furnace at 800-1000 ℃ for 30-60 minutes to form a uniform carbon film;
the annealing process in the high-temperature annealing furnace is performed under the protection of vacuum argon and high-purity nitrogen.
5. The method for high temperature annealing surface protection of silicon carbide chip according to claim 1, wherein said silicon carbide chip deposited with carbon film is annealed in a high temperature annealing furnace at 1400-1900 ℃ for 20-40 minutes to recover crystal structure and eliminate defects and activate impurity ions.
6. The method for protecting the high-temperature annealing surface of the silicon carbide chip according to claim 1, wherein the carbon film on the front and back surfaces is removed by a dry photoresist remover, and the process environment is baking for 600-900s in a pure oxygen and high-purity nitrogen environment at 50-100 ℃ so that the carbon film is completely oxidized, and finally the carbon film is removed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310012548.7A CN116313750A (en) | 2023-01-05 | 2023-01-05 | Method for protecting high-temperature annealing surface of silicon carbide chip |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310012548.7A CN116313750A (en) | 2023-01-05 | 2023-01-05 | Method for protecting high-temperature annealing surface of silicon carbide chip |
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| CN116313750A true CN116313750A (en) | 2023-06-23 |
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| CN202310012548.7A Pending CN116313750A (en) | 2023-01-05 | 2023-01-05 | Method for protecting high-temperature annealing surface of silicon carbide chip |
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| CN (1) | CN116313750A (en) |
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- 2023-01-05 CN CN202310012548.7A patent/CN116313750A/en active Pending
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