CN113990918B - Vertical III-nitride power semiconductor device with stepped shielding ring and preparation method thereof - Google Patents
Vertical III-nitride power semiconductor device with stepped shielding ring and preparation method thereof Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 11
- 238000002360 preparation method Methods 0.000 title abstract description 6
- 150000004767 nitrides Chemical class 0.000 claims abstract description 78
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 229910002601 GaN Inorganic materials 0.000 claims description 85
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 54
- 238000000034 method Methods 0.000 claims description 34
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims description 24
- 229910001425 magnesium ion Inorganic materials 0.000 claims description 24
- 238000005530 etching Methods 0.000 claims description 21
- JLVVSXFLKOJNIY-UHFFFAOYSA-N Magnesium ion Chemical compound [Mg+2] JLVVSXFLKOJNIY-UHFFFAOYSA-N 0.000 claims description 18
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 claims description 17
- 238000005468 ion implantation Methods 0.000 claims description 15
- 230000008569 process Effects 0.000 claims description 15
- 229910021529 ammonia Inorganic materials 0.000 claims description 12
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 10
- 238000001312 dry etching Methods 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 10
- 239000010703 silicon Substances 0.000 claims description 10
- 239000012159 carrier gas Substances 0.000 claims description 9
- 238000000137 annealing Methods 0.000 claims description 8
- 238000004519 manufacturing process Methods 0.000 claims description 8
- 238000004151 rapid thermal annealing Methods 0.000 claims description 8
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052757 nitrogen Inorganic materials 0.000 claims description 6
- 239000012298 atmosphere Substances 0.000 claims description 5
- 150000002500 ions Chemical class 0.000 claims description 5
- 239000007789 gas Substances 0.000 claims description 4
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 3
- 230000003213 activating effect Effects 0.000 claims description 3
- 229910052786 argon Inorganic materials 0.000 claims description 3
- 239000001257 hydrogen Substances 0.000 claims description 3
- 229910052739 hydrogen Inorganic materials 0.000 claims description 3
- 238000002513 implantation Methods 0.000 claims description 3
- 238000011065 in-situ storage Methods 0.000 claims description 3
- 239000000203 mixture Substances 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- 235000012239 silicon dioxide Nutrition 0.000 claims description 3
- 239000000395 magnesium oxide Substances 0.000 claims description 2
- CPLXHLVBOLITMK-UHFFFAOYSA-N magnesium oxide Inorganic materials [Mg]=O CPLXHLVBOLITMK-UHFFFAOYSA-N 0.000 claims description 2
- AXZKOIWUVFPNLO-UHFFFAOYSA-N magnesium;oxygen(2-) Chemical compound [O-2].[Mg+2] AXZKOIWUVFPNLO-UHFFFAOYSA-N 0.000 claims description 2
- 230000010354 integration Effects 0.000 claims 1
- 238000004088 simulation Methods 0.000 abstract description 7
- 238000004458 analytical method Methods 0.000 abstract description 4
- 238000004364 calculation method Methods 0.000 abstract description 2
- 230000015556 catabolic process Effects 0.000 description 30
- 230000004888 barrier function Effects 0.000 description 22
- 230000005684 electric field Effects 0.000 description 15
- 230000000694 effects Effects 0.000 description 12
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 8
- 235000011114 ammonium hydroxide Nutrition 0.000 description 8
- 238000010438 heat treatment Methods 0.000 description 8
- XCZXGTMEAKBVPV-UHFFFAOYSA-N trimethylgallium Chemical compound C[Ga](C)C XCZXGTMEAKBVPV-UHFFFAOYSA-N 0.000 description 8
- 230000000903 blocking effect Effects 0.000 description 7
- 238000009616 inductively coupled plasma Methods 0.000 description 7
- 238000004220 aggregation Methods 0.000 description 6
- 230000002776 aggregation Effects 0.000 description 6
- 238000001035 drying Methods 0.000 description 6
- 239000011777 magnesium Substances 0.000 description 6
- 239000000463 material Substances 0.000 description 6
- 238000009826 distribution Methods 0.000 description 5
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 4
- KFZMGEQAYNKOFK-UHFFFAOYSA-N Isopropanol Chemical compound CC(C)O KFZMGEQAYNKOFK-UHFFFAOYSA-N 0.000 description 4
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 description 4
- 239000008367 deionised water Substances 0.000 description 4
- 229910021641 deionized water Inorganic materials 0.000 description 4
- 238000011010 flushing procedure Methods 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- 229910052749 magnesium Inorganic materials 0.000 description 4
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 4
- GETQZCLCWQTVFV-UHFFFAOYSA-N trimethylamine Chemical compound CN(C)C GETQZCLCWQTVFV-UHFFFAOYSA-N 0.000 description 4
- 238000000927 vapour-phase epitaxy Methods 0.000 description 4
- 230000004913 activation Effects 0.000 description 3
- UOSXPFXWANTMIZ-UHFFFAOYSA-N cyclopenta-1,3-diene;magnesium Chemical compound [Mg].C1C=CC=C1.C1C=CC=C1 UOSXPFXWANTMIZ-UHFFFAOYSA-N 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 238000000407 epitaxy Methods 0.000 description 3
- INQLNSVYIFCUML-QZTLEVGFSA-N [[(2r,3s,4r,5r)-5-(6-aminopurin-9-yl)-3,4-dihydroxyoxolan-2-yl]methoxy-hydroxyphosphoryl] [(2r,3s,4r,5r)-5-(4-carbamoyl-1,3-thiazol-2-yl)-3,4-dihydroxyoxolan-2-yl]methyl hydrogen phosphate Chemical compound NC(=O)C1=CSC([C@H]2[C@@H]([C@H](O)[C@@H](COP(O)(=O)OP(O)(=O)OC[C@@H]3[C@H]([C@@H](O)[C@@H](O3)N3C4=NC=NC(N)=C4N=C3)O)O2)O)=N1 INQLNSVYIFCUML-QZTLEVGFSA-N 0.000 description 2
- 238000000861 blow drying Methods 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
- 238000004381 surface treatment Methods 0.000 description 2
- 238000004506 ultrasonic cleaning Methods 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
- H01L29/0623—Buried supplementary region, e.g. buried guard ring
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- H01L29/66196—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices with an active layer made of a group 13/15 material
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Abstract
The invention relates to a vertical III-nitride power semiconductor device with a stepped shielding ring and a preparation method thereof, wherein the vertical III-nitride power semiconductor device sequentially comprises a cathode electrode, a heavily doped N-nitride substrate region, a lightly doped N-nitride drift region, a heavily doped P-nitride region and an anode electrode from bottom to top, wherein a lightly doped P-nitride shielding ring is embedded below the heavily doped P-nitride region in the lightly doped N-nitride drift region; through a large number of simulation calculation analyses, the lightly doped P-type nitride shielding ring is embedded in the lightly doped N-type nitride drift region, so that the reverse voltage withstand capability of the device can be greatly improved on the premise of keeping the size of the device unchanged, and meanwhile, the reverse leakage is further reduced, so that the device can be applied to a higher voltage scene.
Description
Technical Field
The invention relates to a III-nitride vertical power device structure with a shielding ring structure, and a preparation method and application thereof, and belongs to the technical field of semiconductor devices.
Background
Compared with the first generation semiconductor represented by silicon and the second generation semiconductor represented by gallium arsenide, the third generation semiconductor represented by silicon carbide and III nitride has wide application prospect in the fields of high-frequency communication, power electronics and the like due to the excellent characteristics of large forbidden band width, high critical breakdown field strength, high thermal conductivity, high electron saturation drift rate and the like.
Currently, gallium nitride-based devices that can be widely used are mainly lateral high electron mobility transistors (High Electron Mobility Transistors, HEMT). However, the main disadvantage of the lateral device is that the reverse breakdown voltage of the device is proportional to the electrode spacing in the lateral direction of the device, resulting in a larger device size for high voltage operation scenario applications, which greatly increases the process manufacturing cost of the device. In order to solve the problem, the fully vertical device can realize larger reverse breakdown voltage by increasing the vertical drift layer thickness of the device, effectively avoid current crowding effect in a transverse structure and a quasi-vertical structure, and reduce forward on-resistance.
In the reverse blocking process of the device, excellent reverse breakdown characteristics can be realized by adjusting the electric field distribution inside the device uniformly, but in the optimization process of the structural parameters of the device, the phenomenon of advanced breakdown of the device caused by local electric field aggregation can be generated.
Schottky barrier diodes are an important component of modern power electronics systems because of their reduced voltage, fast switching speed, etc. In order to meet the application of consumer electronics and high-frequency communication devices, the traditional Schottky diode has higher requirements in high-voltage and high-power application scenes, and the performance limit of the devices is also more and more prominent.
In a high reverse bias scenario, planar schottky barrier diodes (Planar Schottky Barrier Diode, SBD) tend to produce significant barrier lowering effects due to strong electric field concentrations below the schottky contact barrier, thereby producing large reverse leakage currents that limit the reverse breakdown characteristics of the schottky barrier diode. This problem can be solved by using a hybrid PiN junction barrier schottky diode (Merged PiN Schottky diode, MPS diode) new structure. Compared with the traditional planar Schottky barrier diode, the gallium nitride vertical mixed PiN junction barrier Schottky diode can effectively modulate electric field distribution below a Schottky contact barrier, and can form a good electric field shielding effect on the Schottky contact barrier by utilizing the superposition of depletion regions of adjacent PN junctions, so that the problems of large leakage current and advanced breakdown caused by barrier reduction effect are avoided. However, when the doping concentration of p-GaN is too high, strong electric field aggregation occurs at the corners of the bottom of the p-GaN structure, thereby again causing early breakdown of the device and limiting the reverse blocking performance of the device.
Disclosure of Invention
Aiming at the defects of the prior art, the invention provides a III-nitride vertical power device structure with a shielding ring structure; the invention provides a technical scheme for effectively solving the problem of local electric field aggregation of a gallium nitride vertical mixed PiN junction barrier Schottky diode under the condition of p-GaN high doping, which comprises the following steps:
1. the shallow doped stepped shielding ring structure below the heavily doped p-GaN is realized by a growth method of secondary epitaxy or multiple epitaxy and ion implantation, the depletion effect of the shielding ring can effectively relieve the strong electric field aggregation at the corner of the bottom of the heavily doped p-GaN structure, and an electric field shielding protection effect is formed on the heavily doped p-GaN structure;
2. the parameters (magnesium ion doping concentration, upper step thickness and lower step thickness) of the p-GaN shallow doped stepped shielding ring are optimized, so that the greatly improved reverse blocking characteristic is obtained. The physical mechanism of the device structure is that the shallow doped p-GaN and the n-type drift layer form a space charge depletion region of a PN junction, and the width of the space charge depletion region can be changed along with the change of reverse bias voltage, so that the concentrated local electric field is dispersed, the electric field distribution is more uniform, and the purpose of improving the reverse breakdown voltage of the device is achieved.
Term interpretation:
1. dry etching is a technique of etching a thin film with plasma.
2. MOCVD is a novel Vapor Phase Epitaxy (VPE) technology developed on the basis of the MOCVD furnace Vapor Phase Epitaxy (VPE).
The technical scheme of the invention is as follows:
the III-nitride vertical power device structure with the shielding ring structure sequentially comprises a cathode electrode, a heavily doped N-type nitride substrate region, a lightly doped N-type nitride drift region, a heavily doped P-type nitride region and an anode electrode from bottom to top, wherein a lightly doped P-type nitride shielding ring is embedded below the heavily doped P-type nitride region in the lightly doped N-type nitride drift region;
according to the invention, the lightly doped P-type nitride shielding ring is in a ladder shape, and the thickness T of the upper ladder is equal to that of the lower ladder 1 Thickness T of the lower step is 0.5-2.0 μm 2 The width W of the lower step is 1.0-4.0 mu m and is 1.0-10.0 mu m;
most preferably, the thickness T of the upper step 1 Thickness T of the lower step of 2.0 μm 2 The width W of the lower step was 8.0 μm and 2. Mu.m.
According to the invention, the doping concentration of magnesium ions in the lightly doped P-type nitride shielding ring is 1e15cm -3 -5e17cm -3 。
Further preferably, the doping concentration of magnesium ions in the lightly doped P-type nitride shielding ring is 1e16cm -3 -8e16cm -3 。
Most preferably, the lightly dopedThe doping concentration of magnesium ions in the P-type nitride shielding ring is 3e16cm -3 。
According to the invention, the heavily doped N-type nitride substrate region is a heavily doped N-type gallium nitride substrate region, the lightly doped N-type nitride drift region is a lightly doped N-type gallium nitride drift region, and the heavily doped P-type nitride region is a heavily doped P-type gallium nitride region.
The preparation method of the III-nitride vertical power device structure with the shielding ring structure comprises the following steps:
(1) Sequentially growing a heavily doped N-type nitride substrate region and a lightly doped N-type nitride drift region on the cathode electrode;
(2) Performing ICP etching on the lightly doped N-type nitride drift region, and performing secondary epitaxial growth to form a stepped lightly doped P-type nitride shielding ring;
(3) And continuing to epitaxially grow a heavily doped P-type nitride region and an anode electrode in sequence to obtain the semiconductor device.
According to the invention, in the step (2), the step of forming the stepped lightly doped P-type nitride shielding ring by performing the secondary epitaxial growth comprises the following specific implementation steps:
(1) etching a groove region on the lightly doped N-type nitride drift region by using a dry etching process, and performing damage treatment on the etched surface;
(2) the silicon dioxide is used as a hard mask to shield an unetched lightly doped N-type nitride drift region, ammonia is used as an N source, magnesium oxide is used as a doping source, and H 2 As carrier gas, adopting MOCVD method to homoepitaxial a layer of P-type nitride on the upper surface of lightly doped N-type nitride drift region;
(3) and (3) in-situ annealing in the MOCVD furnace, activating P-type doped magnesium ions, and growing to form a stepped lightly doped P-type nitride shielding ring.
According to the invention, in the step (2), after performing ICP etching, a step-shaped lightly doped P-type nitride shielding ring is formed by performing multiple epitaxial and ion implantation processes, and the specific implementation steps comprise:
A. etching a groove region on the lightly doped N-type nitride drift region by using a dry etching process, and performing damage treatment on the etched surface;
B. carrying out Mg ion implantation on the bottom surface of the groove area of the lightly doped N-type nitride drift region by using an ion implanter, wherein the power energy of the ion implantation is set to be 150-300 keV, and the implantation depth is 0.3-0.6 mu m;
C. carrying out rapid thermal annealing treatment in a gas atmosphere of a mixture of one or more than two of nitrogen, ammonia, argon and hydrogen in any proportion, wherein the temperature range of the rapid thermal annealing treatment is 400-1500 ℃ and the annealing time is 10-90 min;
D. epitaxially growing N-type nitride with thickness of 0.3-0.6 μm by MOCVD method, and doping concentration of silicon of 2e16cm -3 ；
E. Repeating the steps B to D for a plurality of times until the lightly doped P-type nitride shielding ring with the specified thickness is generated.
The group iii nitride material system may be a gallium nitride material.
The III-nitride vertical power device structure with the shielding ring structure is applied to high-frequency, high-voltage and high-power electronics and integrated systems.
The beneficial effects of the invention are as follows:
1. according to the invention, the stepped shallow doped stepped p-GaN region is arranged at the bottom of the heavily doped p-GaN region of the vertical hybrid Pin junction barrier Schottky diode, so that a shielding ring structure is formed, and the problem of local electric field aggregation at the corner of the heavily doped p-GaN region is effectively solved, thereby improving the reverse blocking performance of the device.
2. The invention utilizes ICP dry etching to form a groove region, and then uses MOCVD to epitaxially grow a shallow doped stepped p-GaN shielding ring. The preparation method is suitable for a III nitride system, the process is relatively simple, the activation efficiency is high, and the obtained P-type structure is stable. The relevant processes to which the present invention relates are well known to those skilled in the art, as are the specific process conditions and deposition temperatures.
Drawings
FIG. 1 is a schematic diagram of a hybrid PIN junction barrier Schottky diode with a shallow doped stepped p-GaN shield ring according to the present invention;
fig. 2 is a schematic structural diagram of a conventional planar hybrid PiN junction barrier schottky diode;
fig. 3 is a graph of magnesium doping concentration versus reverse breakdown voltage of the device for a stepped p-GaN shield ring.
FIG. 4 is a graph of the upper step thickness of a stepped p-GaN shield ring versus the reverse breakdown voltage of the device;
fig. 5 is a graph of the downstep thickness of a stepped p-GaN shield ring versus the reverse breakdown voltage of the device.
Detailed Description
The invention is further defined by, but is not limited to, the following drawings and examples in conjunction with the specification.
Example 1
As shown in FIG. 1, the III-nitride vertical power device structure with the shielding ring structure sequentially comprises a cathode electrode, a heavily doped N-type gallium nitride substrate region, a lightly doped N-type gallium nitride drift region, a heavily doped P-type gallium nitride region and an anode electrode from bottom to top, wherein a lightly doped P-type gallium nitride shielding ring is embedded below the heavily doped P-type gallium nitride region in the lightly doped N-type gallium nitride drift region; the shallow doped stepped p-GaN shielding ring is positioned below the heavily doped p-GaN, can form a PN junction with the n-type shallow doped drift layer, and can regulate and control a strong electric field at the corner of the heavily doped p-GaN structure under the depletion effect.
The structure of the conventional planar hybrid PiN junction barrier schottky diode is shown in fig. 2, and is obtained through a great amount of simulation calculation and analysis, and a lightly doped P-type gallium nitride shielding ring is embedded in a lightly doped N-type gallium nitride drift region, so that the reverse voltage endurance of the device can be greatly improved on the premise that the size of a holding device is unchanged, and meanwhile, reverse leakage is further reduced, so that the device can be applied to a higher voltage scene.
Example 2
A group iii nitride vertical power device structure having a shield ring structure according to embodiment 1, which is different in that:
the lightly doped P-type gallium nitride shielding ring is stepped and has the thickness T of the upper step 1 Thickness T of the lower step is 0.5-2.0 μm 2 The width W of the lower step is 1.0-4.0 mu m and is 1.0-10.0 mu m; the doping concentration of magnesium ions in the lightly doped P-type gallium nitride shielding ring is 1e15cm -3 -5e17cm -3 。
When the thickness T of the step is 1 、T 2 When the value is larger, the shielding ring structure is deeper into the device, the depletion region can be expanded to the deep part of the drift layer, and the region bearing voltage is increased, so that higher reverse breakdown voltage can be realized. The effective depletion protection effect of the shielding ring structure can be ensured by selecting the doping concentration of magnesium ions, so that the phenomenon that the depletion effect of the shielding ring is too small and negligible when the concentration is too low and the local electric field aggregation is caused by the strong depletion effect when the concentration is too high, thereby leading to the advanced breakdown of the device is avoided.
Example 3
A group iii nitride vertical power device structure having a shield ring structure according to embodiment 2, which is different in that:
thickness T of the upper step 1 Thickness T of the lower step of 2.0 μm 2 The width W of the lower step was 8.0 μm and 2. Mu.m.
The doping concentration of magnesium ions in the lightly doped P-type gallium nitride shielding ring is 3e16cm -3 。
The thickness of the heavily doped N-type gallium nitride substrate area is 2 mu m, the doping element is silicon, and the doping concentration is 5e18cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The thickness of the lightly doped N-type gallium nitride drift region is 15 mu m, the doping element is silicon, and the doping concentration is 2e16cm -3 . The heavily doped P-type gallium nitride region has a square structure, a depth of 2 μm and a width of 4 μm, and doped ions are Mg ions with a doping concentration of 1e18cm -3 . The intermediate schottky contact width was set to 2 μm.
Example 4
The method for manufacturing a group iii nitride vertical power device structure with a shielding ring structure according to any one of embodiments 1 or 2, includes the steps of:
(1) Sequentially growing a heavily doped N-type gallium nitride substrate region and a lightly doped N-type gallium nitride drift region on the cathode electrode;
(2) Performing ICP etching on the lightly doped N-type gallium nitride drift region, and performing secondary epitaxial growth to form a stepped lightly doped P-type gallium nitride shielding ring; obtaining the vertical MPS diode with the shallow doped stepped p-GaN shielding ring; the MOCVD is utilized to carry out secondary epitaxial growth, the outline between the material layers is clear, the distribution is uniform, and the lattice damage of the material in the ion implantation mode is avoided.
The specific implementation steps comprise:
(1) etching a groove region on the lightly doped N-type gallium nitride drift region by using a dry etching process, and performing damage treatment on the etched surface;
(2) the silicon dioxide is used as a hard mask to shield the unetched lightly doped N-type gallium nitride drift region, and ammonia (NH) 3 ) As N source, magnesium dicyclopentadiene (Cp 2 Mg) as doping source, H 2 As carrier gas, adopting MOCVD method to homoepitaxial a layer of P-type gallium nitride on the upper surface of lightly doped N-type gallium nitride drift region;
(3) and (3) in-situ annealing in the MOCVD furnace, activating P-type doped magnesium ions, and growing to form a stepped lightly doped P-type gallium nitride shielding ring.
(3) And continuing to epitaxially grow a heavily doped P-type gallium nitride region and an anode electrode in sequence to obtain the semiconductor device.
Example 5
The method for manufacturing a group iii nitride vertical power device structure with a shield ring structure according to example 4 is different in that:
in the step (2), after performing ICP etching, performing multiple epitaxial and ion implantation processes to grow to form a stepped lightly doped P-type gallium nitride shielding ring, wherein the specific implementation steps comprise:
A. etching a groove region on the lightly doped N-type gallium nitride drift region by using a dry etching process, and performing damage treatment on the etched surface;
B. carrying out Mg ion implantation on the bottom surface of the groove area of the lightly doped N-type gallium nitride drift region by utilizing an ion implanter, wherein the power energy of the ion implantation is set to be 150-300 keV, and the implantation depth is 0.3-0.6 mu m;
C. carrying out rapid thermal annealing treatment in a gas atmosphere of a mixture of one or more than two of nitrogen, ammonia, argon and hydrogen in any proportion, wherein the temperature range of the rapid thermal annealing treatment is 400-1500 ℃ and the annealing time is 10-90 min; so as to improve the activation rate of Mg ions in gallium nitride;
D. epitaxially growing N-type gallium nitride with thickness of 0.3-0.6 μm by MOCVD method, and doping concentration of silicon being 2e16cm -3 ；
E. And (3) repeating the steps B to D for a plurality of times until the lightly doped P-type gallium nitride shielding ring with the specified thickness is generated.
The ion implantation process realizes no interface between the implanted layer and the matrix, high bonding strength and good adhesiveness, and does not change the outline dimension and the surface finish of the device.
Example 6
The method for manufacturing the group iii nitride vertical power device structure with the shielding ring structure of embodiment 3 includes the following steps:
(1) Respectively using trimethyl ammonium (TMGa), ammonia (NH) 3 ) As Ga source and N source, S i H 3 CH 3 As N-type impurity source, H 2 As carrier gas, low defect, low dislocation heavily doped N-type gallium nitride substrate region with thickness of 2 μm and silicon doping concentration of 5e18cm are realized in MOCVD -3 ；
(2) Respectively using trimethyl ammonium (TMGa), ammonia (NH) 3 ) As Ga source and N source, S i H 3 CH 3 As N-type impurity source, H 2 As carrier gas, lightly doped N-type gallium nitride drift region with thickness of 15 μm is homoepitaxial on the surface of heavily doped N-type gallium nitride substrate region, and the doping concentration of silicon is 2e16cm -3 ；
(3) Using S on epitaxial wafer i O 2 The hard mask plate is used for shielding the part of the epitaxial wafer which is not etched, and the mask plate is formed in Cl 2 /BCl 3 Performing step groove region etching by utilizing Inductively Coupled Plasma (ICP) in the mixed atmosphere of Ar;
(4) After dry etching, a large number of peaks and burrs with slopes exist on the surface of the material, a sample is placed into a 25% TMAH solution, and the sample is treated for 1 hour at the temperature of 85 ℃ to remove surface damage caused by etching: then placing the sample into acetone and heating to 85 ℃, and heating in a water bath for 10 minutes; ultrasonic cleaning with isopropanol for 5 minutes, flushing with deionized water for 6 times, drying with nitrogen, and drying with a hot plate; heating an ammonia water solution with the concentration of 25wt% to 85 ℃ in a water bath, putting a sample into the water bath, and heating the sample in the water bath for 10 minutes; taking out the sample from the ammonia water, then flushing the sample for 6 times by using deionized water, removing the ammonia water on the surface, stopping the surface treatment effect of the ammonia water, and drying the sample by using a hot plate after blow-drying; testing etching depth and etching morphology by using an atomic force microscope;
(5) Using trimethylgallium (TMGa), magnesium dicyclopentadiene (Cp) 2 Mg) and ammonia (NH) 3 ) Respectively as Ga, mg and N sources, H 2 As carrier gas, the MOCVD method is utilized to homoepitaxially grow a P-type shallow doped gallium nitride layer in the stepped groove area to form a stepped shielding ring, and the doping concentration interval of magnesium is 1e16cm -3 -8e16cm -3 ；
(6) And continuing to epitaxially grow a heavily doped P-type gallium nitride region and an anode electrode in sequence.
Example 7
The method for manufacturing a group iii nitride vertical power device structure with a shielding ring structure of embodiment 3, which is manufactured by using a multiple epitaxy and ion implantation method, includes the following steps:
(1) Respectively using trimethyl ammonium (TMGa), ammonia (NH) 3 ) As Ga source and N source, S i H 3 CH 3 As N-type impurity source, H 2 As carrier gas, low defect, low dislocation N-type heavily doped gallium nitride substrate layer with thickness of 2 μm and doping concentration of silicon of 5e18cm is realized in MOCVD -3 ；
(2) Respectively using trimethyl ammonium (TMGa), ammonia (NH) 3 ) As Ga source and N source, S i H 3 CH 3 As N-type impurity source, H 2 As carrier gas, an N-type lightly doped gallium nitride drift layer with the thickness of 15 mu m is homoepitaxial on the surface of an N-type heavily doped gallium nitride substrate layer, and the doping concentration of silicon is 2e16cm -3 ；
(3) Using S on epitaxial wafer i O 2 The hard mask plate is used for shielding the etching-free area of the epitaxial wafer, and the etching-free area is formed inCl 2 /BCl 3 Performing step groove region etching by utilizing Inductively Coupled Plasma (ICP) in the mixed atmosphere of Ar;
(4) After dry etching, a large number of peaks and burrs with slopes exist on the surface of the material, a sample is placed into a 25% TMAH solution, and the sample is treated for 1 hour at the temperature of 85 ℃ to remove surface damage caused by etching: then placing the sample into acetone and heating to 85 ℃, and heating in a water bath for 10 minutes; ultrasonic cleaning with isopropanol for 5 minutes, flushing with deionized water for 6 times, drying with nitrogen, and drying with a hot plate; heating an ammonia water solution with the concentration of 25wt% to 85 ℃ in a water bath, putting a sample into the water bath, and heating the sample in the water bath for 10 minutes; taking out the sample from the ammonia water, then flushing the sample for 6 times by using deionized water, removing the ammonia water on the surface, stopping the surface treatment effect of the ammonia water, and drying the sample by using a hot plate after blow-drying; testing etching depth and etching morphology by using an atomic force microscope;
(5) Ammonia (NH) gas using trimethylgallium (TMGa) 3 ) Respectively as Ga source and N source, H 2 As carrier gas, using MOCVD method to homoepitaxially grow 300-500 nm thick N-type gallium nitride layer in stepped groove region;
(6) Carrying out Mg ion implantation on the N-type gallium nitride layer epitaxially grown at the bottom of the stepped groove by using an ion implanter, adjusting the energy of the ion implantation, realizing that a P-type gallium nitride layer with the thickness of 300-500 nm is used as a shielding ring area, and then removing SiO on the surface 2 And (3) carrying out a rapid thermal annealing (PIA) treatment on the hard mask, wherein the rapid thermal annealing treatment is carried out in a nitrogen atmosphere, the high-temperature annealing temperature range is 450 ℃, and the annealing time is 20 minutes, so that the hole activation rate in the P-type gallium nitride layer is improved.
(7) Repeating the step (5) and the step (6) for a plurality of times to grow a p-GaN shielding ring with a specified thickness;
(8) And continuing to epitaxially grow a heavily doped P-type gallium nitride region and an anode electrode in sequence.
Example 8
Variation example 1 magnesium ion doping concentration of the shield ring in a planar hybrid PiN junction barrier schottky diode structure with a shallow doped stepped p-GaN shield ring (variation range 1e16cm -3 -8e16cm -3 ) A graph of reverse breakdown voltage of the device versus magnesium ion doping concentration in the shallow doped stepped p-GaN shield ring region is obtained by numerical simulation, as shown in fig. 3.
The reverse breakdown voltage of a conventional planar hybrid PiN junction barrier schottky diode without a shield ring structure is 1123V, which is used as a reference, is noted in fig. 3. At this time, the concentration of the N-type shallow doped drift layer is set to be 2e16cm -3 . Compared with the reverse breakdown voltage (1123V) of the traditional planar hybrid Pin junction barrier Schottky diode, the device with the shallow doped stepped p-GaN shielding ring shows higher reverse breakdown voltage; further, the optimal magnesium ion doping concentration is 3e16cm -3 . As the magnesium ion doping concentration increases, the reverse breakdown voltage shows a tendency to increase and decrease, but both show a reverse breakdown voltage value higher than 1123V. The result analysis of TCAD simulation shows that after the stepped shielding ring structure is provided, reverse breakdown voltage can be effectively improved, better reverse blocking characteristics are shown, and better reverse voltage withstand capability can be further realized by optimizing the doping concentration of magnesium ions. The merits of the reverse blocking performance are mainly represented by the magnitude of the reverse breakdown voltage.
Example 9
The upper step thickness of the shield ring (variation range is 0.5 μm-2.0 μm) in the planar hybrid PiN junction barrier schottky diode structure with the shallow doped stepped p-GaN shield ring in variation example 1, and the relationship between the reverse breakdown voltage of the device and the upper step thickness of the shallow doped stepped p-GaN shield ring was obtained through numerical simulation, as shown in fig. 4. At the moment, the magnesium doping concentration of the stepped p-GaN shielding ring is set to be 4e16cm -3 。T 1 The larger the value of (c) exhibits a higher reverse breakdown voltage. With the increase of the step thickness on the shielding ring, the reverse breakdown voltage shows a monotonically rising trend, at T 1 At 2.0 μm, a reverse breakdown voltage of up to 1811V is achieved.
Example 10
Variation example 1 planar hybrid PiN junction barrier schottky diode with shallow doped stepped p-GaN shield ring the shield ring has a downstep thickness (variation rangeThe circumference is 1-10 μm), and a graph of the reverse breakdown voltage of the device and the lower step thickness of the shallow doped stepped p-GaN shielding ring is obtained through numerical simulation, as shown in fig. 5. At the moment, the magnesium doping concentration of the stepped p-GaN shielding ring is set to be 4e16cm -3 。T 2 The larger the value of (c) shows a higher reverse breakdown voltage and tends to saturate when its width reaches 8 μm, and the device internal structure shows a p-GaN shield ring lower step close to the n-type heavily doped substrate region. With the increase of the thickness of the step below the shielding ring, the reverse breakdown voltage shows a nearly monotonically rising trend, at T 2 At 10 μm, a reverse breakdown voltage of up to 2381V is achieved. The result analysis through TCAD simulation can obtain, and the deeper step thickness can realize the dark depletion region degree of depth, and effective utilization N type lightly doped gallium nitride drift layer comes even electric field distribution to realize better reverse blocking performance.
Claims (10)
1. The III-nitride vertical power device structure with the shielding ring structure is characterized by comprising a cathode electrode, a heavily-doped N-type nitride substrate region, a lightly-doped N-type nitride drift region, a heavily-doped P-type nitride region and an anode electrode from bottom to top in sequence, wherein a lightly-doped P-type nitride shielding ring is embedded below the heavily-doped P-type nitride region in the lightly-doped N-type nitride drift region;
the lightly doped P-type nitride shielding ring is stepped and has the thickness T of the upper step 1 Thickness T of the lower step is 0.5-2.0 μm 2 The width W of the lower step is 1.0-4.0 μm and is 1.0-10.0 μm.
2. The group iii nitride vertical power device structure with shield ring structure of claim 1, wherein the thickness T of the upper step 1 Thickness T of the lower step of 2.0 μm 2 The width W of the lower step was 8.0 μm and 2. Mu.m.
3. The group iii nitride vertical power device structure with shield ring structure of claim 1, wherein the lightly doped P-type nitride shieldThe doping concentration of magnesium ions in the ring is 1e15cm -3 -5e17cm -3 。
4. The vertical power device structure of group iii nitride with shielding ring structure of claim 1, wherein the doping concentration of magnesium ions in the lightly doped P-type nitride shielding ring is 1e16cm -3 -8e16cm -3 。
5. The group iii nitride vertical power device structure of claim 1, wherein the magnesium ion doping concentration in the lightly doped P-type nitride shield ring is 3e16cm -3 。
6. The vertical power device structure of claim 1, wherein the heavily doped N-type nitride substrate region is a heavily doped N-type gallium nitride substrate region, the lightly doped N-type nitride drift region is a lightly doped N-type gallium nitride drift region, and the heavily doped P-type nitride region is a heavily doped P-type gallium nitride region.
7. The method for manufacturing a group iii nitride vertical power device structure having a shield ring structure as set forth in any one of claims 1 to 6, comprising the steps of:
(1) Sequentially growing a heavily doped N-type nitride substrate region and a lightly doped N-type nitride drift region on the cathode electrode;
(2) Performing ICP etching on the lightly doped N-type nitride drift region, and performing secondary epitaxial growth to form a stepped lightly doped P-type nitride shielding ring;
(3) And continuing to epitaxially grow a heavily doped P-type nitride region and an anode electrode in sequence to obtain the semiconductor device.
8. The method for manufacturing a group iii nitride vertical power device structure with a shielding ring structure according to claim 7, wherein in the step (2), the step of performing a second epitaxial growth to form a stepped lightly doped P-type nitride shielding ring, the specific implementation steps include:
(1) etching a groove region on the lightly doped N-type nitride drift region by using a dry etching process, and performing damage treatment on the etched surface;
(2) the silicon dioxide is used as a hard mask to shield an unetched lightly doped N-type nitride drift region, ammonia is used as an N source, magnesium oxide is used as a doping source, and H 2 As carrier gas, adopting MOCVD method to homoepitaxial a layer of P-type nitride on the upper surface of lightly doped N-type nitride drift region;
(3) and (3) in-situ annealing in the MOCVD furnace, activating P-type doped magnesium ions, and growing to form a stepped lightly doped P-type nitride shielding ring.
9. The method for manufacturing a group iii nitride vertical power device structure with a shielding ring structure according to claim 7, wherein in the step (2), after performing ICP etching, a step-shaped lightly doped P-type nitride shielding ring is formed by performing epitaxial and ion implantation for a plurality of times, and the specific implementation steps include:
A. etching a groove region on the lightly doped N-type nitride drift region by using a dry etching process, and performing damage treatment on the etched surface;
B. carrying out Mg ion implantation on the bottom surface of the groove area of the lightly doped N-type nitride drift region by using an ion implanter, wherein the power energy of the ion implantation is set to be 150-300 keV, and the implantation depth is 0.3-0.6 mu m;
C. carrying out rapid thermal annealing treatment in a gas atmosphere of a mixture of one or more than two of nitrogen, ammonia, argon and hydrogen in any proportion, wherein the temperature range of the rapid thermal annealing treatment is 400-1500 ℃ and the annealing time is 10-90 min;
D. epitaxially growing N-type nitride with thickness of 0.3-0.6 μm by MOCVD method, and doping concentration of silicon is 2e16cm -3 ；
E. Repeating the steps B to D for a plurality of times until the lightly doped P-type nitride shielding ring with the specified thickness is generated.
10. Use of a group iii nitride vertical power device structure with a shield ring structure according to any of claims 1-6, characterized in that the group iii nitride vertical power device structure with a shield ring structure is used in high frequency, high voltage and high power electronics and integration systems.
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