CN115036220A - Gallium nitride electronic device and preparation method thereof - Google Patents
Gallium nitride electronic device and preparation method thereof Download PDFInfo
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Abstract
The invention discloses a gallium nitride electronic device and a preparation method thereof. The preparation method comprises the following steps: providing an epitaxial structure layer, wherein the epitaxial structure layer comprises a lightly doped GaN layer, an aluminum-containing III-group nitride semiconductor insertion layer and a p-type GaN layer which are sequentially stacked on a substrate; processing a designated region on the surface of the p-type GaN layer to form a groove structure in the designated region on the surface of the p-type GaN layer, and exposing part of the aluminum-containing group III nitride semiconductor insertion layer from the groove structure; forming a first electrode in the groove structure, wherein the first electrode and the insertion layer form Schottky contact; and manufacturing a second electrode and a third electrode which form ohmic contact with the epitaxial structure layer. The gallium nitride electronic device provided by the embodiment of the invention can overcome the defects of the prior art and has the advantages of stable and controllable junction region, good forward conduction, high reverse withstand voltage, good forward current transverse expansion and the like.
Description
Technical Field
The invention particularly relates to a gallium nitride electronic device and a preparation method thereof, belonging to the technical field of semiconductors.
Background
Currently, power conversion devices are primarily based on first generation semiconductor silicon (Si) material devices. However, as the social requirements for electric energy conversion devices are continuously increased, the performance of silicon devices is closer to the theoretical limit determined by the materials, and thus the application requirements cannot be met. Third generation semiconductor materials, represented by gallium nitride (GaN), are rapidly becoming the first choice for high frequency and high power electronic products due to their excellent material properties (e.g., high critical breakdown field strength, high electron saturation drift rate, etc.). Compared with Si and SiC materials, the GaN material has ultrahigh Baliga advantage value (BFOM), so that the GaN-based power switch device has the same reverse breakdown voltage V B In turn, has a lower on-resistance Ron than Si and SiC devices, and thus lower power loss.
The basic structure of GaN-based power electronic devices can be divided into lateral and vertical structures; the transverse power device based on the AlGaN/GaN heterojunction mainly works by two-dimensional electron gas (2DEG) with high density and high mobility at the heterojunction interface, and has the advantages of high switching speed and small series resistance; however, the device with lateral structure has the challenge of reliability and manufacturing cost, and the voltage resistance is easily affected by surface electric field (V) B Oc Ec · d), the anode-cathode distance d needs to be increased in order to increase the device withstand voltage; this leads to an increase in device size and cost; compared with a transverse structure, the peak electric field of the vertical structure device is far away from the surface, the current density in the drift region is uniform, and the device has good heat dissipation performance and high reliability.
As a typical representative of vertical devices, a GaN-based Schottky Barrier Diode (SBD) has a low on-voltage (<1V) and operates on multi-carrier, no conductive modulation effect, and a very high switching frequency; however, due to surface states, mirror image forces, and the like, GaN-based SBDs have large reverse leakage and severely limited withstand voltage. Compared with the prior art, the Pin power diode bears voltage by virtue of a PN junction, has small reverse leakage and high reverse withstand voltage, but has large GaN forbidden band width, so that the forward starting voltage of the device is usually large (> 3V).
In order to improve the reverse withstand voltage while maintaining the turn-on voltage, a novel GaN-based vertical power device is developed: junction Barrier Schottky (JBS) power diodes, sometimes also referred to as hybrid PiN/Schottky (MPS) power diodes. The anode region of the device is of a PN alternating grid structure, and when the device is conducted in the forward direction, the Schottky junction is mainly started, so that the conduction voltage is low and is similar to SBD; when a reverse bias is added, the depletion regions of adjacent PN junctions expand, so that a high electric field region is transferred from the surface to the body, the leakage is small, the reverse withstand voltage is high, and the diode is similar to a PiN diode. As shown in fig. 1, the JBS combines the advantages of the SBD and PiN devices, and avoids the disadvantages of the SBD and PiN devices, and has the significant advantages of small forward turn-on voltage, fast switching frequency, and high reverse withstand voltage.
At present, the preparation of GaN-based JBS mainly adopts three technical paths:
(1) selective area doping, as shown in fig. 2, forming a local Mg-doped lightly doped GaN layer mainly by a selective area Mg ion implantation manner, and then annealing at high temperature to form local p-type GaN, thereby forming an effective local PN junction depletion region on the GaN-based SBD; the technology is mature in the preparation of Si or SiC-based JBS devices. However, it is very difficult to realize GaN-based JBS using this method, mainly because: 1) the injection of a large amount of Mg ions can cause lattice damage (donor-type nitrogen vacancies) to GaN, thereby compensating Mg acceptors and influencing the hole concentration of pGaN; 2) the Mg acceptor injected into the GaN needs to be annealed and activated under extremely high temperature (>1000 ℃) and high pressure conditions, the annealing conditions are severe, and the GaN surface is easy to degrade; 3) in the process of activating Mg by high-temperature annealing, Mg ions are diffused to easily cause drift of a PN junction area, so that the forward opening and closing of a device are influenced;
(2) firstly, etching a groove by a dry method and then carrying out secondary epitaxy on pGaN, as shown in FIG. 3, firstly, etching a selected area to generate a groove, and then carrying out secondary epitaxy on pGaN in the groove; the difficulty of preparing the JBS by the method is that 1) the dry etching damage in the groove is difficult to repair well, and the quality of a groove PN junction is influenced; 2) the interface impurity contamination in the groove is serious due to the high-temperature decomposition of the mask medium in the secondary epitaxial growth process; 3) the growth anisotropy of GaN in the groove is realized, the difference between the growth rate and Mg doping efficiency of p-type GaN on the side wall (non-polar surface) and the bottom (polar surface) of the groove is large, and the quality of a PN junction is seriously influenced;
(3) the closest implementation scheme to the invention is as follows: for example, in patent CN 110752260 a, p-type GaN is grown at one time, and then a p-type GaN floating island (n-lightly doped GaN layer is exposed) is formed by dry etching, thereby effectively avoiding the problems of secondary epitaxy of pGaN grooves and Mg activation, greatly reducing the process difficulty and complexity, and the principle is shown in fig. 4; however, this solution, although the process difficulty is greatly reduced, faces the following problems:
1) the depth of the pGaN groove is difficult to be accurately controlled, and pGaN is usually required to be over-etched in order to expose the surface of the n-lightly doped GaN layer to prepare Schottky contact, so that the pinch-off effect of the lateral expansion (red dotted line region) of the PN junction depletion region under reverse bias voltage on the Schottky depletion region is weakened or even eliminated, the electric field of the Schottky depletion region cannot be shielded, and no substantial help is brought to the improvement of withstand voltage.
2) The surface etching damage of the etching groove is difficult to repair, and the Schottky contact is obviously influenced; interface state defects such as etching damage (N vacancy) and the like on the surface of the N-lightly doped GaN layer can pin a Fermi level to cause the Schottky barrier height to be reduced, and can assist electrons hopping and tunneling to cause reverse leakage of Schottky contact to be increased, so that the voltage resistance of a device is influenced.
3) The forward on and reverse off characteristics of the device cannot be synchronously optimized; for the GaN-based groove structure JBS, although the p-n junction pinch-off effect at both sides of the groove can suppress the decrease of the schottky barrier height caused by the image force, the schottky barrier height is still an important factor for determining the reverse leakage of the device in nature. The Schottky barrier height in the groove is increased unilaterally, so that off-state leakage can be reduced, but the turn-on voltage is increased, and the forward turn-on and reverse turn-off characteristics of the device cannot be improved synchronously.
As described above, although the technical solution for preparing the JBS by dry etching of pGaN can avoid the problems of secondary epitaxy of pGaN grooves and Mg activation, it still suffers from a number of pain points such as uncontrollable groove depth, high interface state density, and inability to synchronously improve on-off characteristics, and the performance of the actual device is greatly reduced compared with the ideal situation.
Disclosure of Invention
The invention mainly aims to provide a gallium nitride electronic device and a preparation method thereof, so as to overcome the defects in the prior art.
In order to achieve the purpose, the technical scheme adopted by the invention comprises the following steps:
an embodiment of the present invention provides a method for manufacturing a gallium nitride electronic device, including:
providing an epitaxial structure layer, wherein the epitaxial structure layer comprises a lightly doped GaN layer, an aluminum-containing III-group nitride semiconductor insertion layer and a p-type GaN layer which are sequentially stacked on a substrate;
processing a designated region on the surface of the p-type GaN layer to form a groove structure in the designated region on the surface of the p-type GaN layer and a floating island structure in a region other than the designated region, and partially exposing the aluminum-containing group III nitride semiconductor insertion layer from the groove structure;
forming a first electrode in the groove structure, and enabling the first electrode and the aluminum-containing group III nitride semiconductor insertion layer to form Schottky contact; and
and manufacturing a second electrode and a third electrode, wherein the second electrode and the third electrode are in ohmic contact with the epitaxial structure layer.
The embodiment of the invention also provides a gallium nitride electronic device prepared by the preparation method.
Compared with the prior art, the invention has the advantages that:
1) according to the preparation method of the gallium nitride electronic device, provided by the embodiment of the invention, the accurate control of the depth of the groove can be realized by introducing the Al-containing III-group nitride semiconductor insertion layer;
2) according to the preparation method of the gallium nitride electronic device provided by the embodiment of the invention, interface etching damage can be effectively repaired and interface state density is reduced by a thermal decomposition method;
3) according to the preparation method of the gallium nitride electronic device, provided by the embodiment of the invention, the Schottky contact barrier between metal and GaN can be improved by introducing the Al-containing III-group nitride semiconductor insertion layer, so that the reverse withstand voltage capability is improved;
4) according to the preparation method of the gallium nitride electronic device, provided by the embodiment of the invention, the width of a Schottky depletion region is reduced by effectively utilizing a polarization electric field between Al-containing III-group nitride semiconductor/GaN (typically AlGaN/GaN), so that forward electron tunneling is enhanced, the starting voltage is reduced, and the forward and reverse characteristics of the device are synchronously improved;
5) according to the preparation method of the gallium nitride electronic device, provided by the embodiment of the invention, the forward current expansion can be enhanced by effectively utilizing the polarization electric field induced 2DEG between the Al-containing III-group nitride semiconductor/GaN (such as AlGaN/GaN), and the on-resistance of the device is reduced.
Drawings
FIG. 1 is a graph comparing I-V characteristics of SBD, Pin, JBS vertical power devices;
FIG. 2 is a schematic diagram of a technical principle of implementing JBS by Mg ion implantation in the prior art;
FIG. 3 is a schematic diagram of a technical principle of realizing JBS by combining dry etching with secondary epitaxy in the prior art;
FIG. 4 is a schematic diagram of the technical principle of realizing JBS by dry etching pGaN in the prior art;
FIG. 5 is a schematic structural diagram of a method for achieving precise control of etch depth through an Al-containing etch-resistant group III nitride semiconductor in accordance with an exemplary embodiment of the present invention;
FIG. 6 is a schematic diagram of an electronic device with a GaN all-vertical structure according to an exemplary embodiment of the present invention;
FIG. 7 is a schematic view of an epitaxial structure of an electronic device with a GaN full-vertical structure according to an exemplary embodiment of the invention;
FIG. 8 is a schematic structural view of a mask pattern fabricated on the surface of an Al-containing group III-nitride semiconductor cap layer in accordance with an exemplary embodiment of the present invention;
FIG. 9 is a schematic structural diagram of a p-type GaN substrate after selective etching to form a groove structure in an exemplary embodiment of the invention;
FIG. 10 is a schematic structural view after removing the p-type GaN mask medium and repairing the etching damage of the p-type GaN sidewall by wet etching in an exemplary embodiment of the invention;
FIG. 11 is a schematic view showing the structure of an exemplary embodiment of the present invention after the thermal decomposition process removes p-type GaN in the groove structure and exposes the Al-containing group III nitride semiconductor insertion layer;
FIG. 12 is a schematic diagram illustrating a structure after an anode Schottky contact metal is deposited within the recessed structures in accordance with an exemplary embodiment of the present invention;
FIG. 13 is a schematic diagram of the final device structure after ohmic contact electrodes are formed on the p-type GaN layer and the backside of the substrate in accordance with an exemplary embodiment of the invention;
FIG. 14 is a schematic structural diagram of an electronic device with a GaN quasi-vertical structure according to an exemplary embodiment of the invention;
FIG. 15 is a schematic view of an epitaxial structure of a GaN quasi-vertical structure electronic device provided in an exemplary embodiment of the invention;
FIG. 16 is a schematic structural view after completing the preparation of a mask pattern on the surface of an Al-containing group III nitride semiconductor cap layer and selectively etching to expose an n + GaN epitaxial layer in an exemplary embodiment of the invention;
FIG. 17 is a schematic diagram illustrating a groove structure formed by selectively etching a p-type GaN layer according to an exemplary embodiment of the invention;
FIG. 18 is a schematic structural diagram of a p-type GaN layer after removing the mask medium on the surface of the p-type GaN layer and repairing the etching damage on the sidewall of the groove structure in the p-type GaN layer by wet etching in an exemplary embodiment of the invention;
FIG. 19 is a schematic diagram showing the structure after the thermal decomposition process removes the remaining p-type GaN in the trench structure and deposits an anode Schottky metal in accordance with one exemplary embodiment of the present invention;
fig. 20 is a schematic view of the final device structure after ohmic contact electrodes are formed on the p-type GaN layer and the n + GaN epitaxial layer in accordance with an exemplary embodiment of the present invention.
Detailed Description
In view of the deficiencies in the prior art, the inventors of the present invention have made extensive studies and extensive practices to provide technical solutions of the present invention. The technical solution, its implementation and principles, etc. will be further explained as follows.
An embodiment of the present invention provides a method for manufacturing a gallium nitride electronic device, including:
providing an epitaxial structure layer, wherein the epitaxial structure layer comprises a lightly doped GaN layer, an aluminum-containing III-group nitride semiconductor insertion layer and a p-type GaN layer which are sequentially stacked on a substrate;
processing a designated region on the surface of the p-type GaN layer to form a groove structure in the designated region on the surface of the p-type GaN layer, and form a floating island structure in a region outside the designated region, and partially expose the aluminum-containing group III nitride semiconductor insertion layer from the groove structure;
forming a first electrode in the groove structure and enabling the first electrode to form a Schottky contact with the aluminum-containing III-nitride semiconductor insertion layer; and
and manufacturing a second electrode and a third electrode, wherein the second electrode and the third electrode are in ohmic contact with the epitaxial structure layer.
In some more specific embodiments, the preparation method specifically comprises: and etching a designated area on the surface of the p-type GaN layer, and enabling the etching reaction to stop automatically when reaching or entering the aluminum-containing III-nitride semiconductor insertion layer, thereby forming the groove structure in the p-type GaN layer.
In some more specific embodiments, the preparation method specifically comprises: etching a designated area on the surface of the p-type GaN layer to form a groove structure, and reserving p-type GaN with a designated thickness at the bottom of the groove structure; and then removing the p-type GaN remained at the bottom of the groove structure by adopting a thermal decomposition mode, and enabling the thermal decomposition reaction to be automatically stopped when the p-type GaN reaches or enters the aluminum-containing III-group nitride semiconductor insertion layer so as to expose the aluminum-containing III-group nitride semiconductor insertion layer.
Further, the preparation method specifically comprises the following steps: in N 2 Atmosphere or N 2 And NH 3 Under the condition of 700-1000 ℃, the p-type GaN remained at the bottom of the groove structure is removed by thermal decomposition reaction.
Furthermore, the thickness of the p-type GaN remained at the bottom of the groove structure is 1-100 nm.
In some more specific embodiments, the preparation method further comprises: and etching damage repair is carried out on the interior of the groove structure in a wet etching mode, and the p-type GaN layer exposed in the groove structure is subjected to annealing treatment so as to activate the p-type GaN layer.
Further, the etching solution used in the wet etching manner includes one or a combination of two or more of tetramethylammonium hydroxide (TMAH), a potassium hydroxide solution, and a sodium hydroxide solution, but is not limited thereto.
Further, the temperature of the annealing treatment is 500-1000 ℃, and the time is 10s-30 min.
In some more specific embodiments, the preparation method further comprises: and forming an insulating medium layer on the side wall of the groove structure.
Furthermore, the material of the insulating medium layer comprises SiO 2 、SiNx(0<x<1)、SiON、Al 2 O 3 、AlON、SiAlON、TiO 2 、Ta 2 O 5 、ZrO 2 Any one or a combination of two or more of them, and the thickness is 0 to 1 μm.
Further, the material of the aluminum-containing group III nitride semiconductor insertion layer includes any one or a combination of two or more of AlN, AlGaN, AlInN, AlScN, AlInGaN, BAlN, BAlGaN, and BAlInN, but is not limited thereto.
Further, the content of Al in the aluminum-containing group III nitride semiconductor insertion layer is 0 to 50%, preferably 5 to 50%.
Further, the content of Al in the aluminum-containing group III nitride semiconductor insertion layer is gradually changed in the thickness direction thereof.
Further, the thickness of the aluminum-containing group III nitride semiconductor insertion layer is 0 to 50 nm.
Further, a group III nitride semiconductor cover layer containing Al is formed on the floating island structure.
Further, the material of the Al-containing group III nitride semiconductor cap layer includes any one or a combination of two or more of AlN, AlGaN, AlInN, AlScN, AlInGaN, balnn, and BAlInN, but is not limited thereto.
Further, the Al content in the Al-containing group III nitride semiconductor cap layer is 1-100%.
Further, the thickness of the Al-containing group III nitride semiconductor cover layer is 0-30 nm.
Further, the shape of the floating island structure includes any one or a combination of two or more of a ring shape, a bar shape, a square shape, a hexagonal shape, a triangular shape and a zigzag shape, but is not limited thereto.
Further, the lightly doped GaN layer includes an n + type GaN epitaxial layer and an n-type GaN epitaxial layer which are stacked, and the aluminum-containing group III nitride semiconductor insertion layer is stacked on the n-type GaN epitaxial layer.
Furthermore, the gallium nitride electronic device is of a full-vertical structure, the second electrode is arranged on the surface of the p-type GaN layer and forms ohmic contact with the p-type GaN layer, and the third electrode is arranged on the back surface of the substrate, which is opposite to the lightly-doped GaN layer;
or, the gallium nitride electronic device is in a quasi-vertical structure, the second electrode is arranged on the surface of the p-type GaN layer and forms ohmic contact with the p-type GaN layer, and the third electrode is arranged on the surface of the n + type GaN epitaxial layer and forms ohmic contact with the n + type GaN epitaxial layer.
The embodiment of the invention also provides a gallium nitride electronic device prepared by the preparation method.
In the following, the technical scheme, the implementation process and the principle thereof will be further explained with reference to the drawings and the specific embodiments, unless otherwise specified, the MOCVD and other methods, the etching process, the etching solution, the masking and other processes and materials, the testing method and the like used in the embodiments of the present invention may be known to those skilled in the art.
In view of the drawbacks of the prior art, as shown in fig. 5, an embodiment of the present invention provides a gallium nitride electronic device and a method for manufacturing the same, growing a layer of Al-containing III-group nitride semiconductor alloy (namely the Al-containing III-group nitride semiconductor insertion layer, represented by AlGaN as a typical representation) which is resistant to etching between an N-type lightly doped GaN layer (also can be expressed as N-GaN, the same below) and a p-type GaN layer (also can be expressed as pGaN, the same below), providing a natural termination barrier for etching of a groove structure in the p-type GaN layer by utilizing the advantage that the Al-N bond energy is larger than the Ga-N bond energy, selecting a proper temperature window, realizing the accurate control of the etching termination of a pGaN/N-GaN interface by utilizing a near-damage thermal decomposition mode, ensuring that the etching of the groove structure is just stopped at the p-N junction interface, thereby solving an important short plate of the conventional technical scheme for preparing the GaN-based JBS by dry etching the pGaN.
In addition, according to the gallium nitride electronic device and the preparation method thereof provided by the embodiment of the invention, the Al-containing III-group nitride semiconductor insertion layer is introduced, and the interface state density is greatly reduced by combining a thermal decomposition method, namely, pGaN is etched in a selected area to form a groove structure until a certain thickness of pGaN remains at the bottom of the groove structure, and then the remaining pGaN at the bottom of the groove structure is removed in a thermal decomposition manner.
On one hand, the preparation method provided by the embodiment of the invention can realize the groove structure surface with accurate and controllable depth and low interface state density, and has good consistency, uniformity and repeatability; on the other hand, the exposed Al-containing group III nitride semiconductor (wider band gap) has a higher Schottky contact barrier with metal, thereby being beneficial to improving the reverse withstand voltage of the device.
In addition, according to the preparation method provided by the embodiment of the invention, the component and the thickness of the Al-containing group III nitride semiconductor can be controlled, and the polarization electric field between the Al-containing group III nitride semiconductor and the GaN is utilized to reduce the width of a Schottky depletion region and enhance the electron tunneling during forward opening, so that the opening voltage is reduced; finally, the two-dimensional electron gas (2DEG), induced by the polarization electric field between the Al-containing group III nitride semiconductor and the lightly doped GaN layer, contributes to enhancing the lateral transport of electrons (current spreading) when turned on in the forward direction, thereby reducing the on-resistance of the device at low operating current densities.
Referring to fig. 6, an electronic device structure with GaN full-vertical structure includes, from bottom to top, a cathode ohmic contact electrode (i.e., the third electrode, the same below) 10, a substrate 20, an n + type GaN epitaxial layer 30, an n-type GaN epitaxial layer 40, an Al-containing III-nitride semiconductor insertion layer 50, a p-type GaN layer 60, an Al-containing III-nitride semiconductor cap layer 70, an anode schottky contact electrode (i.e., the first electrode, the same below) 100, and a pGaN ohmic contact electrode (i.e., the second electrode, the same below) 110.
A preparation method of an electronic device with a GaN vertical structure comprises the following steps:
(1) providing a GaN free-standing substrate 20;
(2) an n + type GaN epitaxial layer 30, an n-type GaN epitaxial layer 40, an Al-containing group III nitride semiconductor insertion layer 50, a p-type GaN layer 60, an Al-containing group III nitride semiconductor cap layer 70 are sequentially grown on the front surface of the GaN free-standing substrate 20 by MOCVD or the like, as shown in fig. 7;
(3) preparing a mask pattern 80 on the surface of the Al-containing group III nitride semiconductor cap layer 70 by photolithography or the like, as shown in fig. 8;
(4) removing the Al-containing group III nitride semiconductor cap layer 70 and the p-type GaN layer 60 in the selected region by dry etching, wet etching, nanoimprinting, or the like to form a groove structure in the p-type GaN layer 60 in the selected region, form a floating island structure in a region other than the selected region, and leave a certain thickness of p-type GaN at the bottom of the groove structure, as shown in fig. 9;
(5) preliminarily repairing the etching damage of the groove structure by adopting methods such as wet etching and the like, as shown in fig. 10, and then annealing and activating the p-type GaN layer 60; optionally, depositing an insulating medium layer on the side wall of the groove structure;
(6) removing the mask pattern on the surface of the p-type GaN, completely removing the p-type GaN remained at the bottom of the groove by thermal decomposition and other methods, exposing the Al-containing group III nitride semiconductor insertion layer, and forming pGaN with a floating island structure, as shown in FIG. 11;
(7) depositing an anode schottky metal in the groove structure by thermal evaporation and the like and annealing to form a first electrode 100, so that the first electrode 100 forms a good schottky contact with the surface of the exposed Al-containing group III nitride semiconductor insertion layer 50, as shown in fig. 12;
(8) ohmic contact metals are respectively deposited on the surface of the epitaxial structure layer and the back surface of the substrate 20 by methods such as electron beam evaporation, and then annealing is carried out to respectively form a pGaN ohmic contact electrode 110 and a cathode ohmic contact electrode, so as to complete the device preparation, as shown in FIG. 13.
Referring to fig. 14, an electronic device structure with GaN quasi-vertical structure includes, from bottom to top, a substrate 201, a transition layer 301, an unintentionally doped GaN layer 401, an n + type GaN epitaxial layer 501, an n-type GaN epitaxial layer 601, an Al-containing III-nitride semiconductor insertion layer 701, a p-type GaN layer 801, an Al-containing III-nitride semiconductor cap layer 901, an anode schottky contact electrode (i.e., the first electrode, the same below) 120, a p-type GaN ohmic contact electrode (i.e., the second electrode, the same below) 130, and an n + type GaN ohmic contact electrode (i.e., the third electrode, the same below) 140.
A preparation method of an electronic device with a GaN quasi-vertical structure comprises the following steps:
(1) providing a substrate 201 which can be a substrate of silicon, silicon carbide, SOI, diamond, zinc oxide, gallium oxide, or the like;
(2) a transition layer 301, an unintentionally doped GaN layer 401, an n + type GaN epitaxial layer 501, an n-type GaN epitaxial layer 601, an Al-containing group III nitride semiconductor insertion layer 701, a p-type GaN layer 801, an Al-containing group III nitride semiconductor cap layer 901 are sequentially grown on a substrate 201 by a method such as MOCVD, as shown in fig. 15;
(3) preparing a mask pattern 101 on the surface of the Al-containing III-group nitride semiconductor cover layer 901 by adopting methods such as photoetching, and exposing the n + type GaN epitaxial layer 501 by utilizing methods such as dry etching for preparing a subsequent cathode ohmic contact electrode; then, removing part of the mask medium by wet etching and other methods, and partially exposing the III-group nitride semiconductor cover layer containing Al on the surface, as shown in FIG. 16;
(4) preparing a mask pattern by adopting a photoetching method and the like, removing the Al-containing group III nitride semiconductor cover layer 901 and the p-type GaN layer 801 in the selected area by utilizing a dry etching method and the like so as to form a groove structure in the selected area, forming a floating island structure in the area outside the selected area, and reserving p-type GaN with a certain thickness at the bottom of the groove structure, as shown in FIG. 17;
(5) repairing etching damage on the side wall of the groove structure in the p-type GaN layer by adopting wet etching and other technologies, and annealing and activating the p-GaN epitaxial layer; then removing the surface mask medium by adopting a wet etching mode, as shown in FIG. 18; optionally, depositing an insulating medium layer on the side wall of the groove structure;
(6) placing the formed epitaxial wafer into an MOCVD reaction chamber, completely removing the residual p-type GaN at the bottom of the groove structure by using a thermal decomposition method and the like to expose the Al-containing group III nitride semiconductor insertion layer, then evaporating a first electrode in the groove structure by using a thermal evaporation method and the like and annealing to form a good schottky contact between the formed first electrode 120 and the exposed Al-containing group III nitride semiconductor insertion layer surface, as shown in fig. 19;
(7) ohmic contact metals are deposited on the floating island structure of the p-type GaN layer and the exposed n + GaN epitaxial layer 501 respectively by methods such as electron beam evaporation and the like, and annealing is performed to form a p-type GaN ohmic contact electrode 130 and an n + type GaN ohmic contact electrode 140, so that the device is prepared, as shown in fig. 20.
The present invention will be described in detail with reference to examples.
Example 1: preparation of vertical structure JBS by using GaN self-supporting substrate
S1: sequentially epitaxially growing an n + type GaN epitaxial layer (Si doping concentration is 3 multiplied by 10) with the thickness of 2 mu m on a self-supporting GaN substrate by adopting Metal Organic Chemical Vapor Deposition (MOCVD) equipment 18 cm -3 ) 6 μm n-type GaN epitaxial layer (Si doping concentration 2X 10) 16 cm -3 ) 5nm of AlGaN insertion layer of 25% Al composition, 100nm of p-type GaN layer (Mg doping concentration 3X 10) 19 cm -3 ) 5nm Mg heavily doped p-type GaN layer (Mg doping concentration 1X 10) 20 cm -3 ) 1nm AlN cap layer, as shown in FIG. 7;
s2: preparing a strip-shaped mask on the surface of the AlN cover layer by a photoetching process, wherein the width ratio of a mask area to a window area is 1: 1, the width of the window area is 5 μm, as shown in fig. 8; then selectively etching the p-type GaN layer by utilizing an ICP (inductively coupled plasma) dry etching process to form a groove structure in the p-type GaN layer corresponding to the window region, and reserving 10nm p-type GaN at the bottom of the groove structure, as shown in figure 9;
s3: performing wet etching treatment on the interior of the groove structure for 10 minutes by using a tetramethylammonium hydroxide (TMAH) solution (potassium hydroxide solution, sodium hydroxide solution and the like can also be adopted) at 85 ℃ to preliminarily repair the etching damage on the interior of the groove structure in the p-type GaN layer, as shown in fig. 10;
s4: removing the photoresist mask on the surface of the AlN cover layer by adopting a degumming solution, then putting the epitaxial wafer into an MOCVD reaction chamber, and placing the epitaxial wafer in an N reaction chamber 2 And NH 3 Heating to 850 deg.C to thermally decompose and remove residual p-type GaN at the bottom of the groove structure and expose Al with low interface state density 0.25 Ga 0.75 An N insertion layer forming a p-type GaN layer having a floating island structure, as shown in fig. 11;
s5: at 700 ℃ and N 2 Annealing the p-type GaN exposed in the groove structure for 30s in the atmosphere, activating the p-type GaN layer, and then depositing Ni (50nm)/Au (150nm) anode Schottky metal in the groove structure by adopting a thermal evaporation process, as shown in FIG. 12;
s6: depositing 100nm Au thickened metal on the surface of the AlN cover layer corresponding to the p-type GaN floating island structure by adopting an electron beam evaporation process to serve as an ohmic contact electrode;
s7: thermal evaporation was used to deposit Ti/Al/Ti/Au (20/130/50/150nm) on the back of a free-standing GaN substrate) Ohmic contact to the metal, then at 550 ℃ N 2 And annealing for 60s under the atmosphere to form a cathode ohmic contact electrode, thereby completing the preparation of the device, and finally forming the device structure as shown in figure 6.
FIG. 6 shows the JBS device with GaN vertical structure prepared in example 1, and I-V test shows that the JBS device with GaN vertical structure obtained in example 1 has an on-voltage of 0.6V and an on-resistance of only 0.7m Ω cm 2 Reverse leakage of 1X 10 -10 cm -2 And the reverse withstand voltage is as high as 1600V, which is improved by about 400V compared with a GaN JBS device with a traditional structure.
Example 2: method for preparing GaN quasi-vertical structure JBS by using silicon substrate
S1: by adopting MOCVD equipment, an AlN/AlGaN transition layer with the thickness of 1 mu m, an unintentionally doped GaN layer with the thickness of 1 mu m and an n + type GaN epitaxial layer with the thickness of 1 mu m (the doping concentration of Si is 3 multiplied by 10) are epitaxially grown on a Si (111) substrate in sequence 18 cm -3 ) 4 μm n-type GaN epitaxial layer (Si doping concentration 1X 10) 16 cm -3 ) AlGaN insertion layer with 5nm Al composition linearly graded from 0 to 25%, p-type GaN layer with 150nm (Mg doping concentration 2X 10) 19 cm -3 )、2nm Al 0.5 Ga 0.5 N cap layer, as shown in fig. 15;
s2: al on epitaxial structure by photoetching process 0.5 Ga 0.5 Preparing an annular mask pattern on the surface of the N cover layer, wherein the diameter of an inner ring is 10 mu m, and the diameter of an outer ring is 20 mu m; etching the outer ring area by adopting an ICP (inductively coupled plasma) dry etching process to expose the n + type GaN epitaxial layer for preparing a subsequent cathode ohmic contact electrode;
s3: secondary photoetching mask, adopting PECVD process to deposit SiNx layer in inner ring region, then adopting wet etching method to remove partial mask medium and expose partial Al 0.5 Ga 0.5 N cap layer surface, as shown in fig. 16;
s4: photoetching to prepare a mask pattern, and etching to remove the exposed part of the epitaxial structure by adopting an ICP (inductively coupled plasma) dry etching process so as to form a groove structure in the p-type GaN layer, and reserving a 15nm p-type GaN layer at the bottom of the groove structure, as shown in FIG. 17;
s5: wet etching the inside of the groove structure for 20 minutes by using a TMAH alkaline solution at 75 ℃ to repair etching damage in the inside of the groove structure in the p-type GaN layer, and then removing the SiNx mask medium by using a BOE solution, as shown in FIG. 18;
s6: placing the formed epitaxial wafer into an MOCVD reaction chamber, and NH at 800 DEG C 3 Removing the residual p-type GaN at the bottom of the groove structure by thermal decomposition under protection to expose the AlGaN insertion layer with gradually changed Al components, thereby forming a p-type GaN layer with a floating island structure;
s7: at 550 ℃ and N 2 Thermally annealing the p-type GaN layer exposed in the groove structure for 10 minutes in the atmosphere to activate the p-type GaN layer; then adopting electron beam evaporation to prepare a Pd (50nm)/Au (150nm) Schottky contact electrode in the groove structure, as shown in FIG. 19;
s8: depositing a 100nm Au thickening electrode on a floating island of a p-type GaN layer by adopting thermal evaporation, removing a SiNx mask medium on the surface of an n + GaN epitaxial layer by adopting a BOE solution, and then depositing Ti/Al/Ti/Au (20/130/50/150nm) ohmic contact metal on the surface of the n + GaN epitaxial layer by adopting a thermal evaporation method;
s9: at 750 ℃ and N 2 And annealing the ohmic contact metal for 60s under the atmosphere to form a good gold half contact, thereby completing the preparation of the device, wherein the structure of the obtained silicon-based GaN vertical structure JBS is shown in FIG. 20.
FIG. 14 is a schematic structural diagram of the silicon-based GaN vertical structure JBS prepared in example 2, and I-V tests show that the turn-on voltage of the silicon-based GaN vertical structure JBS device prepared in example 2 is 0.7V, and the on-resistance is only 0.9m Ω cm 2 Reverse leakage 1X 10 -10 cm -2 The reverse withstand voltage is up to 950V, which is about doubled compared with a silicon-based GaN JBS device with a traditional structure.
The preparation method of the JBS with the GaN vertical structure provided by the embodiment of the invention mainly utilizes the Al-containing III-group nitride semiconductor insertion layer (including but not limited to AlN, AlGaN, AlInN, AlScN, AlInGaN, BALN, BALGaN, BALInN and the like) to effectively realize the position controllability of a PN junction depletion region and a gold-half Schottky junction depletion region in the JBS device and effectively control the interface state density of a groove region by a thermal decomposition method, thereby reducing the reverse leakage of the device, inhibiting the peak electric field at the edge of the Schottky junction and obviously improving the breakdown voltage of the GaN-based JBS device.
According to the preparation method of the JBS with the GaN vertical structure, provided by the embodiment of the invention, the III-group nitride semiconductor insertion layer containing Al is introduced into the epitaxial structure of the traditional GaN-based JBS device to realize etching self-termination, so that not only can the position of the gold-half Schottky junction region be accurately controlled and the electric field of the PN junction depletion region and the electric field of the Schottky depletion region are maximally coupled, but also the gold-half Schottky contact with low interface state density can be realized through the advantages of methods such as thermal decomposition and selective etching, so that the reverse electric leakage of the device is greatly inhibited, and the voltage resistance of the device is improved; and the accurate control of the etching depth of the pGaN groove structure in the GaN vertical structure electronic device can be realized by utilizing the Al-containing III-group nitride semiconductor insertion layer.
According to the preparation method of the JBS with the GaN vertical structure, provided by the embodiment of the invention, the accurate control of the position of the gold-semiconductor Schottky junction region is realized by utilizing the Al-containing III-group nitride semiconductor insertion layer, and the coupling maximization of the PN junction region and the Schottky junction region is realized.
According to the preparation method of the GaN vertical structure JBS provided by the embodiment of the invention, firstly, a thin layer of Al-containing III-group nitride semiconductor insertion layer is epitaxially grown on a lightly doped GaN layer, then p-type GaN is grown, a groove structure is formed through selective etching, then the p-type GaN remained in the groove structure is removed by using a near-equilibrium state thermal decomposition method, and the defect that the groove depth of the conventional pGaN JBS is uncontrollable is overcome by using the advantage that the Al-N bond energy is larger than the Ga-N bond energy, so that the thermal decomposition in the groove structure is automatically terminated on the Al-containing III-group nitride semiconductor insertion layer, and the accurate controllability of the groove depth of the pGaN JBS is realized, and the pGaN vertical structure JBS has good consistency, uniformity and repeatability.
The embodiment of the invention provides a preparation method of a GaN vertical structure JBS, which utilizes an Al-containing III-group nitride semiconductor insertion layer to synchronously improve the reverse withstand voltage, the forward starting voltage and the conduction characteristic of a device, and the invention can reduce the reverse leakage of the device and improve the reverse withstand voltage by introducing the Al-containing III-group nitride semiconductor insertion layer, and is mainly represented in the following aspects:
1) the p-type GaN is decomposed and automatically terminated on the Al-containing III-group nitride semiconductor insertion layer by utilizing the thermal decomposition technology, so that the depth of the groove structure can be accurately controlled, the electric field of the PN junction depletion region is coupled with the electric field of the metal/Al-containing III-group nitride semiconductor Schottky depletion region to the maximum extent, the peak electric field at the edge of the Schottky junction is weakened, and the reverse withstand voltage of the device is improved;
2) compared with the surface of a groove structure etched by a dry method, the surface of the Al-containing III-group nitride semiconductor insertion layer subjected to thermal decomposition and self-termination has lower surface state density, and has good consistency, uniformity and repeatability, electrons can be remarkably inhibited from being transported by hopping of interface state energy levels under reverse bias, and electric leakage is effectively inhibited;
3) compared with metal/GaN Schottky contact, the Schottky contact barrier between metal and the Al-containing III-group nitride semiconductor insertion layer with wider band gap is higher, which is more favorable for inhibiting electron leakage and improving reverse withstand voltage of the device.
In addition, the polarization electric field between the Al-containing III-nitride semiconductor/GaN can greatly reduce the width of the depletion region of the Schottky junction, thereby improving the forward tunneling capability of electrons and further reducing the turn-on voltage of the GaN-based JBS/MPS. Meanwhile, a polarization electric field between the Al-containing III-group nitride semiconductor/GaN can induce 2DEG with certain concentration to enhance the transverse transport of forward electrons, so that the on-resistance of the device is lower when a small current (when a p-n junction is not opened); therefore, a GaN vertical structure electronic device which can improve reverse withstand voltage and reduce both forward turn-on voltage and on-resistance can be obtained by using a group III nitride semiconductor insertion layer containing Al.
The novel groove structure GaN-based JBS and the preparation method thereof provided by the embodiment of the invention can overcome the defects of the prior art, have the advantages of stability, controllability, good forward conduction, high reverse withstand voltage and the like, and have wide application prospect.
Compared with the prior art, the novel groove structure GaN-based JBS/MPS and the preparation method thereof provided by the embodiment of the invention can realize accurate control of the depth of the groove structure by introducing the Al-containing III-group nitride semiconductor insertion layer; interface etching damage in the groove structure can be effectively repaired by a thermal decomposition method, and the density of interface states is reduced; the schottky contact barrier between metal/GaN can also be improved by introducing a group III nitride semiconductor insertion layer containing Al, thereby improving reverse withstand voltage capability.
According to the preparation method provided by the embodiment of the invention, the width of the Schottky depletion region is reduced by effectively utilizing the polarization electric field between the Al-containing III-group nitride semiconductor/GaN (typically AlGaN/GaN), so that forward electron tunneling is enhanced, the starting voltage is reduced, and the forward and reverse characteristics of the device are synchronously improved; in addition, the preparation method provided by the embodiment of the invention can also effectively utilize the polarization electric field induced 2DEG between the Al-containing group III nitride semiconductor/GaN (such as AlGaN/GaN) to enhance the forward current expansion and reduce the on-resistance of the device.
The novel groove structure GaN-based JBS/MPS and the preparation method thereof have the advantages of stable and controllable junction area, good forward conduction, high reverse withstand voltage, good forward current transverse expansion and the like, the contained aluminum-containing III-group nitride semiconductor insertion layer integrates double functions of groove interface control and energy band regulation, and has great advantages of having two functions of stable and nearly nondestructive p-GaN groove controllable preparation of junction area and synchronous correlation regulation of JBS device opening and closing characteristics, and the application prospect is wide.
It should be understood that the above-mentioned embodiments are merely illustrative of the technical concepts and features of the present invention, which are intended to enable those skilled in the art to understand the contents of the present invention and implement the present invention, and therefore, the protection scope of the present invention is not limited thereby. All equivalent changes and modifications made according to the spirit of the present invention should be covered within the protection scope of the present invention.
Claims (10)
1. A method for preparing a gallium nitride electronic device is characterized by comprising the following steps:
providing an epitaxial structure layer, wherein the epitaxial structure layer comprises a lightly doped GaN layer, an aluminum-containing III-group nitride semiconductor insertion layer and a p-type GaN layer which are sequentially stacked on a substrate;
processing a designated region on the surface of the p-type GaN layer to form a groove structure in the designated region on the surface of the p-type GaN layer, and form a floating island structure in a region outside the designated region, and partially expose the aluminum-containing group III nitride semiconductor insertion layer from the groove structure;
forming a first electrode in the groove structure, and enabling the first electrode and the aluminum-containing group III nitride semiconductor insertion layer to form Schottky contact; and
and manufacturing a second electrode and a third electrode, wherein the second electrode and the third electrode are in ohmic contact with the epitaxial structure layer.
2. The method according to claim 1, comprising: and etching a designated area on the surface of the p-type GaN layer, and enabling the etching reaction to stop automatically when reaching or entering the aluminum-containing III-group nitride semiconductor insertion layer, thereby forming the groove structure in the p-type GaN layer.
3. The method according to claim 1, comprising:
etching a specified region on the surface of the p-type GaN layer to form a groove structure, and reserving p-type GaN with specified thickness at the bottom of the groove structure; removing the p-type GaN remained at the bottom of the groove structure by adopting a thermal decomposition mode, and enabling the thermal decomposition reaction to automatically stop when the p-type GaN reaches or enters the aluminum-containing III-group nitride semiconductor insertion layer so as to expose the aluminum-containing III-group nitride semiconductor insertion layer;
preferably, the preparation method specifically comprises the following steps: in N 2 Atmosphere or N 2 And NH 3 Under the condition of 700-1000 ℃, the p-type GaN remained at the bottom of the groove structure is removed by thermal decomposition reaction;
preferably, the thickness of the p-type GaN remained at the bottom of the groove structure is 1-100 nm.
4. The production method according to claim 2 or 3, characterized by further comprising: etching damage repair is carried out on the interior of the groove structure in a wet etching mode, and the p-type GaN layer exposed in the groove structure is annealed to activate the p-type GaN layer;
preferably, the etching solution used in the wet etching manner includes one or a combination of two or more of tetramethylammonium hydroxide (TMAH), a potassium hydroxide solution, and a sodium hydroxide solution;
preferably, the temperature of the annealing treatment is 500-1000 ℃, and the time is 10s-30 min.
5. The method of claim 4, further comprising: forming an insulating medium layer on the side wall of the groove structure;
preferably, the material of the insulating medium layer comprises SiO 2 、SiNx(0<x<1)、SiON、Al 2 O 3 、AlON、SiAlON、TiO 2 、Ta 2 O 5 、ZrO 2 Any one or a combination of two or more of them, and the thickness of the insulating medium layer is 0 to 1 μm.
6. The method of claim 1, wherein: the material of the aluminum-containing III-group nitride semiconductor insertion layer comprises any one or the combination of more than two of AlN, AlGaN, AlInN, AlScN, AlInGaN, BALN, BALGaN and BALInN;
preferably, the content of Al in the aluminum-containing group III nitride semiconductor insertion layer is 0 to 50%, preferably 5 to 50%;
preferably, the content of Al in the aluminum-containing group III nitride semiconductor insertion layer is gradually changed in the thickness direction thereof;
preferably, the aluminum-containing group III nitride semiconductor insertion layer has a thickness of 0 to 50 nm.
7. The production method according to claim 1, characterized in that: a III-group nitride semiconductor cover layer containing Al is also formed on the floating island structure;
preferably, the material of the Al-containing group III nitride semiconductor cap layer includes any one or a combination of two or more of AlN, AlGaN, AlInN, AlScN, AlInGaN, balnn;
preferably, the Al content in the Al-containing group III nitride semiconductor cap layer is 1-100%;
preferably, the thickness of the Al-containing group III nitride semiconductor cover layer is 0-30 nm;
preferably, the shape of the floating island structure comprises any one or a combination of more than two of annular, strip-shaped, square-shaped, hexagonal, triangular and zigzag shapes.
8. The method of claim 1, wherein: the lightly doped GaN layer comprises an n + type GaN epitaxial layer and an n-type GaN epitaxial layer which are arranged in a laminated mode, and the aluminum-containing III-group nitride semiconductor insertion layer is arranged on the n-type GaN epitaxial layer in a laminated mode.
9. The method of claim 8, wherein: the gallium nitride electronic device is of a full-vertical structure, the second electrode is arranged on the surface of the p-type GaN layer and forms ohmic contact with the p-type GaN layer, and the third electrode is arranged on the back surface of the substrate, which is opposite to the lightly-doped GaN layer;
or the gallium nitride electronic device is of a quasi-vertical structure, the second electrode is arranged on the surface of the p-type GaN layer and forms ohmic contact with the p-type GaN layer, and the third electrode is arranged on the surface of the n + type GaN epitaxial layer and forms ohmic contact with the n + type GaN epitaxial layer.
10. Gallium nitride electronic devices obtained by the production method according to any one of claims 1 to 9.
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