CN116298488B - Voltage sampling circuit, control method thereof and battery management system - Google Patents
Voltage sampling circuit, control method thereof and battery management system Download PDFInfo
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/25—Arrangements for measuring currents or voltages or for indicating presence or sign thereof using digital measurement techniques
- G01R19/2503—Arrangements for measuring currents or voltages or for indicating presence or sign thereof using digital measurement techniques for measuring voltage only, e.g. digital volt meters (DVM's)
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/30—Structural combination of electric measuring instruments with basic electronic circuits, e.g. with amplifier
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
- H02J7/0047—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries with monitoring or indicating devices or circuits
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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Abstract
The invention discloses a voltage sampling circuit, a control method thereof and a battery management system, wherein the voltage sampling circuit comprises a clock circuit, a multiplexer, an analog-to-digital converter and at least two analog front ends, wherein the clock circuit is used for sequentially distributing an amplified clock to the at least two analog front ends in different clock periods, so that only one analog front end is in an amplified working state in any clock period and the analog front ends in the amplified working state in any two adjacent clock periods are different; the analog front end is used for collecting analog voltage values and amplifying the analog voltage values; the multiplexer is used for connecting the target analog front end in the amplified clock to the analog-to-digital converter, so that the amplified clock exists in each clock period in a plurality of continuous clock periods; the analog-to-digital converter is used for analog-to-digital conversion. The analog-digital converter can continuously work through the matching among the analog front end, the multiplexer and the analog-digital converter, and the working efficiency of the sampling circuit is improved.
Description
Technical Field
The present invention relates to the field of circuit control technologies, and in particular, to a voltage sampling circuit, a control method thereof, and a battery management system.
Background
At present, due to limitations in terms of technology and circuit design, a high-voltage sampling circuit applied to a battery management system often works at a lower working frequency, a bottleneck limiting the speed of the high-voltage sampling circuit is often a high-voltage sampling front end, and a subsequent analog-to-digital converter (ADC) is often easy to work at a higher frequency. In the current circuit, in order to match the working speed of the high-voltage sampling front end, a low-speed ADC is often adopted, and the working speed of the whole system is reduced although the precision can be guaranteed and the consumption is low. A simple way to increase the speed of the high-voltage sampling circuit is to use multiple sets of circuits to measure the voltage at the same time, and each channel is divided into different ADCs in sequence to quantize. However, not only the area and the power consumption of the circuit are increased, but also the reliability of the circuit is difficult to ensure, because any ADC fails to cause a corresponding number of channels to fail, and the vehicle-mounted chip often has a high requirement on the reliability. Another way to increase the speed of the high voltage sampling circuit is to directly increase the speed of the high voltage sampling front end, but this often means a trade-off in area, power consumption, accuracy and speed, and often the cost of increasing the operating speed is not acceptable. Therefore, the portion at the front end of the high-pressure sampling can be lifted very limited.
Because the high-voltage sampling front end adopts a structure of a switch capacitor, two working states of sampling and amplifying exist, and in the sampling stage, the output of the operational amplifier is meaningless and cannot be sampled by the ADC, and only when the switch capacitor is in the amplifying stage, the value obtained by quantizing the output voltage by the ADC is meaningful. This means that if a low-speed high-voltage sampling front end is matched with a high-speed ADC, the ADC cannot operate when the high-voltage sampling front end is in the sampling stage, and only the high-voltage sampling front end can wait for the high-voltage sampling front end to enter the amplifying stage to perform quantization operation, thus slowing down the overall operating speed of the circuit.
Disclosure of Invention
The invention aims to overcome the defect that the working speed of a high-voltage sampling circuit is slowed down because an analog-to-digital converter in the high-voltage sampling circuit needs to wait for the working of the front end of the high-voltage sampling circuit in an amplifying stage in the prior art, and provides a voltage sampling circuit, a control method thereof and a battery management system.
The invention solves the technical problems by the following technical scheme:
the first aspect of the invention provides a voltage sampling circuit, which comprises a clock circuit, a multiplexer, an analog-to-digital converter and at least two analog front ends, wherein the clock circuit is electrically connected with each analog front end, each analog front end is electrically connected with the analog-to-digital converter through the multiplexer, and the working clock of each analog front end comprises a sampling clock and an amplifying clock;
the clock circuit is used for distributing the amplified clock to the at least two analog front ends in turn in different clock cycles, so that only one analog front end is in an amplified working state in any clock cycle of the at least two analog front ends and the analog front ends in the amplified working state in any two adjacent clock cycles are different;
the analog front end is used for collecting an analog voltage value when the working clock is the sampling clock, and amplifying the analog voltage value when the working clock is the amplifying clock;
the multiplexer is used for connecting a target analog front end at the amplified clock to the analog-to-digital converter, so that the amplified clock exists in each clock cycle in a plurality of continuous clock cycles;
the analog-to-digital converter is used for converting the analog voltage value output by the target analog front end into a digital voltage value.
Preferably, the analog front end comprises a voltage sampling switch and a sampling capacitor;
the voltage sampling switch is used for controlling the sampling capacitor to sample;
the sampling capacitor is used for collecting the analog voltage value.
Preferably, the analog front end includes a plurality of sampling channels and a plurality of amplifying channels;
and/or the number of the groups of groups,
the working frequency of the analog front end is 50KHz;
and/or the number of the groups of groups,
the operating frequency of the analog-to-digital converter is 1MHz.
Preferably, the analog front end includes a plurality of amplifying channels, and the analog-to-digital converter is further configured to average the digital voltage values converted from the analog voltage values output by all amplifying channels of the target analog front end.
Preferably, the clock circuit is further configured to perform non-overlapping clock processing on the working clock of the multiplexer based on the working clock of the analog front end, so that the duty cycle of the working clock of the multiplexer is smaller than that of the working clock of the analog front end;
and/or the number of the groups of groups,
the clock circuit is also used for performing non-overlapping clock processing and delay processing on the working clock of the analog-to-digital converter based on the working clock of the analog front end so as to enable the analog voltage value received by the analog-to-digital converter to tend to be stable.
A second aspect of the present invention provides a control method of a voltage sampling circuit, the voltage sampling circuit including a clock circuit, a multiplexer, an analog-to-digital converter, and at least two analog front ends, an operation clock of each of the analog front ends including a sampling clock and an amplification clock, the control method including:
the amplifying clock is sequentially distributed to the at least two analog front ends in different clock periods through the clock circuit, so that only one analog front end is in an amplifying working state in any clock period, and the analog front ends in the amplifying working state in any two adjacent clock periods are different;
acquiring an analog voltage value through the analog front end when a working clock is the sampling clock, and amplifying the analog voltage value when the working clock is the amplifying clock;
connecting a target analog front end at the amplified clock to the analog-to-digital converter through the multiplexer such that the amplified clock is within each of a plurality of consecutive clock cycles;
and converting the analog voltage value output by the target analog front end into a digital voltage value through the analog-to-digital converter.
Preferably, the analog front end includes a plurality of amplifying channels, and the control method further includes:
and averaging the digital voltage values converted from the analog voltage values output by all the amplifying channels of the target analog front end.
Preferably, the control method further includes:
and performing non-overlapping clock processing on the working clock of the multiplexer based on the working clock of the analog front end so that the duty ratio of the working clock of the multiplexer is smaller than that of the working clock of the analog front end.
Preferably, the control method further includes:
and performing non-overlapping clock processing and delay processing on the working clock of the analog-to-digital converter based on the working clock of the analog front end so as to enable the analog voltage value received by the analog-to-digital converter to be stable.
A third aspect of the invention provides a battery management system comprising the voltage sampling circuit of the first aspect.
The invention has the positive progress effects that:
according to the invention, the amplifying clocks are sequentially distributed to at least two analog front ends in different clock periods through the clock circuit, so that at least two analog front ends are in an amplifying working state in any clock period, the analog front ends in the amplifying working state in any two adjacent clock periods are different, and the amplifying clocks are arranged in each clock period in a plurality of continuous clock periods through the matching among the analog front ends, the multiplexer and the analog-to-digital converter, thereby enabling the analog-to-digital converter to continuously work and improving the working efficiency of the sampling circuit.
Drawings
Fig. 1 is a circuit diagram of a voltage sampling circuit according to embodiment 1 of the present invention.
Fig. 2 is a flowchart of a control method of the voltage sampling circuit according to embodiment 2 of the present invention.
Detailed Description
The invention is further illustrated by means of the following examples, which are not intended to limit the scope of the invention.
Example 1
As shown in fig. 1, the voltage sampling circuit provided in this embodiment includes a clock circuit 11, a multiplexer (i.e. MUX) 12, an analog-to-digital converter (i.e. ADC) 13, and at least two analog front ends (i.e. AFEs) 14, where the clock circuit 11 is electrically connected to each analog front end 14, and each analog front end 14 is electrically connected to the analog-to-digital converter 13 through the multiplexer 12, and an operation clock of each analog front end 14 includes a sampling clock and an amplifying clock;
in this embodiment, the clock circuit 11 is electrically connected to an output end of each analog front end 14, the output end of each analog front end 14 is electrically connected to the analog-to-digital converter 13 through the multiplexer 12, the input end of each analog front end 14 is electrically connected to the input end vin_1..vin_n of the voltage sampling circuit, and the output end of the analog-to-digital converter 13 is electrically connected to the output end dig_out of the sampling circuit.
The clock circuit 11 is configured to sequentially allocate the amplified clocks to at least two analog front ends 14 in different clock cycles, so that only one analog front end 14 is in an amplified working state in any clock cycle of the at least two analog front ends 14 and the analog front ends 14 in the amplified working state in any two adjacent clock cycles are different;
in this embodiment, when the amplification clocks are sequentially allocated to at least two analog front ends in different clock cycles, for example, when the number of analog front ends is two, the amplification clocks are allocated to the first analog front end in the first clock cycle (i.e., the amplification clocks are allocated to the first analog front end in the first clock cycle and the sampling clocks are allocated to the second analog front end), the amplification clocks are allocated to the second analog front end in the second clock cycle (i.e., the amplification clocks are allocated to the second analog front end in the second clock cycle and the sampling clocks are allocated to the first analog front end), the amplification clocks are allocated to the first analog front end in the third clock cycle (i.e., the amplification clocks are allocated to the first analog front end and the sampling clocks are allocated to the second analog front end), and so on in the above allocation manner that the amplification clocks are sequentially allocated to the two analog front ends in different clock cycles (i.e., the first analog front end and the second analog front end), so that the first analog front end and the second analog front end are in any two analog front ends in any state of the same in which the two analog front ends are not in any adjacent operation states;
for example, when the number of analog front ends is three, the amplification clock is allocated to the first analog front end in the first clock cycle (i.e., the amplification clock is allocated to the first analog front end and the sampling clock is allocated to the second analog front end and the third analog front end, respectively), the amplification clock is allocated to the second analog front end in the second clock cycle (i.e., the amplification clock is allocated to the second analog front end and the sampling clock is allocated to the first analog front end and the third analog front end, respectively), the third clock cycle allocates the amplification clock to the third analog front end (i.e., the amplification clock is allocated to the third analog front end in the third clock cycle, and the sampling clock is allocated to the first analog front end and the second analog front end, respectively), and so on in the above-described allocation manner, the amplification clocks are sequentially allocated to the three analog front ends in different clock cycles (i.e., the first analog front end, the second analog front end and the third analog front end, respectively), so that the first analog front end, the second analog front end and the third analog front end are in any two adjacent to each other in the same operational state.
The analog front end 14 is used for collecting an analog voltage value when the working clock is a sampling clock, and amplifying the analog voltage value when the working clock is an amplifying clock;
the multiplexer 12 is configured to connect the target analog front end at the amplified clock to the analog-to-digital converter 13 such that the amplified clock is present in each of a plurality of consecutive clock cycles;
in this embodiment, the multiplexer always connects the analog front end at the amplifying clock to the analog-to-digital converter, so that the analog-to-digital converter can continuously operate, and the stage of waiting for the analog front end to be at the sampling stage of the sampling clock is avoided.
The analog-to-digital converter 13 is used for converting the analog voltage value output from the target analog front end into a digital voltage value.
In this embodiment, in order to accelerate the operating speed of the voltage sampling circuit by using the period of time when the analog front end is in the sampling operating state and the analog-to-digital converter is not operating, the multiplexer, the clock circuit and at least two analog front ends cooperate with the analog-to-digital converter to operate in a time interleaving manner, specifically, the operating clocks of at least two analog front ends are staggered, so that one analog front end is in an amplifying operating state in any clock period, and the analog-to-digital converter can continuously operate, thereby improving the operating efficiency of the voltage sampling circuit.
In addition, in the specific implementation process, the multiplexer is matched with a proper working clock, the analog voltage value output by the analog front end is orderly transmitted to the analog-to-digital converter for analog-to-digital conversion, the circuit area is reduced, the power consumption is reduced, the working speed of the voltage sampling circuit is improved, and the battery management system is ensured to work at a faster working speed so as to improve the sampling efficiency.
In one embodiment, the analog front end includes a voltage sampling switch and a sampling capacitor;
the voltage sampling switch is used for controlling the sampling capacitor to sample;
the sampling capacitor is used for collecting analog voltage values.
In one embodiment, the analog front end includes a plurality of sampling channels and a plurality of amplification channels;
in this embodiment, the number of sampling channels and the number of amplifying channels are all set according to actual requirements, for example, the number of sampling channels and the number of amplifying channels at the analog front end may be six, or may be other values, which are not limited specifically herein.
In this embodiment, a complete voltage sampling circuit samples a plurality of different sampling channels, for example, as shown in table 1, the analog front end includes six sampling channels and six amplifying channels, the six sampling channels and the six amplifying channels are alternately allocated to two analog front ends, that is, three sampling channels and three amplifying channels represented by 0, 2, and 4 are allocated to a first analog front end, three amplifying channels and three sampling channels represented by 1, 3, and 5 are equally allocated to a second analog front end, the voltage sampling circuit operates according to the operation sequence in table 1, two analog front ends in table 1 always operate in different operation states, and the multiplexer always connects the analog front ends in the amplifying stage to the analog front end so that the analog front end can continuously operate.
TABLE 1
In one embodiment, the operating frequency of the analog front end is 50KHz; the analog-to-digital converter operates at a frequency of 1MHz with a frequency difference of 20 times between the two, and will operate for 20 cycles in one analog front end operating cycle. For example, in a specific operation process, one analog-to-digital converter is matched with two analog front ends, the analog-to-digital converter will also work for ten times in one amplified clock period, and further, the analog-to-digital converter averages the quantized results of the ten times to obtain a more accurate voltage value.
In an embodiment, the analog front end 14 comprises a plurality of amplifying channels, and the analog-to-digital converter 13 is further configured to average the digital voltage values converted from the analog voltage values output by all amplifying channels of the target analog front end.
In this embodiment, the analog voltage values output by all the amplifying channels at the target analog front end are converted into digital voltage values by the analog-to-digital converter, so as to obtain more accurate voltage values.
In an embodiment, the clock circuit 11 is further configured to perform non-overlapping clock processing on the working clock of the multiplexer based on the working clock of the analog front end, so that the duty cycle of the working clock of the multiplexer is smaller than that of the working clock of the analog front end.
In an embodiment, the clock circuit 11 is further configured to perform non-overlapping clock processing and delay processing on the operation clock of the analog-to-digital converter based on the operation clock of the analog front end, so that the analog voltage value received by the analog-to-digital converter tends to be stable.
In this embodiment, the clock circuit corrects the working clock of the multiplexer and the working clock of the analog-to-digital converter based on the working clock of the analog front end, so that the duty ratio of the working clock of the multiplexer is smaller than that of the working clock of the analog front end, the voltage value output to the analog-to-digital converter is ensured not to be unstable, and the reliability of the voltage sampling circuit is improved.
According to the embodiment, the clock circuit sequentially distributes the amplified clocks to at least two analog front ends in different clock periods, so that at least two analog front ends are in an amplified working state in any clock period, the analog front ends in the amplified working state in any two adjacent clock periods are different, and the amplified clocks are arranged in each clock period in a plurality of continuous clock periods through the cooperation among the analog front ends, the multiplexer and the analog-to-digital converter, and therefore the analog-to-digital converter can work continuously, and the working efficiency of the sampling circuit is improved.
Example 2
The control method of a voltage sampling circuit provided in this embodiment, as shown in fig. 1 in embodiment 1, includes a clock circuit 11, a multiplexer 12, an analog-to-digital converter 13, and at least two analog front ends 14, where an operation clock of each analog front end 14 includes a sampling clock and an amplifying clock, as shown in fig. 2, and includes:
step 201, sequentially distributing an amplified clock to at least two analog front ends in different clock cycles through a clock circuit, so that at least two analog front ends are in an amplified working state in any clock cycle, and the analog front ends in the amplified working state in any two adjacent clock cycles are different;
in this embodiment, when the amplification clocks are sequentially allocated to at least two analog front ends in different clock cycles, for example, when the number of analog front ends is two, the amplification clocks are allocated to the first analog front end in the first clock cycle (i.e., the amplification clocks are allocated to the first analog front end in the first clock cycle and the sampling clocks are allocated to the second analog front end), the amplification clocks are allocated to the second analog front end in the second clock cycle (i.e., the amplification clocks are allocated to the second analog front end in the second clock cycle and the sampling clocks are allocated to the first analog front end), the amplification clocks are allocated to the first analog front end in the third clock cycle (i.e., the amplification clocks are allocated to the first analog front end and the sampling clocks are allocated to the second analog front end), and so on in the above allocation manner that the amplification clocks are sequentially allocated to the two analog front ends in different clock cycles (i.e., the first analog front end and the second analog front end), so that the first analog front end and the second analog front end are in any two analog front ends in any state of the same in which the two analog front ends are not in any adjacent operation states;
for example, when the number of analog front ends is three, the amplification clock is allocated to the first analog front end in the first clock cycle (i.e., the amplification clock is allocated to the first analog front end and the sampling clock is allocated to the second analog front end and the third analog front end, respectively), the amplification clock is allocated to the second analog front end in the second clock cycle (i.e., the amplification clock is allocated to the second analog front end and the sampling clock is allocated to the first analog front end and the third analog front end, respectively), the third clock cycle allocates the amplification clock to the third analog front end (i.e., the amplification clock is allocated to the third analog front end in the third clock cycle, and the sampling clock is allocated to the first analog front end and the second analog front end, respectively), and so on in the above-described allocation manner, the amplification clocks are sequentially allocated to the three analog front ends in different clock cycles (i.e., the first analog front end, the second analog front end and the third analog front end, respectively), so that the first analog front end, the second analog front end and the third analog front end are in any two adjacent to each other in the same operational state.
Step 202, acquiring an analog voltage value through an analog front end when a working clock is a sampling clock, and amplifying the analog voltage value when the working clock is an amplifying clock;
in this embodiment, the analog front end includes a voltage sampling switch and a sampling capacitor;
the voltage sampling switch is used for controlling the sampling capacitor to sample; the sampling capacitor is used for collecting analog voltage values.
Step 203, connecting the target analog front end in the amplified clock to the analog-to-digital converter through the multiplexer, so that the amplified clock exists in each clock cycle in a plurality of continuous clock cycles;
in this embodiment, the multiplexer always connects the analog front end at the amplifying clock to the analog-to-digital converter, so that the analog-to-digital converter can continuously operate, and the stage of waiting for the analog front end to be at the sampling stage of the sampling clock is avoided.
Step 204, converting the analog voltage value output by the target analog front end into a digital voltage value through an analog-to-digital converter.
In this embodiment, in order to accelerate the operating speed of the voltage sampling circuit by using the period of time when the analog front end is in the sampling operating state and the analog-to-digital converter is not operating, the multiplexer, the clock circuit and at least two analog front ends cooperate with the analog-to-digital converter to operate in a time interleaving manner, specifically, the operating clocks of at least two analog front ends are staggered, so that one analog front end is in an amplifying operating state in any clock period, and the analog-to-digital converter can continuously operate, thereby improving the operating efficiency of the voltage sampling circuit.
In addition, in the specific implementation process, the multiplexer is matched with a proper working clock, the analog voltage value output by the analog front end is orderly transmitted to the analog-to-digital converter for analog-to-digital conversion, the circuit area is reduced, the power consumption is reduced, and the working speed of the voltage sampling circuit is improved.
In this embodiment, the analog front end includes a plurality of sampling channels and a plurality of amplifying channels; the number of sampling channels and the number of amplifying channels are all set according to actual requirements, for example, the number of sampling channels and the number of amplifying channels at the analog front end can be six, and can also be other values, which are not limited specifically herein.
In this embodiment, a complete voltage sampling circuit samples a plurality of different sampling channels, for example, as shown in table 1 in embodiment 1, the analog front end includes six sampling channels and six amplifying channels, the six sampling channels and the six amplifying channels are alternately allocated to two analog front ends, that is, three sampling channels and three amplifying channels represented by 0, 2, and 4 are equally allocated to the first analog front end, three amplifying channels and three sampling channels represented by 1, 3, and 5 are equally allocated to the second analog front end, the voltage sampling circuit operates according to the operation sequence in table 1, the two analog front ends in table 1 always operate in different operation states, and the multiplexer always connects the analog front ends in the amplifying stage to the analog-to-digital converter, so that the analog-to-digital converter can continuously operate.
In this embodiment, the working frequency of the analog front end is 50KHz; the analog-to-digital converter operates at a frequency of 1MHz with a frequency difference of 20 times between the two, and will operate for 20 cycles in one analog front end operating cycle. For example, in a specific operation process, one analog-to-digital converter is matched with two analog front ends, the analog-to-digital converter will also work for ten times in one amplified clock period, and further, the analog-to-digital converter averages the quantized results of the ten times to obtain a more accurate voltage value.
In one embodiment, the analog front end includes a plurality of amplification channels, and the control method further includes:
the analog voltage values output by all amplification channels of the target analog front end are converted into digital voltage values, and the digital voltage values are averaged.
In this embodiment, the analog voltage values output by all the amplifying channels at the target analog front end are converted into digital voltage values by the analog-to-digital converter, so as to obtain more accurate voltage values.
In one embodiment, the control method further comprises:
the working clock of the multiplexer is subjected to non-overlapping clock processing based on the working clock of the analog front end, so that the duty ratio of the working clock of the multiplexer is smaller than that of the analog front end.
In one embodiment, the control method further comprises:
the working clock of the analog-to-digital converter is subjected to non-overlapping clock processing and delay processing based on the working clock of the analog front end, so that the analog voltage value received by the analog-to-digital converter tends to be stable.
In this embodiment, the clock circuit corrects the working clock of the multiplexer and the working clock of the analog-to-digital converter based on the working clock of the analog front end, so that the duty ratio of the working clock of the multiplexer is smaller than that of the working clock of the analog front end, the voltage value output to the analog-to-digital converter is ensured not to be unstable, and the reliability of the voltage sampling circuit is improved.
According to the embodiment, the clock circuit sequentially distributes the amplified clocks to at least two analog front ends in different clock periods, so that at least two analog front ends are in an amplified working state in any clock period, the analog front ends in the amplified working state in any two adjacent clock periods are different, and the amplified clocks are arranged in each clock period in a plurality of continuous clock periods through the cooperation among the analog front ends, the multiplexer and the analog-to-digital converter, and therefore the analog-to-digital converter can work continuously, and the working efficiency of the sampling circuit is improved.
Example 3
The present embodiment provides a battery management system including the voltage sampling circuit of embodiment 1.
The working principle of the voltage sampling circuit in the battery management system in this embodiment is shown in embodiment 1, and will not be described here again.
The battery management system of the embodiment sequentially distributes the amplified clocks to at least two analog front ends in different clock cycles through the clock circuit, so that at least two analog front ends are in an amplified working state in any clock cycle, the analog front ends in the amplified working state in any two adjacent clock cycles are different, and the amplified clocks are arranged in each clock cycle in a plurality of continuous clock cycles through the cooperation among the analog front ends, the multiplexer and the analog-to-digital converter, thereby enabling the analog-to-digital converter to continuously work, improving the working efficiency of the sampling circuit, ensuring that the battery management system works at a faster working speed and improving the sampling efficiency.
While specific embodiments of the invention have been described above, it will be appreciated by those skilled in the art that this is by way of example only, and the scope of the invention is defined by the appended claims. Various changes and modifications to these embodiments may be made by those skilled in the art without departing from the principles and spirit of the invention, but such changes and modifications fall within the scope of the invention.
Claims (10)
1. The voltage sampling circuit is characterized by comprising a clock circuit, a multiplexer, an analog-to-digital converter and at least two analog front ends, wherein the clock circuit is electrically connected with each analog front end, each analog front end is electrically connected with the analog-to-digital converter through the multiplexer, and the working clock of each analog front end comprises a sampling clock and an amplifying clock;
the clock circuit is used for distributing the amplified clock to the at least two analog front ends in turn in different clock cycles, so that only one analog front end is in an amplified working state in any clock cycle of the at least two analog front ends and the analog front ends in the amplified working state in any two adjacent clock cycles are different;
the analog front end is used for collecting an analog voltage value when the working clock is the sampling clock, and amplifying the analog voltage value when the working clock is the amplifying clock;
the multiplexer is used for connecting a target analog front end at the amplified clock to the analog-to-digital converter, so that the amplified clock exists in each clock cycle in a plurality of continuous clock cycles;
the analog-to-digital converter is used for converting the analog voltage value output by the target analog front end into a digital voltage value.
2. The voltage sampling circuit of claim 1, wherein the analog front end comprises a voltage sampling switch and a sampling capacitor;
the voltage sampling switch is used for controlling the sampling capacitor to sample;
the sampling capacitor is used for collecting the analog voltage value.
3. The voltage sampling circuit of claim 1, wherein the analog front end comprises a plurality of sampling channels and a plurality of amplification channels;
and/or the number of the groups of groups,
the working frequency of the analog front end is 50KHz;
and/or the number of the groups of groups,
the operating frequency of the analog-to-digital converter is 1MHz.
4. The voltage sampling circuit of claim 1 wherein the analog front end comprises a plurality of amplification channels, the analog-to-digital converter further configured to average digital voltage values into which analog voltage values output by all amplification channels of the target analog front end are converted.
5. The voltage sampling circuit of claim 1, wherein the clock circuit is further configured to non-overlap clock process an operating clock of the multiplexer based on the operating clock of the analog front end such that an operating clock duty cycle of the multiplexer is less than the operating clock of the analog front end;
and/or the number of the groups of groups,
the clock circuit is also used for performing non-overlapping clock processing and delay processing on the working clock of the analog-to-digital converter based on the working clock of the analog front end so as to enable the analog voltage value received by the analog-to-digital converter to tend to be stable.
6. A control method of a voltage sampling circuit, wherein the voltage sampling circuit includes a clock circuit, a multiplexer, an analog-to-digital converter, and at least two analog front ends, and an operation clock of each of the analog front ends includes a sampling clock and an amplifying clock, the control method comprising:
the amplifying clock is sequentially distributed to the at least two analog front ends in different clock periods through the clock circuit, so that only one analog front end is in an amplifying working state in any clock period, and the analog front ends in the amplifying working state in any two adjacent clock periods are different;
acquiring an analog voltage value through the analog front end when a working clock is the sampling clock, and amplifying the analog voltage value when the working clock is the amplifying clock;
connecting a target analog front end at the amplified clock to the analog-to-digital converter through the multiplexer such that the amplified clock is within each of a plurality of consecutive clock cycles;
and converting the analog voltage value output by the target analog front end into a digital voltage value through the analog-to-digital converter.
7. The method of controlling a voltage sampling circuit according to claim 6, wherein the analog front end includes a plurality of amplification channels, the method further comprising:
and averaging the digital voltage values converted from the analog voltage values output by all the amplifying channels of the target analog front end.
8. The control method of a voltage sampling circuit according to claim 6, wherein the control method further comprises:
and performing non-overlapping clock processing on the working clock of the multiplexer based on the working clock of the analog front end so that the duty ratio of the working clock of the multiplexer is smaller than that of the working clock of the analog front end.
9. The control method of a voltage sampling circuit according to claim 6, wherein the control method further comprises:
and performing non-overlapping clock processing and delay processing on the working clock of the analog-to-digital converter based on the working clock of the analog front end so as to enable the analog voltage value received by the analog-to-digital converter to be stable.
10. A battery management system comprising the voltage sampling circuit of any one of claims 1-5.
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