CN116264182A - IGBT structure and preparation method thereof - Google Patents
IGBT structure and preparation method thereof Download PDFInfo
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- CN116264182A CN116264182A CN202111530289.4A CN202111530289A CN116264182A CN 116264182 A CN116264182 A CN 116264182A CN 202111530289 A CN202111530289 A CN 202111530289A CN 116264182 A CN116264182 A CN 116264182A
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- 239000010410 layer Substances 0.000 claims abstract description 226
- 238000000034 method Methods 0.000 claims abstract description 53
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 53
- 239000011241 protective layer Substances 0.000 claims abstract description 53
- 239000011229 interlayer Substances 0.000 claims abstract description 45
- 238000005530 etching Methods 0.000 claims abstract description 30
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 26
- 229920005591 polysilicon Polymers 0.000 claims abstract description 26
- 239000002184 metal Substances 0.000 claims abstract description 22
- 239000003989 dielectric material Substances 0.000 claims abstract description 21
- 238000000151 deposition Methods 0.000 claims abstract description 10
- 238000002161 passivation Methods 0.000 claims abstract description 10
- 238000001259 photo etching Methods 0.000 claims abstract description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 60
- 239000000758 substrate Substances 0.000 claims description 29
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- 239000000377 silicon dioxide Substances 0.000 claims description 28
- 238000004519 manufacturing process Methods 0.000 claims description 14
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 10
- 238000001312 dry etching Methods 0.000 claims description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 10
- 238000001039 wet etching Methods 0.000 claims description 8
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 6
- 238000000137 annealing Methods 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 5
- 238000009826 distribution Methods 0.000 claims description 4
- 238000002513 implantation Methods 0.000 claims description 4
- 238000001465 metallisation Methods 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 3
- 230000000694 effects Effects 0.000 abstract description 6
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- 238000001459 lithography Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
Abstract
The invention provides an IGBT structure and a preparation method thereof, wherein the preparation method comprises the following steps: providing an underlying structure; forming a first photoresist pattern layer on the interlayer dielectric layer by photoetching, and etching to form a contact hole; removing the first photoresist pattern layer and sequentially forming a protective layer; depositing a dielectric material layer above the protective layer and photoetching to form a second photoresist pattern layer; etching the pressure-resistant dielectric material layer to form a pressure-resistant dielectric structure; removing the second photoresist pattern layer and the protective layer to expose the active region or the polysilicon layer, wherein a part of the protective layer is still reserved below the pressure-resistant medium structure; and depositing a metal connecting layer and forming a passivation layer to protect the metal connecting layer. The invention eliminates the adverse effect of wafer warpage caused by the pressure-resistant medium structure on the contact hole forming process by adjusting the forming sequence of the contact hole and the pressure-resistant medium structure; by introducing the protective layer, the contact hole structure is prevented from being influenced by the process of forming the pressure-resistant medium structure.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to an IGBT structure and a preparation method thereof.
Background
IGBT (Insulated Gate Bipolar Transistor) is an insulated gate bipolar transistor, and is a compound full-control voltage-driven power semiconductor device composed of BJT and MOS. The IGBT has the characteristics of self-turn-off, small driving power and reduced saturation voltage, and is suitable for a power supply management system with the withstand voltage of more than 600V. The application voltage of the extra-high voltage IGBT is higher than 1000V, and the extra-high voltage IGBT has great challenges for the withstand voltage of the device.
Currently, in order to realize the withstand voltage characteristic of the ultra-high voltage IGBT, a withstand voltage structure formed by a doped dielectric layer is introduced into a device dielectric layer. Such a structure can improve the breakdown characteristics of the device by adjusting the electric field distribution of the device.
However, the design pattern of the voltage-resistant structure formed by the doped dielectric layer generally has non-uniform distribution in the wafer plane, which results in poor warpage of the wafer, thereby affecting the normal operation of the subsequent process. For example, contact hole lithography has high requirements on the accuracy of the lithography process and the wafer warpage, such as abnormal wafer warpage caused by introduction of a pressure-resistant structure, which can make the wafer unable to flow normally.
Therefore, there is a need to propose a new IGBT structure and a method for fabricating the same, which solves the above-mentioned problems.
Disclosure of Invention
In view of the above drawbacks of the prior art, an object of the present invention is to provide an IGBT structure and a method for manufacturing the same, which are used for solving the problem that the prior art cannot normally flow due to warpage caused by a voltage-resistant structure.
To achieve the above and other related objects, the present invention provides a method for manufacturing an IGBT structure, including the steps of:
1) Providing an substructure, the substructure comprising: forming a substrate of an active region, a polysilicon layer and an interlayer dielectric layer;
2) Forming a first photoresist pattern layer on the interlayer dielectric layer by photoetching; etching the interlayer dielectric layer and the bottom layer structure by taking the first photoresist pattern layer as an etching mask to form a contact hole;
3) Removing the first photoresist pattern layer, and forming a protective layer on the side wall and the bottom of the contact hole and the surface of the interlayer dielectric layer in sequence;
4) Depositing a pressure-resistant dielectric material layer above the protective layer and photoetching the pressure-resistant dielectric material layer to form a second photoresist pattern layer; etching the pressure-resistant dielectric material layer by taking the second photoresist pattern layer as an etching mask so as to form a pressure-resistant dielectric structure;
5) Removing the second photoresist pattern layer and the protective layer to expose the active region or the polysilicon layer at the bottom of the contact hole, wherein a part of the protective layer is still reserved below the pressure-resistant medium structure;
6) And depositing a metal connecting layer on the contact hole and the surface of the interlayer dielectric layer, and forming a passivation layer on the surface of the metal connecting layer to protect the metal connecting layer.
As an alternative of the present invention, a pad silicon dioxide layer for relieving the stress between the protective layer and the substrate is further formed between the interlayer dielectric layer and the protective layer.
As an alternative of the present invention, in step 5), after removing the second photoresist pattern layer and the protective layer, further removing the underlying pad silicon oxide layer to completely expose the active region or the polysilicon layer at the bottom of the contact hole; and a part of the liner silicon dioxide layer is still reserved below the pressure-resistant medium structure.
As an alternative of the present invention, the method of removing the liner silicon dioxide layer includes HF wet etching or plasma dry etching for silicon dioxide material.
As an alternative of the present invention, the projection of the dielectric structure onto the substrate does not coincide with the projection of the contact hole onto the substrate.
As an alternative of the present invention, the thickness of the substrate silicon dioxide layer is 200nm-500nm.
As an alternative of the present invention, the protective layer is composed of a silicon nitride layer; by wet etching with hot phosphoric acid or by CF in step 5) 4 /CHF 3 And removing the silicon nitride layer by plasma dry etching serving as etching gas.
As an alternative of the present invention, after forming the metal connection layer and the passivation layer, the method further includes the steps of performing a back side thinning, a back side implantation, a back side annealing, and a back side metallization process on the substrate.
The invention also provides an IGBT structure, which comprises:
the bottom structure comprises a substrate, a polysilicon layer and an interlayer dielectric layer which are sequentially stacked from bottom to top to form an active region;
the bottom of the contact hole is stopped on the active region or the polysilicon layer;
a protective layer formed over the interlayer dielectric layer;
and the pressure-resistant medium structure is formed above the protective layer.
As an alternative scheme of the invention, a liner silicon dioxide layer is also formed between the interlayer dielectric layer and the protective layer; the distribution shape of the liner silicon dioxide layer corresponds to the pressure-resistant medium structure.
As described above, the IGBT structure and the method for manufacturing the same provided by the invention have the following beneficial effects:
the invention eliminates the adverse effect of wafer warpage caused by the pressure-resistant medium structure on the contact hole forming process by adjusting the forming sequence of the contact hole and the pressure-resistant medium structure; by introducing the protective layer, the contact hole structure is prevented from being influenced in the process of forming the pressure-resistant medium structure, the process window is improved, and the process yield is improved.
Drawings
Fig. 1 is a flowchart of a method for manufacturing an IGBT structure according to an embodiment of the present invention.
Fig. 2 is a schematic view of a substrate provided in an embodiment of the present invention.
Fig. 3 is a schematic diagram of forming a first photoresist pattern layer according to an embodiment of the present invention.
Fig. 4 is a schematic diagram of forming a contact hole according to an embodiment of the present invention.
Fig. 5 is a schematic diagram of removing the first photoresist pattern layer according to an embodiment of the present invention.
Fig. 6 is a schematic diagram of forming a liner silicon dioxide layer according to an embodiment of the invention.
Fig. 7 is a schematic diagram of forming a protective layer according to an embodiment of the invention.
Fig. 8 is a schematic diagram of forming a dielectric material layer according to an embodiment of the present invention.
Fig. 9 is a schematic diagram of forming a second photoresist pattern layer according to an embodiment of the present invention.
Fig. 10 is a schematic diagram of a dielectric structure for forming a pressure-resistant medium according to an embodiment of the present invention.
FIG. 11 is a schematic diagram of removing the second photoresist pattern layer according to an embodiment of the present invention.
Fig. 12 is a schematic diagram of removing a protective layer according to an embodiment of the invention.
Fig. 13 is a schematic view of a removal liner silicon dioxide layer provided in an embodiment of the invention.
Description of element reference numerals
101. Substrate and method for manufacturing the same
102. Active region
103. Polysilicon layer
104. Interlayer dielectric layer
105. First photoresist pattern layer
106. Contact hole
107. Liner silicon dioxide layer
108. Protective layer
109. Pressure-resistant dielectric material layer
110. Second photoresist pattern layer
111. Pressure-resistant medium structure
S1-S6 Steps 1) -6)
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
Please refer to fig. 1 to 13. It should be noted that, the illustrations provided in the present embodiment are merely schematic illustrations of the basic concepts of the present invention, and only the components related to the present invention are shown in the illustrations, rather than being drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
Referring to fig. 1 to 13, the present embodiment provides a method for manufacturing an IGBT structure, including the following steps:
1) Providing an substructure, the substructure comprising: a substrate 101, a polysilicon layer 103 and an interlayer dielectric layer 104 forming an active region 102;
2) Forming a first photoresist pattern layer 105 on the interlayer dielectric layer 104 by photoetching; etching the interlayer dielectric layer 104 and etching the underlying structure by taking the first photoresist pattern layer 105 as an etching mask to form a contact hole 106;
3) Removing the first photoresist pattern layer 105, and sequentially forming a protective layer on the side wall and the bottom of the contact hole 106 and the surface of the interlayer dielectric layer 104;
4) Depositing a pressure-resistant dielectric material layer 109 above the protective layer 108 and forming a second photoresist pattern layer 110 on the pressure-resistant dielectric material layer 109 by lithography; etching the pressure-resistant dielectric material layer 109 by using the second photoresist pattern layer 110 as an etching mask to form a pressure-resistant dielectric structure 111;
5) Removing the second photoresist pattern layer 110 and the protective layer 108 to expose the active region 102 or the polysilicon layer 103 at the bottom of the contact hole 106, wherein a portion of the protective layer 108 remains below the dielectric structure 109;
6) And depositing a metal connection layer on the contact hole 106 and the surface of the interlayer dielectric layer 104, and forming a passivation layer on the surface of the metal connection layer to protect the metal connection layer.
The invention eliminates the adverse effect of wafer warpage caused by the pressure-resistant medium structure on the contact hole forming process by adjusting the forming sequence of the contact hole and the pressure-resistant medium structure; by introducing the protective layer, the contact hole structure is prevented from being influenced in the process of forming the pressure-resistant medium structure, the process window is improved, and the process yield is improved.
In step 1), referring to step S1 of fig. 1 and fig. 2, an underlying structure is provided, where the underlying structure includes: a substrate 101 forming an active region 102, a polysilicon layer 103 and an interlayer dielectric layer 104.
By way of example, the interlayer dielectric layer 104 includes, but is not limited to, a silicon dioxide layer. The substrate includes, but is not limited to, a silicon substrate, and the active region 102 may be formed by, but is not limited to, ion implantation and thermal annealing processes, including P-type and N-type well regions within the active region 102. The polysilicon layer 103 includes a polysilicon layer of a gate structure and a polysilicon layer of a wiring layer structure, wherein a gate oxide layer is further formed between the gate structure and the substrate.
In step 2), referring to step S2 of fig. 1 and fig. 3 to 4, a first photoresist pattern layer 105 is formed on the interlayer dielectric layer 104 by photolithography; and etching the interlayer dielectric layer 104 by taking the first photoresist pattern layer 105 as an etching mask and etching the bottom layer structure to form a contact hole 106.
In an example, the method of forming the contact hole 106 includes:
as shown in fig. 3, a first photoresist pattern layer 105 is formed on the interlayer dielectric layer 104 through a photolithography process. The first photoresist pattern layer 105 has a pattern of contact holes after photolithographic development exposure.
As shown in fig. 4, the first photoresist pattern layer 105 is used as an etching mask, and the interlayer dielectric layer 104 is subjected to dry etching to form the contact hole 106. The pattern of the patterned first photoresist pattern layer 105 may be inherited to the underlying interlayer dielectric layer 104 by an anisotropic dry etching process. Active region 102 and polysilicon layer 103, which are etch stop layers, are also partially etched away during the over-etch process.
In step 3), referring to step S3 of fig. 1 and fig. 5 to 7, the first photoresist pattern layer 105 is removed, and a protection layer is sequentially formed on the sidewalls and bottom of the contact hole 106 and the surface of the interlayer dielectric layer 104.
As shown in fig. 5, the first photoresist pattern layer 105 is removed by ashing photoresist removal and wet cleaning. Only the patterned contact holes 106 remain after ashing photoresist and wet cleaning.
By way of example, the protective layer 108 includes, but is not limited to, a silicon nitride layer. The silicon nitride layer may be obtained by a CVD or ALD process.
In an example, a liner silicon dioxide layer 107 is also formed between the interlayer dielectric layer 104 and the protective layer 108. The pad silicon dioxide layer 107 may be obtained by a CVD or ALD process. The pad silicon dioxide layer 107 can relieve stress between the silicon nitride layer and the underlying silicon substrate, and prevent defects such as film peeling, and the thickness of the substrate silicon dioxide layer 107 is preferably 200nm-500nm.
In step 4), referring to step S4 of fig. 1 and fig. 8 to 10, a dielectric material layer 109 is deposited over the protective layer 108 and a second photoresist pattern layer 110 is formed on the dielectric material layer 109 by photolithography; and etching the pressure-resistant dielectric material layer 109 by taking the second photoresist pattern layer 110 as an etching mask to form a pressure-resistant dielectric structure 111.
As an example, the material constituting the dielectric structure 111 includes, but is not limited to, phosphorus-doped silicon dioxide.
In one example, the method of forming the pressure resistant dielectric structure 111 includes:
as shown in fig. 8 to 9, a dielectric material layer 109 is deposited over the protective layer 108; a second photoresist pattern layer 110 is formed on the dielectric material layer 109 by a photolithography process.
As shown in fig. 10, the dielectric pressure resistant material layer 109 is dry etched with the second photoresist pattern layer 110 as an etching mask to form the dielectric pressure resistant structure 111.
In step 5), referring to step S5 of fig. 1 and fig. 11 to 13, the second photoresist pattern layer 110 and the protection layer 108 are removed to expose the active region 102 or the polysilicon layer 103 at the bottom of the contact hole 106, and a portion of the protection layer 108 remains under the dielectric structure 109.
As shown in fig. 11, the second photoresist pattern layer 110 is removed by ashing photoresist removal and wet cleaning.
As an example, as shown in fig. 11, the projection of the dielectric structure 111 onto the substrate 101 does not coincide with the projection of the contact hole 106 onto the substrate 101.
As an example, as shown in fig. 12, for the protective layer 108 made of a silicon nitride layer, which has a high selectivity to the underlying pad silicon oxide layer 107, can be removed by hot phosphoric acid wet etching, and damage to the underlying substrate can be prevented. In addition, it is also possible to use CF 4 /CHF 3 And removing the silicon nitride layer by plasma dry etching as etching gas. After the wet or dry etching process, a part of the silicon nitride layer remains under the dielectric structure 111.
As an example, as shown in fig. 13, after the protective layer 108 is removed, the underlying pad silicon oxide layer 107 is further removed to completely expose the active region 102 or the polysilicon layer 103 at the bottom of the contact hole 106. The method of removing the liner silicon dioxide layer 107 includes HF wet etching or plasma dry etching for silicon dioxide material. After the wet or dry etching process, a portion of the liner silicon dioxide layer remains under the dielectric structure 111.
As an example, after removing the protective layer 108, a step of forming a metal connection layer and a passivation layer is further included. After the contact hole 106 and the dielectric structure 111 are formed, a metal connection layer is deposited on the contact hole 106 and the surface of the interlayer dielectric layer, the metal connection layer is patterned by photolithography and etching, and then a passivation layer is deposited on the metal connection layer to protect the metal connection layer.
As an example, after forming the metal connection layer and the passivation layer, the method further includes sequentially performing a back side thinning, a back side implantation, a back side annealing, and a back side metallization process on the substrate. For IGBT devices, backside processes such as backside thinning, backside implantation, backside annealing, and backside metallization processes are optional processes to achieve advanced device performance.
As shown in fig. 13, this embodiment further provides an IGBT structure including:
a bottom structure including a substrate 101 forming an active region 102, a polysilicon layer 103 and an interlayer dielectric layer 104, which are sequentially stacked from bottom to top;
a contact hole 106 formed in the interlayer dielectric layer 104, wherein the bottom of the contact hole 106 is stopped on the active region 102 or the polysilicon layer 103;
a protective layer 108 formed over the interlayer dielectric layer 104;
and a dielectric structure 111 formed over the protective layer 108.
As an example, as shown in fig. 13, a liner silicon dioxide layer 107 is further formed between the interlayer dielectric layer 104 and the protective layer 108; the distribution shape of the pad silicon dioxide layer 107 corresponds to the pressure-resistant dielectric structure 111.
Compared with the prior art that the pressure-resistant medium structure is formed first and then the contact hole is formed, the protective layer is introduced, so that the contact hole forming process can be performed before the pressure-resistant medium structure is formed, and adverse effects on the contact hole forming process such as photoetching process caused by the wafer warping and the like caused by the pressure-resistant medium structure are avoided.
In summary, the invention provides an IGBT structure and a method for manufacturing the same, the method for manufacturing the IGBT structure comprising the steps of:
1) Providing an underlying structure comprising, in order: a substrate with an active region, a polysilicon layer and an interlayer dielectric layer are formed;
2) Forming a first photoresist pattern layer on the interlayer dielectric layer by photoetching; etching the interlayer dielectric layer and the bottom layer structure by taking the first photoresist pattern layer as an etching mask to form a contact hole in the contact hole, wherein the bottom of the contact hole is stopped on the active region or the polysilicon layer;
3) Removing the first photoresist pattern layer, sequentially forming a protective layer on the side wall and the bottom of the contact hole and the surface of the interlayer dielectric layer, and sequentially forming a protective layer on the side wall and the bottom of the contact hole and the surface of the interlayer dielectric layer;
4) Depositing a pressure-resistant dielectric material layer above the protective layer and photoetching the pressure-resistant dielectric material layer to form a second photoresist pattern layer; etching the pressure-resistant dielectric material layer by taking the second photoresist pattern layer as an etching mask so as to form a pressure-resistant dielectric structure;
5) Removing the second photoresist pattern layer and the protective layer to expose the active region or the polysilicon layer at the bottom of the contact hole, wherein a part of the protective layer is still reserved below the pressure-resistant medium structure;
6) And depositing a metal connecting layer on the contact hole and the surface of the interlayer dielectric layer, and forming a passivation layer on the surface of the metal connecting layer to protect the metal connecting layer.
The invention eliminates the adverse effect of wafer warpage caused by the pressure-resistant medium structure on the contact hole forming process by adjusting the forming sequence of the contact hole and the pressure-resistant medium structure; by introducing the protective layer, the contact hole structure is prevented from being influenced in the process of forming the pressure-resistant medium structure, the process window is improved, and the process yield is improved.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (10)
1. The preparation method of the IGBT structure is characterized by comprising the following steps of:
1) Providing an substructure, the substructure comprising: forming a substrate of an active region, a polysilicon layer and an interlayer dielectric layer;
2) Forming a first photoresist pattern layer on the interlayer dielectric layer by photoetching; etching the interlayer dielectric layer and the bottom layer structure by taking the first photoresist pattern layer as an etching mask to form a contact hole;
3) Removing the first photoresist pattern layer, and forming a protective layer on the side wall and the bottom of the contact hole and the surface of the interlayer dielectric layer in sequence;
4) Depositing a pressure-resistant dielectric material layer above the protective layer and photoetching the pressure-resistant dielectric material layer to form a second photoresist pattern layer; etching the pressure-resistant dielectric material layer by taking the second photoresist pattern layer as an etching mask so as to form a pressure-resistant dielectric structure;
5) Removing the second photoresist pattern layer and the protective layer to expose the active region or the polysilicon layer at the bottom of the contact hole, wherein a part of the protective layer is still reserved below the pressure-resistant medium structure;
6) And depositing a metal connecting layer on the contact hole and the surface of the interlayer dielectric layer, and forming a passivation layer on the surface of the metal connecting layer to protect the metal connecting layer.
2. The method for manufacturing the IGBT structure according to claim 1, wherein a pad silicon dioxide layer is further formed between the interlayer dielectric layer and the protective layer to relieve stress between the protective layer and the substrate.
3. The method of claim 2, wherein in step 5), after removing the second photoresist pattern layer and the protective layer, further removing the underlying pad silicon oxide layer to completely expose the active region or the polysilicon layer at the bottom of the contact hole; and a part of the liner silicon dioxide layer is still reserved below the pressure-resistant medium structure.
4. The method of claim 3, wherein the method of removing the liner silicon dioxide layer comprises HF wet etching or plasma dry etching for silicon dioxide material.
5. The method for manufacturing the IGBT structure according to claim 1, wherein the projection of the dielectric structure on the substrate is not coincident with the projection of the contact hole on the substrate.
6. The method of fabricating an IGBT structure according to any one of claims 2 to 4 wherein the thickness of the substrate silicon dioxide layer is 200nm to 500nm.
7. The method of manufacturing an IGBT structure according to any one of claims 1 to 4, wherein the protective layer is constituted by a silicon nitride layer; by wet etching with hot phosphoric acid or by CF in step 5) 4 /CHF 3 And removing the silicon nitride layer by plasma dry etching serving as etching gas.
8. The method of fabricating an IGBT structure according to any one of claims 1 to 5, further comprising the steps of back side thinning, back side implantation, back side annealing and back side metallization of the substrate after forming the metal connection layer and the passivation layer.
9. An IGBT structure comprising:
the bottom structure comprises a substrate, a polysilicon layer and an interlayer dielectric layer which are sequentially stacked from bottom to top to form an active region;
the bottom of the contact hole is stopped on the active region or the polysilicon layer;
a protective layer formed over the interlayer dielectric layer;
and the pressure-resistant medium structure is formed above the protective layer.
10. The IGBT structure of claim 9 wherein a liner silicon dioxide layer is also formed between the interlayer dielectric layer and the protective layer; the distribution shape of the liner silicon dioxide layer corresponds to the pressure-resistant medium structure.
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| CN (1) | CN116264182A (en) |
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2021
- 2021-12-14 CN CN202111530289.4A patent/CN116264182A/en active Pending
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