CN116259604A - 电子封装件及其制法 - Google Patents

电子封装件及其制法 Download PDF

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CN116259604A
CN116259604A CN202211545040.5A CN202211545040A CN116259604A CN 116259604 A CN116259604 A CN 116259604A CN 202211545040 A CN202211545040 A CN 202211545040A CN 116259604 A CN116259604 A CN 116259604A
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layer
pad
electronic
surface treatment
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陈文彰
许哲玮
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Phoenix Pioneer Technology Co Ltd
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Abstract

一种电子封装件及其制法，包括于功能垫的部分表面上形成表面处理层，以令电子元件借由结合层接触并结合于该功能垫及表面处理层上，使本发明的电子封装件于经过冷热冲击时，其表面处理层具备缓冲效果，因而能提高该电子封装件的封装可靠度。

Description

电子封装件及其制法
技术领域
本发明涉及一种半导体封装结构及其工艺，尤其涉及一种可提升封装可靠度的电子封装件及其制法。
背景技术
随着电子产业的蓬勃发展，电子产品也逐渐迈向多功能、高性能的趋势。为了满足电子封装结构微型化(miniaturization)的封装需求，发展出晶片级封装(Wafer LevelPackaging，简称WLP)或芯片级封装(Chip Scale Package，简称CSP)的技术。
图1A为现有CSP半导体封装件的剖面示意图。如图1A所示，该半导体封装件1的工艺中，通过于一承载件(图略)上形成一铜垫10与多个电性接触垫11，再于该铜垫10上涂布粘胶13以将半导体芯片12粘固于该铜垫10上，且于多个所述电性接触垫11上形成导电柱14；接着，以封装层15包覆该半导体芯片12、铜垫10、电性接触垫11及导电柱14；之后，于该封装层15上形成一线路结构16，以令该线路结构16电性连接该导电柱14及半导体芯片12；最后，移除该承载件。
然而，现有半导体封装件1中，该粘胶13位于该铜垫10与该半导体芯片12之间，又因该铜垫10与该半导体芯片12属于不同材质的硬性构材，而该粘胶13属于软性构材，故于工艺的热胀冷缩下，该粘胶13的上、下两侧的结合性容易产生单方向异常，致使该铜垫10与该粘胶13之间的粘合性不佳，故该半导体芯片12容易在粘胶13的结合性较弱的连接界面发生偏位，甚至脱落，导致该半导体封装件1发生可靠度问题。
再者，业界遂于该铜垫10的全部顶表面上形成如其它金属材(如电镀镍金、电镀银或化学沉积非铜的金属材等)的强化层18，如图1B所示，以强化其与该粘胶13的结合，但却使该粘胶13于该半导体芯片12侧的粘性相对较弱，导致该半导体芯片12与该粘胶13之间发生可靠度问题(例如，于冷热冲击工艺下，该半导体芯片12与该粘胶13之间发生分离)，且增加该强化层18将提高生产成本。
因此，如何克服上述现有技术的种种问题，实已成为目前业界亟待克服的难题。
发明内容
鉴于上述现有技术的种种缺陷，本发明的目的在于提供一种电子封装件及其制法，能提高该电子封装件的封装可靠度。
本发明的电子封装件，包括：一图案化金属层，其包括至少一功能垫及一第一线路层；一表面处理层，其设于该功能垫的部分表面上；一结合层，其设于于该功能垫及该表面处理层上；一电子元件，其设于该结合层上，借由该结合层结合于该功能垫及该表面处理层上，且该电子元件设有多个电性连接垫；一封装层，其包覆该电子元件与该图案化金属层，并使部分的该第一线路层的底侧的表面外露于该封装层以作为外接垫；以及一增层线路结构，其与该封装层结合并电性连接该电子元件的该电性连接垫及该第一线路层。
前述的电子封装件中，该表面处理层均匀或非均匀分布于该功能垫的部分表面上。
前述的电子封装件中，该功能垫与该表面处理层为不同的金属材质。
前述的电子封装件中，该结合层为导电粘胶或绝缘粘胶。
前述的电子封装件中，该增层线路结构借由扇出导电体电性连接该电子元件的该电性连接垫。例如，该扇出导电体形成为适应于该电子元件的电性连接垫的几何形状的柱体。
本发明还提供一种电子封装件的制法，包括：提供一至少具有金属表面的承载件；于该承载件上以图案化曝光显影方式电镀形成一图案化金属层，其中，该图案化金属层包括有至少一功能垫及一第一线路层；于该功能垫的部分表面上形成表面处理层；于该功能垫及该表面处理层上形成一结合层；于该结合层上接置一电子元件，其中，该电子元件具有多个电性连接垫；于部分的该第一线路层上以图案化曝光显影方式形成多个导电柱；以封装层包覆该电子元件及该多个导电柱；于该封装层上以图案化曝光显影方式电镀形成一第二线路层，以令该第二线路层电性连接该电子元件及该多个导电柱；以及移除该承载件，以露出部分的该第一线路层的底侧的表面作为外接垫。
前述的制法中，该表面处理层为均匀或非均匀分布形成于该功能垫的部分表面上。
前述的制法中，该功能垫与该表面处理层为不同的金属材质。
前述的制法中，还包括于形成该多个导电柱时，同步于该电子元件的电性连接垫上形成柱状的扇出导电体。例如，该扇出导电体为适应于该电子元件的电性连接垫的几何形状的柱体。
前述的制法中，还包括于形成该封装层后，以激光开孔露出该电子元件的该电性连接垫，且于后续形成该第二线路层时，同步形成导电盲孔，以令该导电盲孔电性连接该第二线路层与该电子元件的该电性连接垫。
由上可知，本发明电子封装件及其制法，主要借由于该功能垫的部分表面上形成表面处理层，使该结合层能接触两种不同材质(该表面处理层与该功能垫)，故相较于现有技术，本发明的电子封装件于经过冷热冲击时，其表面处理层具备缓冲效果，因而能提高该电子封装件的可靠度。
再者，相较于现有铜垫顶表面上全面涂布强化层，本发明的制法仅于功能垫的部分表面上形成表面处理层，因而能降低生产成本。
附图说明
图1A为现有半导体封装件的剖面示意图。
图1B为另一现有半导体封装件的剖面示意图。
图2A至图2G为本发明的电子封装件的剖面示意图。
图2E-1为图2E的另一实施例的剖面示意图。
图2G-1为图2G的另一实施例的剖面示意图。
图2H为本发明的电子封装件的另一实施例及其应用的剖面示意图。
图3A至图3C为图2B的局部俯视示意图。
附图标记如下：
1:半导体封装件
10:铜垫
11:电性接触垫
12:半导体芯片
13:粘胶
14,24,34:导电柱
15,25:封装层
16:线路结构
18:强化层
2,2a:电子封装件
20:功能垫
21:第一线路层
22:电子元件
22a:作用面
22b:非作用面
220:电性连接垫
23:结合层
24a:端面
25a:第一表面
25b:第二表面
250:通孔
251:开孔
26,261:第二线路层
26a,26b:增层线路结构
260:介电层
262,36:导电盲孔
27:导电元件
28:表面处理层
29:扇出导电体
8:电子装置
9:承载件
90:离形层
具体实施方式
以下借由特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所公开的内容轻易地了解本发明的其他优点及功效。
须知，本说明书所附附图所示出的结构、比例、大小等，均仅用以配合说明书所公开的内容，以供本领域技术人员的了解与阅读，并非用以限定本发明可实施的限定条件，故不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所公开的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“第一”、“第二”、“上”及“一”等的用语，亦仅为便于叙述的明了，而非用以限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当亦视为本发明可实施的范畴。
图2A至图2G为本发明的电子封装件2的制法的剖视示意图。
如图2A所示，提供一至少具有金属表面的承载件9，再于该承载件9上形成一包含至少一功能垫20及第一线路层21的图案化金属层。
于本实施例中，该承载件9例如为铜箔基板，以供该第一线路层21及功能垫20设于该铜箔基板的铜材上，且该承载件9上可依需求形成有一离形层90，以供该第一线路层21及功能垫20设于该离形层90上。
再者，该第一线路层21及功能垫20以图案化曝光显影方式同时制作。例如，以电镀或其它方式形成图案化铜层于该铜箔基板上(或该离形层90)上，以令该图案化铜层包含该第一线路层21及功能垫20。具体地，该电镀工艺采用重布线路层(redistribution layer，简称RDL)工艺制作该第一线路层21及功能垫20。
如图2B所示，于该功能垫20的部分顶表面上进行选择性金属化工艺以形成一表面处理层28。
于本实施例中，该功能垫20的材质不同于该表面处理层28的材质。例如，该功能垫20与该表面处理层28为不同的金属材质。具体地，形成该表面处理层28的材质为银、镍、钯、金所组群组的合金或多层金属所组成的群组中的其中一者，例如，电镀镍/金、化学镀镍/金、化镍浸金(ENIG)、化镍钯浸金(ENEPIG)、化学镀锡(Immersion Tin)等，但不限于上述。
再者，该表面处理层28为均匀或非均匀分布形成于该功能垫20的部分表面上。例如，该表面处理层28的布设方式可为至少一片状(如图3A所示)、多点状(如图3B所示的网点状)或其它图案(如图3C所示的网格状)，只需外露出该功能垫20的部分表面(或未完全覆盖该功能垫20的顶表面)即可。
如图2C所示，于该功能垫20及该表面处理层28上形成一结合层23，再于该结合层23上接置一电子元件22，以将该电子元件22借由该结合层23设于该功能垫20及该表面处理层28上，且该结合层23包覆该表面处理层28，使该结合层23同时接触该功能垫20及该表面处理层28。
于本实施例中，该电子元件22为有源元件、无源元件或其二者组合等，其中，该有源元件为例如半导体芯片，且该无源元件为例如电阻、电容及电感。例如，该电子元件22为半导体芯片，其具有相对的作用面22a与非作用面22b，该作用面22a具有多个电性连接垫220，且该电子元件22以其非作用面22b借由该结合层23固定于该功能垫20及该表面处理层28上。
再者，该结合层23为绝缘粘胶或如银胶的导电胶材，以粘附于两种金属材(即该功能垫20及该表面处理层28)，使该结合层23的粘着界面能产生缓冲效果，而确保该结合层23与该功能垫20可通过可靠度测试。例如，该结合层23的胶材于高温下才能硬化，但于高温中，该功能垫20的铜材容易氧化，致使该功能垫20变质而影响其与该结合层23的结合性，故借由于该功能垫20上形成适合该结合层23粘接的金属材(即该表面处理层28)，以于可靠度测试时，该表面处理层28具有缓冲效果，以避免发生品质变差的问题。
另外，该功能垫20不仅作为置晶垫，亦作为该电子元件22的散热垫。
如图2D所示，以图案化曝光显影方式形成多个导电柱24于至少部分的该第一线路层21上。
于本实施例中，形成该多个导电柱24的材质为如铜的金属材或焊锡材。
再者，于形成该多个导电柱24时，同步于该电子元件22的电性连接垫220上扇出(fan out)形成柱状扇出导电体29。例如，该扇出导电体29为适应于该电子元件22的电性连接垫220几何形状的柱体，如方柱、圆柱、或其它截面形状的短柱，并无特别限制。
如图2E所示，于该承载件9上形成一封装层25，以令该封装层25包覆该第一线路层21、该功能垫20、该电子元件22及该多个导电柱24。
于本实施例中，该封装层25定义有相对的第一表面25a与第二表面25b，以令该封装层25的第二表面25b结合至该承载件9(或该离形层90)上。
再者，形成该封装层25的材料为绝缘材，其可为有机介电材(如防焊材)或无机介电材(如绝缘氧化物)。例如，该有机介电材的种类可包含ABF(Ajinomoto Build-up Film)、预浸材、铸模化合物(Molding Compound)、环氧模压树脂(Epoxy Molding Compound，简称EMC)或底层涂料(Primer)。
另外，借由整平工艺，如研磨方式，移除该封装层25的部分材质，以令该封装层25的第一表面25a齐平该导电柱24的端面24a，使该导电柱24的端面24a外露于该封装层25的第一表面25a。
另外，于其它实施例中，如图2E-1所示，亦可先形成该封装层25，再以激光开孔251露出该电子元件22的电性连接垫220，且形成通孔250于该封装层25的第一表面25a上，之后形成导电材于该开孔251及通孔250中，使该导电材成为导电盲孔36及锥状导电柱34，如图2G-1所示。
如图2F所示，接续如图2E所示的工艺，以图案化曝光显影方式电镀形成一第二线路层26于该封装层25的第一表面25a上，以令该第二线路层26电性连接该电子元件22及该多个导电柱24。
于本实施例中，该第二线路层26为扇出(fan out)型重布线路层(redistributionlayer，简称RDL)。于另一实施例中，若接续如图2E-1所示的工艺，于形成该第二线路层26时，如图2G-1所示，同步形成多个导电盲孔36与导电柱34，以令该多个导电盲孔36电性连接该第二线路层26与该电子元件22的电性连接垫220。
再者，该第二线路层26接触该导电柱24的端面24a以电性连接该导电柱24。应可理解地，若该导电柱24的端面24a未外露于该封装层25的第一表面25a，则该第二线路层26可借由该导电盲孔260电性连接该导电柱24。
如图2G所示，移除该承载件9及其上的离形层90，以露出该封装层25的第二表面25b、功能垫20及该第一线路层21的底侧的表面，使该第一线路层21的底侧的表面作为外接垫。
再者，于其它实施例中，于该第二线路层26(或该封装层25的第一表面25a)上亦可以增层法形成至少一增层线路结构26a，如图2H所示的电子封装件2a，该增层线路结构26a电性连接该电子元件22与导电柱24，且该增层线路结构26a具有多个介电层260、多个设于该介电层260上的第二线路层261及多个设于该介电层260中并电性连接各该第二线路层261的导电盲孔262，其中，该介电层260的介电材为如聚对二唑苯(Polybenzoxazole，简称PBO)、聚酰亚胺(Polyimide，简称PI)、预浸材(Prepreg，简称PP)或其它等。
于后续工艺中，该电子封装件2,2a可于该第二线路层26,261上形成多个如焊球的导电元件27(如图2H所示)，以供外接至少一如半导体芯片、无源元件(如多层陶瓷电容(Multi-Layer Ceramic Capacitor)或低电感陶瓷电容(Low Inductance CeramicCapacitor))、电路板或另一封装件的电子装置8(如图2H所示)。应可理解地，亦可于该封装层25的第二表面25b及第一线路层21上形成另一增层线路结构26b(如图2H所示)，以供外接如半导体芯片、无源元件、电路板或另一封装件的电子装置(图未示)。
本发明的制法，主要借由将该表面处理层28形成于功能垫20的部分(局部)顶表面上，使该结合层23同时接触两种不同金属材(该表面处理层28与该功能垫20)，故于该电子封装件2,2a经过冷热冲击时，该表面处理层28具备缓冲效果，因而能提高该电子封装件2,2a的可靠度。例如，若该功能垫20与该结合层23的化学结合力不符预期时，该表面处理层28可作为该功能垫20与该结合层23之间的缓冲层，以增强该电子封装件2,2a于冷热冲击下的可靠度。
再者，相较于现有铜垫顶表面上全面涂布强化层，本发明的制法仅于功能垫20的部分(局部)顶表面上形成表面处理层28，因而能降低生产成本。
本发明还提供一种电子封装件2a，包括：一包含至少一功能垫20及一第一线路层21的图案化金属层、一设于该功能垫20部分表面上的表面处理层28、一结合层23、一设于该结合层23上的电子元件22、一封装层25以及一增层线路结构26a。
所述的封装层25包覆该电子元件22与该图案化金属层且具有相对的第一表面25a及第二表面25b，并使部分的该第一线路层21的底侧的表面外露于该封装层25以作为外接垫。
所述的功能垫20自该第二表面25b埋设于该封装层25中。
所述的表面处理层28设于该功能垫20的部分表面上。
所述的结合层23设于该功能垫20及该表面处理层28上。
所述的电子元件22借由该结合层23设于该功能垫20及表面处理层28上且设有多个电性连接垫220。
所述的增层线路结构26a与该封装层25结合并电性连接该电子元件22的该电性连接垫220及该第一线路层21。
于一实施例中，该表面处理层28为均匀或非均匀分布于该功能垫20的部分表面上。
于一实施例中，该功能垫20的材质不同于该表面处理层28的材质。例如，该功能垫20与该表面处理层28为不同的金属材质。
于一实施例中，该结合层23为导电粘胶或绝缘粘胶。
于一实施例中，该增层线路结构26a借由多个扇出导电体29电性连接该电子元件22的该电性连接垫220，且该扇出导电体29形成为适应于该电子元件22的电性连接垫220的几何形状的柱体。
综上所述，本发明的电子封装件及其制法，借由将该表面处理层28形成于该功能垫20的部分顶表面上，以令该结合层23同时接触两种不同金属材，使该表面处理层28作为缓冲层，故本发明的电子封装件的可靠度能符合需求。
上述实施例仅用以例示性说明本发明的原理及其功效，而非用于限制本发明。本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (12)

1.一种电子封装件，包括：
一图案化金属层，其包括至少一功能垫及一第一线路层；
一表面处理层，其设于该功能垫的部分表面上；
一结合层，其设于该功能垫及该表面处理层上；
一电子元件，其设于该结合层上，借由该结合层结合于该功能垫及该表面处理层上，且该电子元件设有多个电性连接垫；
一封装层，其包覆该电子元件与该图案化金属层，并使部分的该第一线路层的底侧的表面外露于该封装层以作为外接垫；以及
一增层线路结构，其与该封装层结合并电性连接该电子元件的该电性连接垫及该第一线路层。
2.如权利要求1所述的电子封装件，其中，该表面处理层为均匀或非均匀分布于该功能垫的部分表面上。
3.如权利要求1所述的电子封装件，其中，该功能垫与该表面处理层为不同的金属材质。
4.如权利要求1所述的电子封装件，其中，该结合层为导电粘胶或绝缘粘胶。
5.如权利要求1所述的电子封装件，其中，该增层线路结构借由扇出导电体电性连接该电子元件的该电性连接垫。
6.如权利要求5所述的电子封装件，其中，该扇出导电体形成为适应于该电子元件的电性连接垫的几何形状的柱体。
7.一种电子封装件的制法，包括：
提供一至少具有金属表面的承载件；
于该承载件上以图案化曝光显影方式电镀形成一图案化金属层，其中，该图案化金属层包括有至少一功能垫及一第一线路层；
于该功能垫的部分表面上形成表面处理层；
于该功能垫及该表面处理层上形成一结合层；
于该结合层上接置一电子元件，其中，该电子元件具有多个电性连接垫；
于部分的该第一线路层上以图案化曝光显影方式形成多个导电柱；
以封装层包覆该电子元件及该多个导电柱；
于该封装层上以图案化曝光显影方式电镀形成一第二线路层，以令该第二线路层电性连接该电子元件及该多个导电柱；以及
移除该承载件，以露出部分的该第一线路层的底侧的表面作为外接垫。
8.如权利要求7所述的电子封装件的制法，其中，该表面处理层为均匀或非均匀分布形成于该功能垫的部分表面上。
9.如权利要求7所述的电子封装件的制法，其中，该功能垫与该表面处理层为不同的金属材质。
10.如权利要求7所述的电子封装件的制法，其中，该制法还包括于形成该多个导电柱时，同步于该电子元件的电性连接垫上形成柱状的扇出导电体。
11.如权利要求10所述的电子封装件的制法，其中，该扇出导电体为适应于该电子元件的电性连接垫的几何形状的柱体。
12.如权利要求7所述的电子封装件的制法，其中，该制法还包括于形成该封装层后，以激光开孔露出该电子元件的该电性连接垫，且于后续形成该第二线路层时，同步形成导电盲孔，以令该导电盲孔电性连接该第二线路层与该电子元件的该电性连接垫。。
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