CN116259548A - 高功率密度和绝缘增强的中高压sic功率模块及制备工艺 - Google Patents
高功率密度和绝缘增强的中高压sic功率模块及制备工艺 Download PDFInfo
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Abstract
本发明涉及电力半导体封装技术领域,尤其涉及一种高功率密度和绝缘增强的中高压SIC功率模块及制备工艺,其模块包括正极负极电位DBC基板、直流正极电位端子、直流负极端子、上桥臂钼柱、上桥臂SiC MOSFET芯片、交流电位DBC基板、交流电位端子、下桥臂钼柱和下桥臂SiC MOSFET芯片,正极负极电位DBC基板和交流电位DBC基板相对设置,且相对的表面铜层上均涂覆有PI涂层,上桥臂SiC MOSFET芯片和下桥臂SiC MOSFET芯片的表面涂覆有PI涂层。本发明是基于平面封装和PI薄膜工艺的双面散热结构高功率密度封装模块,优化布局和PI薄膜的应用使模块能够在数十纳秒内切换6kV,同时振荡和电压过冲可以忽略不计且而由模块到芯片的功率利用率高达81%。
Description
技术领域
本发明涉及电力半导体封装技术领域,具体为一种高功率密度和绝缘增强的中高压SIC功率模块及制备工艺。
背景技术
宽禁带功率器件的研发创新广泛推动了电力电子设备的发展,由碳化硅(SiC)制成的功率半导体器件更是引起了广泛关注。SiC半导体目前已展示出了卓越的高压能力。然而,半导体芯片的封装显著影响着实际工况下的工作表现,这是目前阻碍中压SiC器件发挥其性能的主要原因。此外引线键合会引入额外的固有寄生电感,这通常占开关电路寄生电感的很大一部分。
模块的绝缘设计对中压SiC器件的性能有特别突出的限制。在功率模块中,电场集中在三种介质的交点处,即三相点。目前研究已经提出了几种解决方案来降低三相点的电场强度,包括改变金属陶瓷基板的几何形状、改变基板电极的尺寸、在三相点应用高击穿场强电介质以及使用非线性电介质。这些方法可以优化模块内部的电场,但不适合应用于特定模块。
发明内容
针对现有技术中存在的问题,本发明提供一种高功率密度和绝缘增强的中高压SIC功率模块及制备工艺,以优化中压模块的寄生参数与绝缘性能。
本发明是通过以下技术方案来实现:
一种高功率密度和绝缘增强的中高压SIC功率模块制备工艺,包括以下步骤:
S1,先将正极负极电位DBC基板、上桥臂钼柱和上桥臂SiC MOSFET芯片进行焊接,再将直流正极电位端子和直流负极端子焊接于正极负极电位DBC基板上,之后通过键合线将上桥臂SiC MOSFET芯片的栅极连接至正极负极电位DBC基板上,构成上桥臂子模块;
先将交流电位DBC基板、下桥臂钼柱和下桥臂SiC MOSFET芯片进行焊接,再将交流电位端子焊接于交流电位DBC基板上,之后通过键合线将下桥臂SiC MOSFET芯片的栅极连接至交流电位DBC基板上,构成下桥臂子模块;
S2,在上桥臂子模块和下桥臂子模块的互联区域上滴蜡掩膜,并在上桥臂SiCMOSFET芯片、正极负极电位DBC基板的金属化表面、下桥臂上SiC MOSFET芯片和交流电位DBC基板的金属化表面涂覆PI涂层,获得预处理子模块;
S3,将栅极铜端子、直流正铜端子和直流负铜端子与正极负极电位DBC基板连接,交流铜端子与交流DBC基板连接,获得直流子模块和交流子模块;
S4,将直流子模块和交流子模块以PI涂层相对的方式放置并进行焊接,获得中高压SIC功率模块。
优选的,在S2中,PI涂层由BPDA单体和PPDA单体聚合而成的PI溶液旋涂而成。
优选的,在旋涂过程中,转速为1000r/min-3000r/min,时间为30s~60s。
优选的,PI涂层的厚度为20~40μm。
优选的,在PI涂层涂覆过程中,增加“30℃-150℃-260℃”曲线烧结工艺。
优选的,在曲线烧结工艺中,温升速率为1℃/min。
优选的,在曲线烧结工艺中,在“30℃~150℃”烧结区段在氮气气氛中进行,气压为1*103~1*104Pa;在“150℃~260℃”烧结区段中气压为10Pa~100Pa。
优选的,在“30℃~150℃”烧结区段包括“30℃~100℃”区段和“100℃-150℃”区段,其中,在“30℃~100℃”区段和“100℃-150℃”区段中均进行保温处理,保温的时间分别至少为0.5h和1h;在“150℃~260℃”烧结区段中升温时间为0.5~1h。
优选的,栅极铜端子、直流正铜端子和直流负铜端子与正极负极电位DBC基板通过纳米烧结银工艺进行连接,交流铜端子与交流DBC基板通过纳米烧结银工艺进行连接。
一种由所述的高功率密度和绝缘增强的中高压SIC功率模块制备工艺所制备的中高压SIC功率模块,包括正极负极电位DBC基板、直流正极电位端子、直流负极端子、上桥臂钼柱、上桥臂SiC MOSFET芯片、交流电位DBC基板、交流电位端子、下桥臂钼柱和下桥臂SiCMOSFET芯片,上桥臂SiC MOSFET芯片、上桥臂钼柱均设置于正极负极电位DBC基板上,正极负极电位DBC基板上设有上桥臂门极外引区,上桥臂SiC MOSFET芯片的栅极键合于上桥臂门极外引区,直流正极电位端子和直流负极端子均与正极负极电位DBC基板连接;
下桥臂SiC MOSFET芯片、下桥臂钼柱均设置于交流电位DBC基板上,交流电位DBC基板上设有下桥臂门极外引区,下桥臂SiC MOSFET芯片的栅极键合于下桥臂门极外引区,交流电位端子与交流电位DBC基板连接;
正极负极电位DBC基板和交流电位DBC基板相对设置,且相对的表面铜层上均涂覆有PI涂层,上桥臂SiC MOSFET芯片和下桥臂SiC MOSFET芯片的表面涂覆有PI涂层。
与现有技术相比,本发明具有以下有益效果:
由于三相点的高电场强度限制着功率模块的绝缘设计,本发明通过建模与电场模拟,计算得到电场集中在芯片端子的绝缘终端层与金属焊盘层的连接处,最大电场强度可达,远超填充硅胶所能承受的/>,因此在考虑到绝缘设计与功率模块长期运行的热可靠性后,采用由BPDA(C16H6O6)、PPDA(C6H8N2)两种单体聚合而成,且与SiC热膨胀系数相近的聚酰亚胺作为芯片表面的绝缘包覆材料。
本发明是基于平面封装和PI薄膜工艺的双面散热结构高功率密度封装模块。优化布局和PI薄膜的应用使模块能够在数十纳秒内切换6kV,同时振荡和电压过冲可以忽略不计且而由模块到芯片的功率利用率高达81%。受益于PI涂层的应用和双面散热结构体积的减小,使得模组功率密度达到了52.22W/mm3。
附图说明
图1为本发明一种高功率密度和绝缘增强的中高压SIC功率模块的示意图;
图2为本发明SiC功率模块直流正极负极电位子模块示意图;
图3为本发明SiC功率模块交流电位子模块示意图。
图中,1、正极负极电位DBC基板;2、直流正极电位端子;3、直流负极端子;4、上桥臂钼柱;5、上桥臂SiC MOSFET芯片;6、上桥臂门极外引区;7、交流电位DBC基板;8、交流电位端子;9、下桥臂钼柱;10、下桥臂SiC MOSFET芯片;11、下桥臂门极外引区。
具体实施方式
下面结合具体的实施例对本发明做进一步的详细说明,所述是对本发明的解释而不是限定。
参照图1,本发明公开了一种高功率密度和绝缘增强的中高压SIC功率模块,包括正极负极电位DBC基板、直流正极电位端子、直流负极端子、上桥臂钼柱、上桥臂SiC MOSFET芯片、交流电位DBC基板、交流电位端子、下桥臂钼柱和下桥臂SiC MOSFET芯片。
参照图2,上桥臂SiC MOSFET芯片、上桥臂钼柱均设置于正极负极电位DBC基板上,正极负极电位DBC基板上设有上桥臂门极外引区,上桥臂SiC MOSFET芯片的栅极键合于上桥臂门极外引区,直流正极电位端子和直流负极端子均与正极负极电位DBC基板连接。
参照图3,下桥臂SiC MOSFET芯片、下桥臂钼柱均设置于交流电位DBC基板上,交流电位DBC基板上设有下桥臂门极外引区,下桥臂SiC MOSFET芯片的栅极键合于下桥臂门极外引区,交流电位端子与交流电位DBC基板连接。
正极负极电位DBC基板和交流电位DBC基板相对设置,且相对的表面铜层上均涂覆有PI涂层,上桥臂SiC MOSFET芯片和下桥臂SiC MOSFET芯片的表面涂覆有PI涂层。
本发明公开了一种高功率密度和绝缘增强的中高压SIC功率模块的制备工艺,包括以下步骤:
S1,先将正极负极电位DBC基板、上桥臂钼柱和上桥臂SiC MOSFET芯片进行焊接,再将直流正极电位端子和直流负极端子焊接于正极负极电位DBC基板上,之后通过键合线将上桥臂SiC MOSFET芯片的栅极连接至正极负极电位DBC基板上,构成上桥臂子模块;
先将交流电位DBC基板、下桥臂钼柱和下桥臂SiC MOSFET芯片进行焊接,再将交流电位端子焊接于交流电位DBC基板上,之后通过键合线将下桥臂SiC MOSFET芯片的栅极连接至交流电位DBC基板上,构成下桥臂子模块。其中下桥臂钼柱和上桥臂钼柱,均是为了充当缓冲层和连接层,负责连接芯片的源极和另一块DBC基板。
S2,在上桥臂子模块和下桥臂子模块的互联区域上滴蜡掩膜,并在上桥臂SiCMOSFET芯片、正极负极电位DBC基板的金属化表面、下桥臂上SiC MOSFET芯片和交流电位DBC基板的金属化表面涂覆PI涂层,获得预处理子模块。
其中,PI涂层由BPDA单体和PPDA单体聚合而成的PI溶液旋涂而成,在旋涂过程中,转速为1000r/min-3000r/min,时间为30s~60s,厚度为20~40μm。
另外,在PI涂层涂覆过程中,增加“30℃-150℃-260℃”曲线烧结工艺。即使用真空加热固化,升温至100℃,恒温0.5h,再升温至150℃,保温1h(除溶剂),继续升温至260℃,视涂层厚度不同加热0.5~1h,厚度约厚,260℃加温时间越长。温升速率为1℃/min,防止出现气泡。
在150℃恒温蒸溶剂结束之前,烧结炉气压应控制在1×103-4Pa左右,防止溶剂蒸出时由于气压过低形成鼓泡。从150℃开始升温前,再把气压控制在102数量级以下。在曲线烧结工艺中,温升速率为1℃/min。
在曲线烧结工艺中,在“30℃~150℃”烧结区段在氮气气氛中进行,气压为1*103~1*104Pa;在“150℃~260℃”烧结区段中气压为10Pa~100Pa。
在“30℃~150℃”烧结区段中的“100℃-150℃”区间中进行保温处理,保温的时间至少为1h。
S3,将栅极铜端子、直流正铜端子和直流负铜端子与正极负极电位DBC基板通过纳米烧结银工艺进行连接,交流铜端子与交流DBC基板通过纳米烧结银工艺进行连接,获得直流子模块和交流子模块。本实施例中栅极铜端子、直流正铜端子、直流负铜端子和交流电位端子均采用紫铜材料制作,且各功率端子上均开设有M4螺纹孔,以便形成机械连接。
S4,将直流子模块和交流子模块以PI涂层相对的方式放置并进行焊接,获得中高压SIC功率模块。
以上所述的仅仅是本发明的较佳实施例,并不用以对本发明的技术方案进行任何限制,本领域技术人员应当理解的是,在不脱离本发明精神和原则的前提下,该技术方案还可以进行若干简单的修改和替换,这些修改和替换也均属于权利要求书所涵盖的保护范围之内。
Claims (10)
1.一种高功率密度和绝缘增强的中高压SIC功率模块的制备工艺,其特征在于,包括以下步骤:
S1,先将正极负极电位DBC基板、上桥臂钼柱和上桥臂SiC MOSFET芯片进行焊接,再将直流正极电位端子和直流负极端子焊接于正极负极电位DBC基板上,之后通过键合线将上桥臂SiC MOSFET芯片的栅极连接至正极负极电位DBC基板上,构成上桥臂子模块;
先将交流电位DBC基板、下桥臂钼柱和下桥臂SiC MOSFET芯片进行焊接,再将交流电位端子焊接于交流电位DBC基板上,之后通过键合线将下桥臂SiC MOSFET芯片的栅极连接至交流电位DBC基板上,构成下桥臂子模块;
S2,在上桥臂子模块和下桥臂子模块的互联区域上滴蜡掩膜,并在上桥臂SiC MOSFET芯片、正极负极电位DBC基板的金属化表面、下桥臂上SiC MOSFET芯片和交流电位DBC基板的金属化表面涂覆PI涂层,获得预处理子模块;
S3,将栅极铜端子、直流正铜端子和直流负铜端子与正极负极电位DBC基板连接,交流铜端子与交流DBC基板连接,获得直流子模块和交流子模块;
S4,将直流子模块和交流子模块以PI涂层相对的方式放置并进行焊接,获得中高压SIC功率模块。
2.根据权利要求1所述的高功率密度和绝缘增强的中高压SIC功率模块的制备工艺,其特征在于,在S2中,PI涂层由BPDA单体和PPDA单体聚合而成的PI溶液旋涂而成。
3.根据权利要求2所述的高功率密度和绝缘增强的中高压SIC功率模块的制备工艺,其特征在于,在旋涂过程中,转速为1000r/min-3000r/min,时间为30s~60s。
4.根据权利要求1所述的高功率密度和绝缘增强的中高压SIC功率模块的制备工艺,其特征在于,PI涂层的厚度为20~40μm。
5.根据权利要求1所述的高功率密度和绝缘增强的中高压SIC功率模块的制备工艺,其特征在于,在PI涂层涂覆过程中,增加“30℃-150℃-260℃”曲线烧结工艺。
6.根据权利要求5所述的高功率密度和绝缘增强的中高压SIC功率模块的制备工艺,其特征在于,在曲线烧结工艺中,温升速率为1℃/min。
7.根据权利要求5所述的高功率密度和绝缘增强的中高压SIC功率模块的制备工艺,其特征在于,在曲线烧结工艺中,在“30℃~150℃”烧结区段在氮气气氛中进行,气压为1*103~1*104Pa;在“150℃~260℃”烧结区段中气压为10Pa~100Pa。
8.根据权利要求1所述的高功率密度和绝缘增强的中高压SIC功率模块的制备工艺,其特征在于,在“30℃~150℃”烧结区段包括“30℃~100℃”区段和“100℃-150℃”区段,其中,在“30℃~100℃”区段和“100℃-150℃”区段中均进行保温处理,保温的时间分别至少为0.5h和1h;在“150℃~260℃”烧结区段中升温时间为0.5~1h。
9.根据权利要求1所述的高功率密度和绝缘增强的中高压SIC功率模块的制备工艺,其特征在于,栅极铜端子、直流正铜端子和直流负铜端子与正极负极电位DBC基板通过纳米烧结银工艺进行连接,交流铜端子与交流DBC基板通过纳米烧结银工艺进行连接。
10.一种由权利要求1~9任一项所述的高功率密度和绝缘增强的中高压SIC功率模块所制备的中高压SIC功率模块,其特征在于,包括正极负极电位DBC基板、直流正极电位端子、直流负极端子、上桥臂钼柱、上桥臂SiC MOSFET芯片、交流电位DBC基板、交流电位端子、下桥臂钼柱和下桥臂SiC MOSFET芯片,上桥臂SiC MOSFET芯片、上桥臂钼柱均设置于正极负极电位DBC基板上,正极负极电位DBC基板上设有上桥臂门极外引区,上桥臂SiC MOSFET芯片的栅极键合于上桥臂门极外引区,直流正极电位端子和直流负极端子均与正极负极电位DBC基板连接;
下桥臂SiC MOSFET芯片、下桥臂钼柱均设置于交流电位DBC基板上,交流电位DBC基板上设有下桥臂门极外引区,下桥臂SiC MOSFET芯片的栅极键合于下桥臂门极外引区,交流电位端子与交流电位DBC基板连接;
正极负极电位DBC基板和交流电位DBC基板相对设置,且相对的表面铜层上均涂覆有PI涂层,上桥臂SiC MOSFET芯片和下桥臂SiC MOSFET芯片的表面涂覆有PI涂层。
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