CN116230754B - Semiconductor structure and manufacturing method thereof - Google Patents

Semiconductor structure and manufacturing method thereof Download PDF

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Publication number
CN116230754B
CN116230754B CN202310484392.2A CN202310484392A CN116230754B CN 116230754 B CN116230754 B CN 116230754B CN 202310484392 A CN202310484392 A CN 202310484392A CN 116230754 B CN116230754 B CN 116230754B
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gate
heavily doped
doped region
gate structures
structures
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CN116230754A (en
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秋珉完
郑大燮
金起凖
詹奕鹏
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Nexchip Semiconductor Corp
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Nexchip Semiconductor Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
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  • Physics & Mathematics (AREA)
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  • General Chemical & Material Sciences (AREA)
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  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)

Abstract

The application discloses a semiconductor structure and a manufacturing method thereof, which belong to the technical field of semiconductors, wherein the semiconductor structure comprises: a substrate; a gate oxide layer disposed on the substrate; at least two first gate structures disposed on the gate oxide layer, the first gate structures being disposed adjacent to each other; at least two second gate structures disposed on the gate oxide layer, the second gate structures being disposed on both sides of the first gate structure; the heavily doped region is arranged on the substrate and comprises a first heavily doped region and a second heavily doped region, the second heavily doped region is arranged between adjacent first grid structures and on one side, far away from the first grid structures, of the second grid structures, and the first heavily doped region and the second heavily doped region are arranged between adjacent first grid structures and the second grid structures in parallel. The semiconductor structure and the manufacturing method thereof can improve the performance and service life of the semiconductor structure.

Description

Semiconductor structure and manufacturing method thereof
Technical Field
The application belongs to the technical field of semiconductors, and particularly relates to a semiconductor structure and a manufacturing method thereof.
Background
An integrated Power Management circuit (PMIC) is an integrated circuit for voltage conversion, voltage regulation, and battery Management. The PMIC can process the time sequence of the power supply system, supply power to various loads and manage a plurality of external power supplies. The Metal-Oxide-Semiconductor Field-Effect Transistor (MOS) has the characteristics of high input impedance, low noise, large dynamic range, small power consumption, easy integration and the like, and can be used as a switch. However, when the drain voltage exceeds a certain value, the MOS transistor breaks down (BVdss) to cause permanent damage to the MOS transistor, or a negative resistance (Snapback) effect is generated, that is, when the forward voltage reaches a certain level, the current increases, and the voltage decreases.
Disclosure of Invention
The application aims to provide a semiconductor structure and a manufacturing method thereof, which can reduce permanent damage of the semiconductor structure, improve rebound performance of the semiconductor structure and prolong service life of the semiconductor structure.
In order to solve the technical problems, the application is realized by the following technical scheme:
the application provides a semiconductor structure, comprising:
a semiconductor structure, comprising:
a substrate;
a gate oxide layer disposed on the substrate;
at least two first gate structures disposed on the gate oxide layer, the first gate structures being disposed adjacent to each other;
at least two second gate structures disposed on the gate oxide layer, the second gate structures being disposed on both sides of the first gate structure; and
the heavily doped region is arranged on the substrate, the heavily doped region comprises a first heavily doped region and a second heavily doped region, the second heavily doped region is arranged between adjacent first gate structures and on one side, far away from the first gate structures, of the second gate structures, and the first heavily doped region and the second heavily doped region are arranged between adjacent first gate structures and the second gate structures in parallel.
In an embodiment of the present application, the first heavily doped region and the second heavily doped region between the first gate structure and the second gate structure are disposed perpendicular to the first gate structure and the second gate structure.
In an embodiment of the present application, the second heavily doped region is located at two sides of the first heavily doped region.
In one embodiment of the present application, the semiconductor structure includes a lightly doped region disposed between adjacent first gate structures and between the first gate structures and the second gate structures.
In one embodiment of the present application, the semiconductor structure includes lightly doped regions disposed on both sides of the first gate structure and the second gate structure.
In an embodiment of the present application, an edge of the lightly doped region is aligned with an edge of the first gate structure and/or the second gate structure.
In an embodiment of the present application, the semiconductor structure includes a sidewall structure, and the sidewall structure is disposed on two sides of the first gate structure and/or the second gate structure.
In an embodiment of the present application, edges of the first heavily doped region and/or the second heavily doped region are aligned with edges of the sidewall structure.
In an embodiment of the present application, the semiconductor structure includes a well region and a shallow trench isolation structure, and a depth of the well region is less than or equal to a depth of the shallow trench isolation structure.
The application also provides a manufacturing method of the semiconductor structure, which at least comprises the following steps:
providing a substrate;
forming a gate oxide layer on the substrate;
forming at least two first gate structures on the gate oxide layer, wherein the first gate structures are adjacently arranged;
forming at least two second gate structures on the gate oxide layer, wherein the second gate structures are arranged on two sides of the first gate structure; and
and forming a heavily doped region on the substrate, wherein the heavily doped region comprises a first heavily doped region and a second heavily doped region, the second heavily doped region is arranged between adjacent first gate structures and on one side, far away from the first gate structures, of the second gate structures, and the first heavily doped region and the second heavily doped region are arranged between adjacent first gate structures and the second gate structures in parallel.
In summary, the semiconductor structure and the method for manufacturing the same provided by the application can reduce the permanent damage of the semiconductor structure and improve the negative resistance effect of the semiconductor structure. Meanwhile, the switching transistor can be protected, the rebound performance of the switching transistor is improved, and the service life of the semiconductor structure is prolonged.
Of course, it is not necessary for any one product to practice the application to achieve all of the advantages set forth above at the same time.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a substrate distribution in an embodiment.
FIG. 2 is a schematic diagram of a shallow trench isolation structure in an embodiment.
FIG. 3 is a diagram of well sector area in one embodiment.
Fig. 4 is a schematic diagram of a first gate structure and a second gate structure in an embodiment.
FIG. 5 is a schematic diagram of a lightly doped region in an embodiment.
Fig. 6 is a schematic diagram illustrating formation of a sidewall structure in an embodiment.
FIG. 7 is a schematic diagram of a first heavily doped region and a second heavily doped region in an embodiment.
Fig. 8 is a top view of the sidewall structure omitted in fig. 7.
Fig. 9 is a schematic circuit diagram of a semiconductor structure and a semiconductor structure in an embodiment.
FIG. 10 is a schematic view of a lightly doped region in another embodiment.
Fig. 11 is a schematic view illustrating formation of a sidewall structure in another embodiment.
Fig. 12 is a schematic view of a first heavily doped region and a second heavily doped region in another embodiment.
Fig. 13 is a schematic circuit diagram of a semiconductor structure and a semiconductor structure in another embodiment.
Fig. 14 is a schematic diagram of an electrostatic discharge trigger signal of a semiconductor structure obtained by computer aided design.
Fig. 15 is a data diagram of the negative resistance effect of a semiconductor structure obtained by computer aided design.
Description of the reference numerals:
10. a substrate; 11. a pad oxide layer; 12. pad nitriding layer; 13. shallow trench isolation structures; 14. a well region; 15. a gate oxide layer; 16. a first gate structure; 17. a second gate structure; 18. a lightly doped region; 19. a side wall structure; 200. a heavily doped region; 20. a first heavily doped region; 21. and a second heavily doped region.
Detailed Description
Other advantages and effects of the present application will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present application with reference to specific examples. The application may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present application.
It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present application by way of illustration, and only the components related to the present application are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
In the present application, it should be noted that, as terms such as "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., appear, the indicated orientation or positional relationship is based on that shown in the drawings, only for convenience of description and simplification of the description, and does not indicate or imply that the apparatus or element in question must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the application. Furthermore, the terms "first," "second," and the like, as used herein, are used for descriptive and distinguishing purposes only and are not to be construed as indicating or implying a relative importance.
The application provides a semiconductor structure and a manufacturing method thereof, which can reduce negative resistance effect and improve rebound performance of a switching transistor while improving breakdown resistance of a MOS transistor. The semiconductor structure obtained by the manufacturing method of the semiconductor structure provided by the application can be applied to different integrated circuits and can meet the use functions of different integrated circuits.
Referring to fig. 1, in an embodiment of the present application, a plurality of regions are included in a substrate 10 to form a plurality of semiconductor devices or a plurality of types of semiconductor devices, and in this embodiment, only a substrate forming a semiconductor structure is described as an example. The substrate 10 is provided first, and the substrate 10 may be any material suitable for forming a semiconductor structure, for example, a semiconductor material formed of silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), indium phosphide (InP), gallium arsenide (GaAs), silicon germanium (GeSi), sapphire, silicon wafer, or other III/V compound, a stacked structure formed of these semiconductor materials, or a silicon-on-insulator, a stacked silicon-on-insulator, a silicon-germanium-on-insulator, a germanium-on-insulator, or the like. The material of the substrate 10 is not limited in the present application, and the substrate 10 may be a P-doped semiconductor substrate or an N-doped semiconductor substrate, and in this embodiment, the substrate 10 is, for example, a P-doped silicon semiconductor substrate.
Referring to fig. 1-2, in one embodiment of the present application, a plurality of shallow trench isolation structures are formed on a substrate 10 to isolate adjacent semiconductor structures from semiconductor devices. Specifically, the pad oxide layer 11 is formed on the substrate 10, and the pad oxide layer 11 is, for example, a dense silicon oxide or the like, and the pad oxide layer 11 can be prepared by, for example, a thermal oxidation method, an in-situ vapor growth method, a chemical vapor deposition (Chemical Vapor Deposition, CVD) or the like. A pad nitride layer 12 is formed on the pad oxide layer 11, and the pad nitride layer 12 is, for example, silicon nitride or a mixture of silicon nitride and silicon oxide, and the pad nitride layer 12 may be formed by chemical vapor deposition or the like. In the process of forming the shallow trench isolation structure, the pad oxide layer 11 can improve the stress between the substrate 10 and the pad nitride layer 12, and can protect the substrate 10 from being damaged by high-energy ions when the well region is formed by ion implantation. A patterned photoresist layer (not shown) is formed over the pad nitride layer 12 to define the locations of the shallow trench isolation structures.
Referring to fig. 1 to 2, in an embodiment of the present application, a patterned photoresist layer is used as a mask, for example, a dry etching process is used to etch in a direction toward a substrate 10 to form a shallow trench, and the etching gas may include, for example, chlorine (Cl) 2 ) Trifluoromethane (CHF) 3 ) Difluoromethane (CH) 2 F 2 ) Nitrogen trifluoride (NF) 3 ) Sulfur hexafluoride (SF) 6 ) Or hydrogen bromide (HBr), etc. After the shallow trench is formed, a liner oxide layer (not shown) is formed in the shallow trench, for example, by a thermal oxidation method, so as to repair etching damage in the process of forming the shallow trench and reduce leakage of the semiconductor structure. An isolation medium, such as an insulating material, for example, silicon oxide, is deposited within the shallow trench, for example, by high density plasma chemical vapor deposition (High Density Plasma CVD, HDP-CVD) or high aspect ratio chemical vapor deposition (High Aspect Ratio Process CVD, HARP-CVD). After the isolation medium deposition is completed, the isolation medium, the pad nitride layer 12 and part of the pad oxide layer 11 are planarized, for example, by a chemical mechanical polishing (Chemical Mechanical Polishing, CMP) process, to form a shallow trench isolation structure 13, and the shallow trench isolation structure 13 is higher than the pad oxide layer 11 on both sides.
Referring to fig. 2 to 3, in an embodiment of the present application, after forming the shallow trench isolation structure 13, the pad oxide layer 11 is used as an ion implantation protection layer, and ion implantation is performed on the substrate 10 to form the well region 14. Specifically, a doped region having a higher concentration than the substrate 10 is formed at a high implantation energy, that is, the well region 14 is formed in the substrate 10, and the well region 14 is, for example, a P-type well, and the doped ions are boron (B) or gallium (Ga) or the like. In the present embodiment, the depth of the well region 14 is, for example, less than or equal to the depth of the shallow trench isolation structure 13. After the well 14 is formed, a rapid thermal annealing process (Rapid Thermal Anneal, RTA) is performed on the substrate 10, and in this embodiment, the annealing temperature is, for example, 1000 ℃ to 1400 ℃, the annealing time is, for example, 0.5h to 1h, and the annealing process is performed under a protective gas atmosphere, for example, under a nitrogen atmosphere. Through the annealing process, ions in the well region are implanted to a proper depth, and the avalanche breakdown resistance of the semiconductor structure is improved.
Referring to fig. 3 to 4, in an embodiment of the application, after forming the well region 14, the pad oxide layer 11 is removed. In this embodiment, for example, wet etching is used to remove the pad oxide layer 11, and a wet etching liquid is selected from hydrofluoric acid, for example, and etching is performed at room temperature. In other embodiments, other etching methods may be used, and the etching method may be selected according to specific manufacturing requirements. After removing the pad oxide layer 11, a gate oxide layer 15 is formed on the surface of the well region 14, and the method for forming the gate oxide layer 15 is not limited in the present application, and may be, for example, chemical vapor deposition, physical vapor deposition, thermal oxidation, or the like. In this embodiment, the gate oxide layer 15 is formed by, for example, a thermal oxidation method, wherein the gate oxide layer 15 is, for example, a silicon oxide material, and the thickness of the gate oxide layer 15 is, for example, 5nm to 10nm. In other embodiments, the material and thickness of the gate oxide layer 15 may be set according to actual needs. By resetting the gate oxide layer 15, the flatness of the gate oxide layer 15 is ensured, the defect rate is reduced, the damage phenomenon of the pad oxide layer 11 in the process of forming the well region 14 is avoided, the breakdown and leakage phenomena of the MOS transistor are improved, and the control capability of the semiconductor structure is improved.
Referring to fig. 4, in an embodiment of the present application, a gate material layer, such as a polysilicon layer or a metal layer, is deposited on the gate oxide layer 15. In this embodiment, the gate material layer is, for example, a polysilicon layer, which is formed by, for example, low-pressure chemical vapor deposition (LPCVD), and the thickness of the gate material layer is, for example, 80nm to 120nm, wherein the polysilicon layer may be selectively doped or undoped, and the doping type may be P-type or N-type.
Referring to fig. 4 to 5, in an embodiment of the present application, after forming the gate structure, lightly doped regions 18 are formed in the substrate 10 at both sides of the gate structure, wherein the lightly doped regions 18 are doped with N-type ions, such As phosphorus (P), arsenic (As), aluminum (Al), or the like. In this embodiment, the lightly doped region 18 is located, for example, in the substrate 10 between the second gate structure 17 and the first gate structure 16, and in the substrate 10 between adjacent first gate structures 16, with the edges of the lightly doped region 18 aligned with the edges of the gate structures. I.e., the side close to the shallow trench isolation structure 13 is not provided with the lightly doped region 18 to improve the back resistance.
Referring to fig. 5 to 6, in an embodiment of the present application, after forming the lightly doped region 18, sidewall structures 19 are formed on both sides of the gate structure. Specifically, after the lightly doped region 18 is formed, a sidewall dielectric layer is formed on the gate structure, the well region 14 and the shallow trench isolation structure 13, and the sidewall dielectric layer is, for example, silicon oxide, silicon nitride or a stack of silicon oxide and silicon nitride. After the side wall dielectric layer is formed, for example, an etching process such as dry etching may be used to remove the side wall dielectric layers on the gate structure, the shallow trench isolation structure 13 and part of the well region 14, the side wall dielectric layers on two sides of the gate structure are reserved, and the gate oxide layer 15 in the regions outside the gate structure and the side wall structure is removed at the same time when the side wall dielectric layers are etched. And defining the side wall structure 19 by the reserved side wall dielectric layer, wherein the side wall structure 19 improves the insulativity of the grid electrode structure. The height of the side wall structure 19 is consistent with the height of the gate structure, the width of the side wall structure 19 gradually increases from the top to the bottom of the gate structure, and the insulating side wall structure 19 is arranged to prevent the prepared transistor from generating the electric leakage phenomenon. In this embodiment, the shape of the sidewall structure 19 is, for example, arc, and in other embodiments, the shape of the sidewall structure may be selected according to the manufacturing requirements.
Referring to fig. 6 to 7, in an embodiment of the present application, after forming the sidewall structure, the substrate is heavily doped to form a source and a drain of the transistor. The heavily doped region 200 includes a first heavily doped region 20 and a second heavily doped region 21, where the first heavily doped region 20 is, for example, P-type doped, the second heavily doped region 21 is, for example, N-type doped, and the edges of the heavily doped regions are aligned with the edges of the sidewall structure 19. A second heavily doped region 21 is formed between adjacent first gate structures 16, a second heavily doped region 21 is formed on a side of the second gate structure 17 remote from the first gate structure 16, and a first heavily doped region 20 and a second heavily doped region 21 are formed between adjacent second gate structures 17 and the first gate structure 16.
Referring to fig. 7 to 8, in an embodiment of the present application, fig. 8 is a top view of fig. 7, and the sidewall structure is omitted in the top view of fig. 8 to ensure that the pictures are concise and clear. In this embodiment, the first heavily doped region 20 and the second heavily doped region 21 are formed between the adjacent second gate structure 17 and first gate structure 16 at the same time, the first heavily doped region 20 and the second heavily doped region 21 are disposed perpendicular to the gate structures on both sides, the first heavily doped region 20 is located at the center position, and the second heavily doped region 21 is located on both sides of the first heavily doped region 20.
Referring to fig. 8 to 9, fig. 9 is a schematic circuit diagram of a semiconductor structure according to an embodiment of the application. Wherein the first gate structure 16 and the second gate structure 17 are connected to a gate voltage (Vg), the second gate structure 17 is distant from the second heavily doped region 21 on one side of the first gate structure 16, and the second heavily doped region 21 between adjacent first gate structures 16 is connected to a drain voltage (Vd), and the first heavily doped region 20 and the second heavily doped region 21 between adjacent second gate structures 17 and the first gate structure 16 are connected to a source voltage (Vs). The first gate structure 16 and the first heavily doped regions 20 on both sides form a switching transistor, the second gate structure 17 and the first heavily doped regions 20 and the second heavily doped regions 21 on both sides form a clamping transistor, and the breakdown voltage of the clamping transistor is smaller than that of the switching transistor. During operation of the switching transistor, current flows laterally at the first heavily doped region 20 and the second heavily doped region 21 between the second gate structure 17 and the first gate structure 16, reducing the flow of current to the first gate structure 16, thereby protecting the switching transistor and improving the bouncing performance of the switching transistor. That is, by providing the clamp transistor, permanent damage to the switching transistor can be reduced, while improving the negative resistance effect and prolonging the lifetime of the semiconductor structure.
Referring to fig. 4 and 10, in another embodiment of the present application, after forming the gate structure, lightly doped regions 18 are formed in the substrate 10 at both sides of the gate, wherein the lightly doped regions 18 are doped with N-type ions, such As phosphorus (P), arsenic (As), aluminum (Al), or the like. In the present embodiment, the lightly doped region 18 is located, for example, in the substrate 10 on both sides of the second gate structure 17 and the first gate structure 16, and the edge of the lightly doped region 18 is aligned with the edge of the gate structure.
Referring to fig. 10 to 11, in another embodiment of the present application, after forming the lightly doped region 18, sidewall structures 19 are formed on both sides of the gate structure. Specifically, after the lightly doped region 18 is formed, a sidewall dielectric layer is formed on the gate structure, the well region 14 and the shallow trench isolation structure 13, and the sidewall dielectric layer is, for example, silicon oxide, silicon nitride or a stack of silicon oxide and silicon nitride. After the side wall dielectric layer is formed, for example, an etching process such as dry etching may be used to remove the side wall dielectric layers on the gate structure, the shallow trench isolation structure 13 and part of the well region 14, the side wall dielectric layers on two sides of the gate structure are reserved, and the gate oxide layer 15 in the regions outside the gate structure and the side wall structure is removed at the same time when the side wall dielectric layers are etched. And defining the side wall structure 19 by the reserved side wall dielectric layer, and improving the insulativity of the side wall structure 19. The height of the side wall structure 19 is consistent with the height of the gate structure, the width of the side wall structure 19 gradually increases from the top to the bottom of the gate structure, and the insulating side wall structure 19 is arranged to prevent the prepared transistor from generating the electric leakage phenomenon. In this embodiment, the shape of the sidewall structure 19 is, for example, arc, and in other embodiments, the shape of the sidewall structure may be selected according to the manufacturing requirements.
Referring to fig. 11 to 12, in an embodiment of the present application, after forming the sidewall structure, the substrate is heavily doped to form a source and a drain of the transistor. The heavily doped region 200 includes a first heavily doped region 20 and a second heavily doped region 21, where the first heavily doped region 20 is, for example, P-type doped, the second heavily doped region 21 is, for example, N-type doped, and the edges of the heavily doped regions are aligned with the edges of the sidewall structure 19. A second heavily doped region 21 is formed between adjacent first gate structures 16, a second heavily doped region 21 is formed on a side of the second gate structure 17 remote from the first gate structure 16, and a first heavily doped region 20 and a second heavily doped region 21 are formed between the second gate structure 17 and the first gate structure 16. In a practical structure, the first heavily doped region 20 and the second heavily doped region 21 are disposed between the adjacent second gate structure 17 and the first gate structure 16, perpendicular to the gate structure, with the first heavily doped region 20 being located at a central position and the second heavily doped region 21 being located at two sides of the first heavily doped region 20.
Referring to fig. 12 to 13, in an embodiment of the present application, the first gate structure 16 and the second gate structure 17 are connected to a gate voltage (Vg), the second gate structure 17 is separated from the second heavily doped region 21 on one side of the first gate structure 16, and the second heavily doped region 21 between adjacent first gate structures 16 is connected to a drain voltage (Vd), and the first heavily doped region 20 and the second heavily doped region 21 between adjacent second gate structures 17 and the first gate structure 16 are connected to a source voltage (Vs). The first gate structure 16 and the first heavily doped regions 20 on both sides form a switching transistor, the second gate structure 17 and the first heavily doped regions 20 and the second heavily doped regions 21 on both sides form a clamping transistor, and the breakdown voltage of the clamping transistor is smaller than that of the switching transistor. During operation of the switching transistor, current flows laterally at the first and second heavily doped regions 20, 21 between the second and first gate structures 17, 16, reducing the flow of current to the first gate structure 16, thereby protecting the switching transistor and improving the bouncing performance. By providing a clamp transistor, permanent damage to the switching transistor can be reduced while improving the negative resistance effect.
Referring to fig. 14 to 15, in one embodiment of the present application, the electrostatic discharge trigger signal I of the semiconductor structure is obtained by a computer aided design (TCAD) pair trigger And simulation of negative resistance effects. Fig. 14 shows an esd trigger signal I trigger FIG. 15 is a data diagram of negative resistance effect. And case-1 is the test data of the semiconductor structure shown in fig. 9, case-2 is the test data of the semiconductor structure shown in fig. 13, general type is the test data of the semiconductor structure with only the switching transistor and no clamp transistor. Obtained by simulation, electrostatic discharge trigger signal I of General type trigger Electrostatic discharge trigger signal I of case-1 of 0.17 mA/. Mu.m trigger Electrostatic discharge trigger signal I of case-2 of 0.69 mA/. Mu.m trigger The breakdown resistance of the switching transistor can be further improved by providing a clamp transistor at 0.23 mA/um, i.e., by connecting the current path to the substrate in advance before the breakdown (BVdss) occurs on the switching transistor, improving the breakdown resistance of the switching transistor, and by not providing a lightly doped region on the side of the clamp transistor away from the switching transistor. Meanwhile, by arranging the clamping transistor, the negative resistance effect of the switching transistor can be improved, the switching transistor is protected, and the rebound performance of the switching transistor is improved.
In summary, according to the semiconductor structure and the manufacturing method thereof provided by the application, the first gate structure and the second gate structure are arranged, and the second gate structure is positioned at the outer side of the first gate structure and is used for forming the switch transistor and the clamp transistor, so that the permanent damage of the switch transistor can be reduced, and meanwhile, the negative resistance effect is improved. By arranging the first heavily doped region and the second heavily doped region between the first gate structure and the second gate structure, permanent damage of the switch transistor can be reduced, the switch transistor can be protected, rebound performance of the switch transistor is improved, and service life of the semiconductor structure is prolonged.
The embodiments of the application disclosed above are intended only to help illustrate the application. The examples are not intended to be exhaustive or to limit the application to the precise forms disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the application and the practical application, to thereby enable others skilled in the art to best understand and utilize the application. The application is limited only by the claims and the full scope and equivalents thereof.

Claims (6)

1. A semiconductor structure, comprising:
a substrate;
a gate oxide layer disposed on the substrate;
at least two first gate structures disposed on the gate oxide layer, the first gate structures being disposed adjacent to each other;
at least two second gate structures disposed on the gate oxide layer, the second gate structures being disposed on both sides of the first gate structure; and
the heavily doped region is arranged on the substrate, and comprises a first heavily doped region and a second heavily doped region, wherein the second heavily doped region is arranged between adjacent first gate structures and on one side, far away from the first gate structures, of the second gate structures, and the first heavily doped region and the second heavily doped region are arranged between adjacent first gate structures and the second gate structures in parallel;
wherein the semiconductor structure further comprises a lightly doped region disposed between adjacent first gate structures and between the first gate structures and the second gate structures;
the first heavily doped region and the second heavily doped region between the first gate structure and the second gate structure are arranged perpendicular to the first gate structure and the second gate structure; the second heavily doped region is positioned at two sides of the first heavily doped region;
the semiconductor structure comprises a switch transistor and a clamping transistor, wherein the switch transistor comprises a first gate structure and the first heavily doped regions at two sides of the first gate structure, and the clamping transistor comprises a second gate structure and the first heavily doped regions and the second heavily doped regions at two sides of the second gate structure.
2. The semiconductor structure of claim 1, wherein an edge of the lightly doped region is aligned with an edge of the first gate structure and/or the second gate structure.
3. The semiconductor structure of claim 1, wherein the semiconductor structure comprises a sidewall structure disposed on both sides of the first gate structure and/or the second gate structure.
4. The semiconductor structure of claim 3, wherein an edge of the first heavily doped region and/or the second heavily doped region is aligned with an edge of the sidewall structure.
5. The semiconductor structure of claim 1, wherein the semiconductor structure comprises a well region and a shallow trench isolation structure, the well region having a depth less than or equal to a depth of the shallow trench isolation structure.
6. A method for fabricating a semiconductor structure, comprising:
providing a substrate;
forming a gate oxide layer on the substrate;
forming at least two first gate structures on the gate oxide layer, wherein the first gate structures are adjacently arranged;
forming at least two second gate structures on the gate oxide layer, wherein the second gate structures are arranged on two sides of the first gate structure; and
forming a heavily doped region on the substrate, wherein the heavily doped region comprises a first heavily doped region and a second heavily doped region, the second heavily doped region is arranged between adjacent first gate structures and on one side, far away from the first gate structures, of the second gate structures, and the first heavily doped region and the second heavily doped region are arranged between adjacent first gate structures and the second gate structures in parallel;
the manufacturing method of the semiconductor structure further comprises the steps of forming a lightly doped region, wherein the lightly doped region is arranged between the adjacent first gate structures and between the first gate structures and the second gate structures;
the first heavily doped region and the second heavily doped region between the first gate structure and the second gate structure are arranged perpendicular to the first gate structure and the second gate structure; the second heavily doped region is positioned at two sides of the first heavily doped region;
the first gate structure and the first heavily doped regions on both sides of the first gate structure form a switching transistor, and the second gate structure and the first heavily doped regions and the second heavily doped regions on both sides of the second gate structure form a clamping transistor.
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