CN110767548B - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN110767548B
CN110767548B CN201810827317.0A CN201810827317A CN110767548B CN 110767548 B CN110767548 B CN 110767548B CN 201810827317 A CN201810827317 A CN 201810827317A CN 110767548 B CN110767548 B CN 110767548B
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layer
forming
substrate
region
isolation layer
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CN110767548A (en
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杨震
陈德艳
赵连国
彭昀鹏
管伟
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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Abstract

A semiconductor structure and a method for forming the same, the method for forming the same includes: providing a substrate, wherein a well region and a drift region which are adjacent are formed in the substrate; forming a groove in the drift region; forming an isolation layer in the groove; and forming a gate layer on the substrate at the junction of the well region and the drift region at one side of the groove. According to the invention, after the groove is formed in the drift region, the isolation layer is formed in the groove, and then the grid layer is formed on the substrate at the junction of the well region at one side of the groove and the drift region.

Description

Semiconductor structure and forming method thereof
Technical Field
Embodiments of the present disclosure relate to semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
As semiconductor chips are increasingly used, the semiconductor chips are increasingly subject to electrostatic damage. In existing chip designs, electrostatic discharge (ESD, electrostatic Discharge) protection circuits are often used to reduce chip damage. The design and application of existing esd protection circuits include: grounded gate N-type field effect transistor (Gate Grounded NMOS, GGNMOS) protection circuits, silicon controlled rectifier (Silicon Controlled Rectifier, SCR) protection circuits, lateral double-diffused field effect transistor (Lateral Double Diffused MOSFET, LDMOS) protection circuits, bipolar junction transistor (Bipolar Junction Transistor, BJT) protection circuits, and the like. Among them, LDMOS are widely used for ESD protection because they can withstand higher breakdown voltages.
In order to improve the pressure resistance, a drift region is further arranged in the substrate between the source region and the drain region, and the doping concentration of the drift region is low, so that when the LDMOS is connected with high voltage, the drift region is high-resistance, and the partial voltage is high, so that the LDMOS can bear higher voltage.
With the continuous development of semiconductor technology, the application of the LDMOS is increasingly wide, and correspondingly, higher requirements are also put forward on the performance of the LDMOS. Therefore, currently, a Field plate technology is mainly adopted to further improve the breakdown voltage of the LDMOS, that is, a Field Oxide (FOX) layer is formed on a substrate of a drift region, and a gate layer of the LDMOS extends from a substrate corresponding to a well region to the top of the Field Oxide layer, and the gate layer located on the Field Oxide layer is used as a Field plate, so that the surface electric Field of the drift region is weakened, and the Field Oxide edge is prevented from being too concentrated by electric lines, thereby improving the breakdown voltage.
Disclosure of Invention
The embodiment of the invention solves the problem of providing a semiconductor structure and a forming method thereof, and improves the performance of LDMOS.
In order to solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein a well region and a drift region which are adjacent are formed in the substrate; forming a groove in the drift region; forming an isolation layer in the groove; and forming a gate layer on the substrate at the junction of the well region and the drift region at one side of the groove.
Optionally, in the step of forming a recess in the drift region, the depth of the recess isTo the point of
Optionally, the step of forming a recess in the drift region includes: and etching a substrate material with partial thickness corresponding to the drift region by adopting a dry etching process, and forming the groove in the substrate.
Optionally, the material of the isolation layer is polysilicon.
Optionally, an isolation layer is formed in the groove through a deposition process.
Optionally, in the step of forming the isolation layer in the groove, the deposition process is a chemical vapor deposition process.
Optionally, the isolation layer and the gate layer are formed in the same process step.
Optionally, the step of forming the gate layer and the isolation layer includes: forming a gate material layer covering the substrate through a deposition process, wherein the gate material layer is also positioned in the groove; and patterning the gate material layer, reserving the residual gate material layer in the groove as the isolation layer, reserving the residual gate material layer on the substrate at the junction of the well region and the drift region as the gate layer, and positioning the gate layer on one side of the isolation layer.
Optionally, after forming the recess in the drift region, before forming the isolation layer in the recess, the method further includes: and forming a linear oxide layer at the bottom and the side wall of the groove.
Optionally, in the step of providing a substrate, the well region and the drift region have doped ions therein, and the doped ions in the drift region are of a different type from the doped ions in the well region; after forming the gate layer and the isolation layer, the method further comprises: forming a source region in a well region at one side of the gate layer far away from the isolation layer, forming a drain region in a drift region at one side of the isolation layer far away from the gate layer, wherein doping ions in the source region and the drain region are the same as doping ions in the drift region; after the source region and the drain region are formed, a silicide blocking layer is formed on the substrate, and covers the drift region and the drain region exposed by the gate layer and the isolation layer, and also covers the isolation layer, and the side wall and part of the top of the gate layer, which is close to one side of the isolation layer.
Optionally, the step of forming the source region and the drain region includes: forming a pattern layer on the substrate, wherein the pattern layer covers the isolation layer and exposes a partial area substrate on one side of the gate layer away from the isolation layer and a partial area substrate on one side of the isolation layer away from the gate layer; doping the substrate by taking the pattern layer as a mask to form the source region and the drain region; and after the source region and the drain region are formed, removing the pattern layer.
Correspondingly, the embodiment of the invention also provides a semiconductor structure, which comprises: a substrate, wherein a well region and a drift region which are adjacent are formed in the substrate; an isolation layer located within the drift region; and the grid electrode layer is positioned on the substrate at the junction of the well region and the drift region at one side of the isolation layer.
Optionally, the distance from the bottom of the isolation layer to the top of the substrate isTo->
Optionally, the material of the isolation layer is polysilicon.
Optionally, the material of the isolation layer is the same as the material of the gate layer.
Optionally, the gate layer is located at one side of the isolation layer.
Optionally, the semiconductor structure further includes: the groove is positioned in the drift region; the isolation layer is positioned in the groove.
Optionally, the semiconductor structure further includes: and the linear oxide layer is positioned between the isolation layer and the substrate at the bottom of the groove and between the isolation layer and the substrate at the side wall of the groove.
Optionally, the well region and the drift region have doped ions therein, and the doped ions in the drift region are of a different type from the doped ions in the well region, and the semiconductor structure further includes: the source region is positioned in the well region at one side of the grid layer far away from the isolation layer, and the doping ions of the source region are the same as the doping ions in the drift region; the drain region is positioned in the drift region at one side of the isolating layer away from the gate layer, and the doping ions in the drain region are the same as the doping ions in the drift region; and the silicide blocking layer is positioned on the substrate and covers the drift region and the drain region exposed by the grid electrode layer and the isolation layer, and also covers the isolation layer, the side wall of one side of the grid electrode layer close to the isolation layer and part of the top.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
in the embodiment of the invention, after the groove is formed in the drift region, the isolation layer is formed in the groove, and the grid layer is formed on the substrate at the junction of the well region at one side of the groove and the drift region.
In an alternative, the isolation layer and the gate layer are formed in the same process step, which is beneficial to simplifying the process step of forming the isolation layer, and the material of the gate layer is usually a dielectric material (for example, polysilicon), so that the material of the isolation layer is correspondingly a dielectric material, and therefore, the isolation layer can still prolong the length of a current flow path after the LDMOS channel is conducted, thereby improving the pressure resistance of the LDMOS.
Drawings
Fig. 1 to 4 are schematic structural views corresponding to steps in a method for forming a semiconductor structure;
fig. 5 to 14 are schematic structural views corresponding to each step in an embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
As known from the background art, after the field plate technology is introduced in the LDMOS formation process, the voltage withstand performance of the LDMOS needs to be improved. The reason for the poor voltage resistance of a semiconductor structure is analyzed by combining a forming method of the semiconductor structure.
Referring to fig. 1 to 4, schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure are shown.
Referring to fig. 1, a substrate 10 is provided; forming a well region 11 and a drift region 12 adjacent to each other in the substrate 10; forming a Pad Oxide layer (Pad Oxide) 13 on the substrate 10 after forming the well region 11 and the drift region 12; a silicon nitride layer 14 is formed on the pad oxide layer 13.
Referring to fig. 2, the silicon nitride layer 14 and the pad oxide layer 13 are sequentially etched, and an opening 15 exposing the substrate 10 is formed in the silicon nitride layer 14 and the pad oxide layer 13.
Referring to fig. 3, a field oxide layer 20 is formed on the surface of the substrate 10 exposed by the opening 15; after the field oxide layer 20 is formed, the silicon nitride layer 14 and the pad oxide layer 13 are removed.
Referring to fig. 4, after removing the silicon nitride layer 14 (shown in fig. 3) and the pad oxide layer 13 (shown in fig. 3), a gate oxide layer (not shown) is formed on the surface of the substrate 10 where the field oxide layer 20 is exposed; forming a gate layer 30 on the gate oxide layer at the junction of the well region 11 and the drift region 12, the gate layer also extending to the top of part of the field oxide layer 20; a source region 31 is formed in the well region 11 on one side of the gate layer 30, and a drain region 32 is formed in the substrate 10 on the other side of the gate layer 30.
Currently, the process of forming the field oxide layer 20 is typically a local oxidation (Local Oxidation Of Silicon, LOCOS) process, during which O 2 Diffusion occurs in all directions, so that the oxide growth under the silicon nitride layer 14 (shown in fig. 3) lifts the edge of the silicon nitride layer 14, and bird's beak effect (shown by the dashed circle a in fig. 4) easily occurs after forming the gate layer 30 (shown in fig. 4).
The electric field intensity at the beak position is larger, breakdown is easy to occur, and the pressure resistance of the LDMOS is reduced; moreover, the bird's beak position near the source region 31 is the junction between the field oxide layer 20 and the gate oxide layer, so that the electric field strength is high, and when the source region 31 is loaded with voltage, the hot carrier injection effect of the LDMOS is easily increased, which is not beneficial to the reliability of the LDMOS.
In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein a well region and a drift region which are adjacent are formed in the substrate; forming a groove in the drift region; forming an isolation layer in the groove; and forming a gate layer on the substrate at the junction of the well region and the drift region at one side of the groove.
According to the embodiment of the invention, after the groove is formed in the drift region, the isolation layer is formed in the groove, and then the grid layer is formed on the substrate at the junction of the well region at one side of the groove and the drift region.
In order that the above objects, features and advantages of the invention will be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
Fig. 5 to 14 are schematic structural views corresponding to each step in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 5, a substrate 100 is provided, and a well region 110 and a drift region 120 are formed adjacent to each other in the substrate 100.
The substrate 100 is used to provide a process platform for the subsequent formation of semiconductor structures. Specifically, the semiconductor structure formed is an LDMOS.
In this embodiment, taking the LDMOS formed as a planar transistor as an example, the substrate 100 is a planar substrate correspondingly. In other embodiments, when the LDMOS formed is a fin field effect transistor, the base includes a substrate and a discrete fin on the substrate, respectively.
In this embodiment, the base 100 is a silicon substrate. In other embodiments, the substrate may be a germanium substrate, a silicon carbide substrate, a gallium arsenide substrate, or an indium gallium arsenide substrate, or other materials, and the substrate may be a silicon on insulator substrate or a germanium on insulator substrate, or other types of substrates.
The well region 110 and the drift region 120 are formed in the substrate 100, and the well region 110 and the drift region 120 are in contact, the well region 110 serves as a lateral diffusion region to form a channel having a concentration gradient, and the drift region 120 is used to receive a large partial pressure.
The well region 110 and the drift region 120 have dopant ions therein, and the dopant ion type in the drift region 120 is different from the dopant ion type in the well region 110.
When the LDMOS is an N-type transistor, the doped ions In the well region 110 are P-type ions, such As B-ions, ga-ions, or In-ions, and the doped ions In the drift region 120 are N-type ions, such As P-ions, as-ions, or Sb-ions; when the LDMOS is a P-type transistor, the doped ions in the well region 110 are N-type ions, and the doped ions in the drift region 120 are P-type ions.
Specifically, the well region 110 and the drift region 120 are formed in different regions of the substrate, respectively, by selectively doping the substrate.
With continued reference to fig. 5, after forming the well region 110 and the drift region 120 in the substrate, the method further includes: forming a pad oxide layer 101 on the substrate; a hard mask layer 102 is formed on the pad oxide layer 101.
The hard mask layer 102 is used as an etching mask for a subsequent etching process, which is beneficial to improving the shape quality of a groove formed by the subsequent etching, and the hard mask layer 102 can also protect the surface of the substrate 100 in the subsequent process. In this embodiment, the material of the hard mask layer 102 is silicon nitride.
Since the stress of the silicon nitride material is large and dislocation is easily generated on the surface of the substrate 100 when the hard mask layer 102 is formed on the surface of the substrate 100, the pad oxide layer 101 is formed between the substrate 100 and the hard mask layer 102 to serve as a stress buffer layer; in addition, the pad oxide layer 101 is further used for protecting the surface of the substrate 100 from chemical contamination during the subsequent removal of the hard mask layer 102. In this embodiment, the material of the pad oxide layer 101 is silicon oxide.
In this embodiment, the pad oxide layer 101 and the hard mask layer 102 are sequentially formed by a deposition process. Specifically, the deposition process may be a furnace tube process.
Referring to fig. 6, a recess 125 is formed in the drift region 120.
The grooves 125 are used to provide space for the subsequent formation of spacers.
Specifically, the step of forming the recess 125 in the drift region 120 includes: forming a first pattern layer (not shown) on the hard mask layer 102; sequentially etching the hard mask layer 102 and the pad oxide layer 101 by taking the first pattern layer as a mask, and forming an opening 105 in the hard mask layer 102 and the pad oxide layer 101, wherein the opening 105 exposes a part of the substrate 100 corresponding to the drift region 120; removing the first pattern layer after forming the opening 105; after the first pattern layer is removed, the remaining hard mask layer 102 is used as a mask, and the substrate 100 material is etched along the opening 105 to a thickness corresponding to the drift region 120, so as to form the recess 125 in the substrate 100.
In this embodiment, the material of the first pattern layer is photoresist, and after the opening 105 is formed, the first pattern layer is removed by ashing or wet photoresist removal.
In this embodiment, in order to improve the quality of the formation of the recess 125, a dry etching process is used to etch a portion of the thickness of the substrate 100 corresponding to the drift region 120.
In this embodiment, the isolation layer formed in the groove is used for isolating the source region and the drain region of the LDMOS, so that the distance between the drain region and the source region can be prolonged, and when the LDMOS channel is turned on, the length of the current flow path is correspondingly prolonged, thereby improving the voltage resistance and reliability of the LDMOS.
When the LDMOS channel is turned on, a current flows from the drain region, bypasses the isolation layer, and flows to the source region via the channel, that is, the current flow path length includes the bottom length and the sidewall length of the groove 125, so that the depth H of the groove 125 is not too small to effectively improve the voltage resistance and reliability of the LDMOS; however, the depth H of the recess 125 should not be too large, and if the depth H of the recess 125 is too large, the thickness of the substrate 100 corresponding to the remaining drift region 120 at the bottom of the recess 125 is too small, which is easy to adversely affect the current flow, but is easy to reduce the performance of the LDMOS. For this reason, in the present embodiment, after the recess 125 is formed in the drift region 120, the depth H of the recess 125 is To->
It should be noted that, increasing the width (not labeled) of the groove 125 can also extend the length of the current flow path, so in the actual process, the width (not labeled) of the groove 125 is reasonably set according to the setting of the device feature size, thereby improving the voltage resistance and reliability of the LDMOS on the basis that the process can be realized.
Specifically, according to the actual process requirement, the depth H of the groove 125 and the width of the groove 125 are reasonably set, and the depth H of the groove 125 and the width of the groove 125 are mutually matched, so that the pressure resistance and the reliability of the LDMOS are effectively improved on the basis of reducing the process risk.
Referring to fig. 7 and 8 in combination, after forming the recess 125 in the drift region 120, the method further includes: a linear Oxide (Liner Oxide) layer 103 is formed on the bottom and sidewalls of the recess 125 (as shown in fig. 8).
In this embodiment, the linear oxide layer 103 is formed on the bottom surface and the sidewall surface of the recess 125 by performing an oxidation treatment on the bottom and the sidewall of the recess 125.
After the grooves 125 are formed by etching the substrate 100, the substrate 100 generally has protruding corners and has defects on the surface, and in the oxidation process, the protruding corners of the substrate 100 have larger specific surface and are more easily oxidized, so that the linear oxide layer 103 is formed, not only can the defects on the surface of the substrate 100 be repaired, but also the corners can be removed, so that the surface of the substrate 100 is smoother, the lattice quality is improved, the problem that the top corner of the groove 125 is discharged at the top corner is solved, and the pressure resistance and reliability of the LDMOS are improved.
The oxidation treatment can be performed by an oxygen plasma oxidation process or a mixed solution oxidation process of sulfuric acid and hydrogen peroxide. In this embodiment, an In-situ steam generation (In-situ Stream Generation, ISSG) oxidation process is used to oxidize the bottom and the sidewall of the recess 125, so as to form the linear oxide layer 103.
During the oxidation process, the liner oxide layer 101 and the hard mask layer 102 on the liner oxide layer 101 are formed on the surface of the substrate 100, so that the linear oxide layer 103 is formed only on the bottom and the sidewalls of the recess 125.
In this embodiment, the material of the substrate 100 is silicon, and the material of the linear oxide layer 103 is silicon oxide.
It should be noted that, as shown in fig. 7, after forming the recess 125 in the drift region 120, before forming the linear oxide layer 103 (as shown in fig. 8) on the bottom and the sidewall of the recess 125, the method further includes: the hard mask layer 102 is subjected to a lateral etching (i.e., pull Back) process along the sidewall of the opening 105.
The hard mask layer 102 is subjected to transverse etching treatment, so that the effect of rounding a corner angle (corner round) at the top corner of the groove 125 is realized, and the pressure resistance and reliability of the LDMOS are further improved; furthermore, by performing a lateral etching process on the hard mask layer 102 before forming the linear oxide layer 103, it is also advantageous to improve the effect produced by the linear oxide layer 103.
In this embodiment, a wet etching process is used to perform a lateral etching process on the hard mask layer 102, where an etching solution used in the wet etching process is a phosphoric acid solution. The wet etching process has a high etching selectivity and less damage to the substrate 100, which is beneficial to reducing the process risk.
Referring to fig. 9, after forming the liner oxide layer 103 (shown in fig. 8) on the bottom and sidewalls of the recess 125, the hard mask layer 102 and the pad oxide layer 101 are removed.
The surface of the substrate 100 is exposed by removing the hard mask layer 102 and the pad oxide layer 101, thereby providing a process basis for a subsequent process.
In this embodiment, a wet etching process is used to sequentially remove the hard mask layer 102 and the pad oxide layer 101.
Specifically, in the step of removing the hard mask layer 102, the etching solution used in the wet etching process is a phosphoric acid solution, and in the step of removing the pad oxide layer 101, the etching solution used in the wet etching process is a hydrofluoric acid solution.
Since the liner oxide layer 101 is made of the same material as the liner oxide layer 103, the liner oxide layer 103 is also removed during the process of removing the liner oxide layer 101.
Referring to fig. 10, it should also be noted that, since the LDMOS is a high-voltage device, that is, the threshold voltage of the LDMOS is high, after removing the hard mask layer 102 and the pad oxide layer 101, the method further includes: a gate oxide layer 200 is formed on the surface of the substrate 100.
The gate oxide layer 200 is used to electrically isolate the channel and gate layers of the LDMOS.
In this embodiment, the gate oxide layer 200 is made of silicon oxide. In other embodiments, the gate oxide layer may also be silicon oxynitride.
In this embodiment, the gate oxide layer 200 is formed by performing oxidation treatment on the surface of the substrate 100, so that the formation quality and the compactness of the gate oxide layer 200 are improved. Specifically, the oxidation treatment may form a process that is an in situ water vapor generating oxidation process.
Accordingly, the gate oxide layer 200 is also formed on the bottom and sidewalls of the recess 125.
Referring to fig. 10 to 11 in combination, an isolation layer 220 (shown in fig. 11) is formed in the groove 125 (shown in fig. 9); a gate layer 210 is formed on the substrate 100 at the junction of the well 110 and the drift 120 on one side of the recess 125 (as shown in fig. 11).
The isolation layer 220 is located in the drift region 120, and the isolation layer 220 is used for prolonging the length of a current flow path of the LDMOS after the LDMOS channel is turned on, so as to improve the voltage resistance of the LDMOS.
In this embodiment, the gate layer 210 is located at one side of the isolation layer 220, and compared with the field plate technology, this embodiment can avoid the influence of the bird's beak effect on the gate layer, and through the isolation layer, under the condition that the field plate technology is not introduced, the breakdown voltage of the LDMOS can be increased, the hot carrier injection effect of the LDMOS can be improved, and the withstand voltage performance and reliability of the LDMOS can be improved.
In this embodiment, the isolation layer 220 is formed by a deposition process, so as to avoid bird's beak effect, which is beneficial to improving the formation quality and performance of the isolation layer 220.
Specifically, the deposition process is a chemical vapor deposition process.
The gate layer 210 is used to control the turn-on and turn-off of the LDMOS channel. In this embodiment, the material of the gate layer 210 is polysilicon.
In this embodiment, the isolation layer 220 and the gate layer 210 are formed in the same process step. Accordingly, the material of the isolation layer 220 is polysilicon.
By forming the isolation layer 220 and the gate layer 210 in the same process step, it is advantageous to simplify the process step of forming the isolation layer 220; in addition, the polysilicon is a dielectric material, so the isolation layer 220 can still isolate the drain region from the source region, thereby improving the pressure resistance and reliability of the LDMOS.
Specifically, the step of forming the gate layer 210 and the isolation layer 220 includes: forming a gate material layer 250 (as shown in fig. 10) covering the substrate 100 by a deposition process, the gate material layer 250 also filling the grooves 125; the gate material layer 250 is patterned, the remaining gate material layer 250 in the recess 125 is reserved as the isolation layer 220, the remaining gate material layer 250 on the substrate 100 at the junction of the well region 110 and the drift region 120 is reserved as the gate layer 210, and the gate layer 210 is located at one side of the isolation layer 220.
In this embodiment, a chemical vapor deposition process is used to form the gate material layer 250 covering the gate oxide layer 200.
After forming the gate material layer 250, the thickness of the gate material layer 250 on top of the gate oxide layer 200 is determined according to the actual performance requirements of the LDMOS formed. In this embodiment, after the gate material layer 250 is formed, the top of the gate material layer 250 in the recess 125 is higher than the top of the recess 125.
In other embodiments, the top of the gate material layer in the recess may also be lower than or flush with the top of the recess, depending on the thickness setting of the gate material layer and the depth setting of the recess.
Accordingly, in this embodiment, after the isolation layer 220 is formed, the top of the isolation layer 220 is higher than the top of the groove 125.
In this embodiment, the step of patterning the gate material layer 250 includes: the gate material layer 250 is patterned by a photolithography process and a dry etching process to form the discrete gate layer 210 and the isolation layer 220.
By adopting the dry etching method, the sidewall morphology quality of the gate layer 210 and the isolation layer 220 can be effectively improved.
After the gate material layer 250 is patterned, the gate layer 210 is located at one side of the isolation layer 220, that is, the gate layer 210 and the isolation layer 220 are isolated, so that the gate layer 210 and the isolation layer 220 can respectively realize corresponding functions, and cross influence is avoided.
In this embodiment, in order to reduce the alignment difficulty of the photolithography process and reduce the probability of exposing the bottom of a portion of the groove 125 of the isolation layer 220, after the isolation layer 220 is formed, the isolation layer 220 also covers a portion of the gate oxide layer 200 on both sides of the groove 125. In other embodiments, the isolation layer sidewalls may also be flush with the recess sidewalls.
In this embodiment, the isolation layer 220 and the gate layer 210 are formed in the same process step. In other embodiments, the gate layer and isolation layer may also be formed separately in different process steps, for example: forming the isolation layer after forming the gate layer; alternatively, the gate layer is formed after the isolation layer is formed.
In addition, in connection with fig. 12, after forming the gate layer 210 and the isolation layer 220, it further includes: side walls 230 are formed on the side walls of the gate layer 210 and the side walls of the isolation layer 220.
The sidewall 230 is used to define the formation regions of the subsequent source and drain regions, and also is used to protect the sidewalls of the gate layer 210 and the spacer 220 during the subsequent process.
The material of the side wall 230 may be one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride oxide, silicon oxynitride, boron nitride and boron carbonitride, and the side wall 230 may have a single-layer structure or a stacked-layer structure. In this embodiment, the side wall 230 has a single-layer structure, and the material of the side wall 230 is silicon nitride.
Referring to fig. 13, after the sidewall 230 is formed, a source region 310 is formed in the well region 110 on the side of the gate layer 210 away from the isolation layer 220, and a drain region 320 is formed in the drift region 120 on the side of the isolation layer 220 away from the gate layer 210, where the doping ions in the source region 310 and the drain region 320 are the same as the doping ions in the drift region 120.
When static electricity is discharged, a large voltage generated by the static electricity is applied to the drain region 320, so that a PN junction formed by the drift region 120 and the well region 110 breaks down, and an NPN bipolar junction transistor formed by the drift region 120, the well region 110 and the source region 310 is turned on, that is, a channel in the substrate 100 below the gate layer 210 is turned on, and a path is generated from the drain region 320 to the source region 310 for discharging the static electricity, thereby functioning as a protection circuit.
When the LDMOS is an N-type transistor, the doped ions in the drift region 120 are N-type ions, and thus the doped ions in the source region 310 and the drain region 320 are N-type ions, wherein the N-type ions include P-ions, as-ions, or Sb-ions; when the LDMOS is a P-type transistor, the doped ions In the drift region 120 are P-type ions, and the doped ions In the source region 310 and the drain region 320 are P-type ions, wherein the P-type ions include B ions, ga ions, or In ions.
In this embodiment, the source region 310 is formed in the well region 110 of the preset region and the drain region 320 is formed in the drift region 120 of the preset region through a Mask (Mask), so as to avoid doping ions into the substrate 100 of other regions.
Specifically, the step of forming the source region 310 and the drain region 320 includes: forming a second pattern layer 330 on the gate oxide layer 200, wherein the second pattern layer 330 covers the isolation layer 220 and exposes a part of the gate oxide layer 200 on the side of the gate layer 210 away from the isolation layer 220 and a part of the gate oxide layer 200 on the side of the isolation layer 220 away from the gate layer 210; doping the substrate 100 with the second pattern layer 330 as a mask to form the source region 310 and the drain region 320; after forming the source region 310 and the drain region 320, the second pattern layer 330 is removed.
It should be noted that, after the second pattern layer 330 is formed, the second pattern layer 330 also exposes a portion of the top of the gate layer 210 near the drain region 320, so that after the substrate 100 is doped, ions are doped in a portion of the gate layer 210 near the drain region 320, which is favorable for reducing the resistance of the gate layer 210.
By exposing the second pattern layer 330 to the top of the portion of the gate layer 210 near the side of the drain region 320, the process difficulty of the photolithography process is reduced, and the possibility that the substrate 100 between the gate layer 210 and the isolation layer 220 are exposed is reduced, thereby ensuring the normal operation of the device. After the doping treatment is performed on a portion of the top of the gate layer 210, the ions can be uniformly doped in the gate layer 210 under the self-diffusion effect of the doped ions.
In this embodiment, the second pattern layer 330 covers the isolation layer 220, so as to avoid doping ions into the isolation layer 220, thereby ensuring the insulation property in the isolation layer 220.
In this embodiment, the material of the second pattern layer 330 is photoresist, and after the source region 310 and the drain region 320 are formed, the second pattern layer 330 is removed by ashing or wet photoresist removal.
Referring to fig. 14, after forming the source region 310 and the drain region 320, further includes: a Salicide Block (SAB) layer 350 is formed on the substrate 100, and the Salicide Block layer 350 covers the drift region 120 and the drain region 320 where the gate layer 210 and the isolation layer 220 are exposed, and also covers the isolation layer 220 and a sidewall and a portion of the top of the gate layer 210 on a side near the isolation layer 220.
By the silicide blocking layer 350, the growth of a subsequent silicide (Salicide) layer is prevented, thereby ensuring the normal operation of the device.
Note that, the side walls 230 are formed on the side walls of the gate layer 210 and the isolation layer 220, so that the silicide blocking layer 350 also covers the side walls 230 on the side walls of the isolation layer 220, and the side walls 230 on the side walls of the gate layer 210 close to the isolation layer 220.
In this embodiment, the silicide blocking layer 350 is formed by a deposition process, a photolithography process, and an etching process. Specifically, the material of the silicide blocking layer 350 is silicon oxide. In other embodiments, the material of the silicide blocking layer may also be silicon nitride, or the silicide blocking layer may also be a stacked structure formed by a silicon oxide layer and a silicon nitride layer.
Correspondingly, the embodiment of the invention also provides a semiconductor structure. With continued reference to fig. 14, a schematic structural diagram of one embodiment of a semiconductor structure of the present invention is shown.
The semiconductor structure includes: a substrate 100, wherein a well region 110 and a drift region 120 are formed in the substrate 100; an isolation layer 220 located within the drift region 120; the gate layer 210 is located on the substrate 100 at the junction of the well region 110 and the drift region 120 at one side of the isolation layer 220.
The substrate 100 provides a process platform for the formation of the semiconductor structure. Specifically, the semiconductor structure is an LDMOS.
In this embodiment, taking the LDMOS formed as a planar transistor as an example, the substrate 100 is a planar substrate correspondingly. In other embodiments, when the LDMOS formed is a fin field effect transistor, the base includes a substrate and a discrete fin on the substrate, respectively.
In this embodiment, the base 100 is a silicon substrate. In other embodiments, the substrate may be a germanium substrate, a silicon carbide substrate, a gallium arsenide substrate, or an indium gallium arsenide substrate, or other materials, and the substrate may be a silicon on insulator substrate or a germanium on insulator substrate, or other types of substrates.
The well region 110 and the drift region 120 are located in the substrate 100, and the well region 110 and the drift region 120 are in contact, the well region 110 acts as a lateral diffusion region to form a channel having a concentration gradient, and the drift region 120 is used to withstand a large partial pressure.
The well region 110 and the drift region 120 have dopant ions therein, and the dopant ion type in the drift region 120 is different from the dopant ion type in the well region 110.
When the LDMOS is an N-type transistor, the doped ions In the well region 110 are P-type ions, such As B-ions, ga-ions, or In-ions, and the doped ions In the drift region 120 are N-type ions, such As P-ions, as-ions, or Sb-ions; when the LDMOS is a P-type transistor, the doped ions in the well region 110 are N-type ions, and the doped ions in the drift region 120 are P-type ions.
The isolation layer 220 is located in the drift region 120, and the isolation layer 220 is used for isolating the source region 310 and the drain region 320, so as to prolong the distance between the source region 310 and the drain region 320, and correspondingly prolong the length of a current flow path after the LDMOS channel is conducted, so that the voltage resistance and reliability of the LDMOS are improved.
In this embodiment, the gate layer 210 is located at one side of the isolation layer 220, and compared with the field plate technology, this embodiment can avoid the influence of the bird's beak effect on the gate layer 210, and through the isolation layer 220, under the condition that the field plate technology is not introduced, the breakdown voltage of the LDMOS can be increased, the hot carrier injection effect of the LDMOS can be improved, and the voltage-withstanding performance and reliability of the LDMOS can be improved.
Thus, the material of the isolation layer 220 is a dielectric material.
In this embodiment, the isolation layer 220 is formed by a deposition process (e.g., a chemical vapor deposition process), which can avoid bird's beak effect and is beneficial to improving the formation quality and performance of the isolation layer 220 compared with the scheme of forming the field oxide layer by using a local oxidation process.
It should be noted that, when the LDMOS channel is turned on, a current flows from the drain region 320, bypasses the isolation layer 220, and flows to the source region 310 via the channel, that isThe current flow path length includes the sidewall length and the bottom length of the isolation layer 220 in the drift region 120, so in order to effectively improve the voltage-withstanding performance and reliability of the LDMOS, the distance (not shown) from the bottom of the isolation layer 220 to the top of the substrate 100 should not be too small; however, the distance from the bottom of the isolation layer 220 to the top of the substrate 100 should not be too large, and if the distance from the bottom of the isolation layer 220 to the top of the substrate 100 is too large, the thickness of the substrate 100 corresponding to the remaining drift region 120 under the isolation layer 220 is too small, which is easy to adversely affect the current flow, but is easy to reduce the performance of the LDMOS. For this purpose, in this embodiment, the distance from the bottom of the isolation layer 220 to the top of the substrate 100 is To->
It should be further noted that, along the direction that the drain region 320 points to the source region 310, increasing the width (not labeled) of the isolation layer 220 located in the drift region 120 can also extend the length of the current flow path, so in the actual process, the width of the isolation layer 220 located in the drift region 120 is reasonably set according to the setting of the device feature size, thereby improving the voltage-withstanding performance and reliability of the LDMOS on the basis that the process is achievable.
Specifically, according to the actual process requirement, the distance from the bottom of the isolation layer 220 to the top of the substrate 100 and the width of the isolation layer 220 in the drift region 120 are reasonably set, and the depth and the width are mutually matched, so that the pressure resistance and the reliability of the LDMOS are effectively improved on the basis of reducing the process risk.
The gate layer 210 is used to control the turn-on and turn-off of the LDMOS channel. In this embodiment, the material of the gate layer 210 is polysilicon.
In this embodiment, the material of the isolation layer 220 is the same as the material of the gate layer 210. Specifically, the isolation layer 220 and the gate layer 210 are formed in the same process step, thereby facilitating the simplification of the process step of forming the isolation layer 220; in addition, the polysilicon is a dielectric material, so the isolation layer 220 can still isolate the drain region 320 from the source region 310, thereby improving the pressure resistance and reliability of the LDMOS.
Accordingly, in this embodiment, the material of the isolation layer 220 is polysilicon.
In this embodiment, the gate layer 210 is located at one side of the isolation layer 220, that is, the gate layer 210 and the isolation layer 220 are isolated, which is also beneficial to enabling the gate layer 210 and the isolation layer 220 to respectively realize corresponding functions, so as to avoid cross influence.
The thickness of the gate layer 210 is dependent on the actual performance requirements of the LDMOS, and the thickness of the isolation layer 220 is dependent on the thickness of the gate layer 210. In this embodiment, the top of the isolation layer 220 is higher than the top of the substrate 100.
In other embodiments, the top of the isolation layer in the recess may also be lower than or flush with the top of the substrate, depending on the thickness setting of the gate layer and the depth setting of the recess.
In the semiconductor process, the process of forming the gate layer 210 and the isolation layer 220 generally includes a deposition process, a photolithography process and an etching process, so in this embodiment, in order to reduce the alignment difficulty of the photolithography process, the width of the isolation layer 220 above the top of the substrate 100 is greater than the width of the isolation layer 220 located in the drift region 120 along the direction in which the drain region 320 points to the source region 310, i.e., the isolation layer 220 above the top of the substrate 100 also covers a portion of the substrate 100. In other embodiments, it may also be: the isolation layer side wall higher than the top of the substrate is flush with the isolation layer side wall in the drift region.
It should be noted that, since the LDMOS is a high-voltage device, that is, the threshold voltage of the LDMOS is high, the semiconductor structure further includes the gate oxide layer 200 on the surface of the substrate 100.
Specifically, the gate oxide layer 200 is positioned between the gate layer 210 and the substrate 100, between the isolation layer 220 and the substrate 100, and on the substrate 100 where the gate layer 210 and the isolation layer 220 are exposed.
The gate oxide layer 200 serves to electrically isolate the channel of the LDMOS from the gate layer 210.
In this embodiment, the gate oxide layer 200 is made of silicon oxide. In other embodiments, the gate oxide layer may also be silicon oxynitride.
Note that, the sidewall of the gate layer 210 and the sidewall of the isolation layer 220 are formed with the sidewall 230.
The sidewall 230 is used to define the formation regions of the source region and the drain region, and also is used to protect the sidewalls of the gate layer 210 and the spacer 220 during the formation of the semiconductor structure.
The material of the side wall 230 may be one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride oxide, silicon oxynitride, boron nitride and boron carbonitride, and the side wall 230 may have a single-layer structure or a stacked-layer structure. In this embodiment, the side wall 230 has a single-layer structure, and the material of the side wall 230 is silicon nitride.
In this embodiment, the semiconductor structure further includes: a source region 310 located in the well region 110 on a side of the gate layer 210 away from the isolation layer 220, wherein the doping ions of the source region 310 are the same as the doping ions in the drift region 120; and a drain region 320 located in the drift region 120 on a side of the isolation layer 220 away from the gate layer 210, wherein the doping ions in the drain region 320 are the same type as the doping ions in the drift region 120.
When static electricity is discharged, a large voltage generated by the static electricity is applied to the drain region 320, so that a PN junction formed by the drift region 120 and the well region 110 breaks down, and an NPN bipolar junction transistor formed by the drift region 120, the well region 110 and the source region 310 is turned on, that is, a channel in the substrate 100 below the gate layer 210 is turned on, and a path is generated from the drain region 320 to the source region 310 for discharging the static electricity, thereby functioning as a protection circuit.
When the LDMOS is an N-type transistor, the doped ions in the drift region 120 are N-type ions, and thus the doped ions in the source region 310 and the drain region 320 are N-type ions, wherein the N-type ions include P-ions, as-ions, or Sb-ions; when the LDMOS is a P-type transistor, the doped ions In the drift region 120 are P-type ions, and the doped ions In the source region 310 and the drain region 320 are P-type ions, wherein the P-type ions include B ions, ga ions, or In ions.
In this embodiment, the source region 310 and the drain region 320 are formed by doping the substrate 100, and the doping treatment is further performed on top of the gate layer 210 during the process of forming the source region 310 and the drain region 320, so that the gate layer 210 also has doping ions therein, and the doping ions in the gate layer 210 have the same type as the doping ions in the source region 310, so as to be beneficial to reducing the resistance of the gate layer 210.
In this embodiment, the material of the isolation layer 220 is polysilicon undoped with ions, i.e., the material of the isolation layer 220 is an intrinsic material, so as to ensure the insulation property in the isolation layer 220.
In this embodiment, the semiconductor structure further includes: a silicide blocking layer 350 on the substrate 100, wherein the silicide blocking layer 350 covers the drift region 120 and the drain region 320 exposed by the gate layer 210 and the isolation layer 220, and also covers the isolation layer 220 and a sidewall and a portion of the top of the gate layer 210 near one side of the isolation layer 220.
The silicide blocking layer 350 covers the drift region 120 and the drain region 320 exposed by the gate layer 210 and the isolation layer 220, and also covers the isolation layer 220 and a sidewall and a portion of the top of the gate layer 210 near one side of the isolation layer 220, so as to prevent the growth of the silicide layer, thereby ensuring the normal operation of the device.
Note that, the side walls 230 are formed on the side walls of the gate layer 210 and the isolation layer 220, so that the silicide blocking layer 350 also covers the side walls 230 on the side walls of the isolation layer 220, and the side walls 230 on the side walls of the gate layer 210 close to the isolation layer 220.
In this embodiment, the silicide blocking layer 350 is made of silicon oxide. In other embodiments, the material of the silicide blocking layer may also be silicon nitride, or the silicide blocking layer may also be a stacked structure formed by a silicon oxide layer and a silicon nitride layer.
The semiconductor structure may be formed by the forming method described in the foregoing embodiments, or may be formed by other forming methods. For a specific description of the semiconductor structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiment, which is not repeated here.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (10)

1. A method of forming a semiconductor structure, comprising:
Providing a substrate, wherein a well region and a drift region which are adjacent are formed in the substrate;
forming a groove in the drift region;
forming an isolation layer in the groove, wherein the isolation layer has an insulating property;
forming a grid layer on the substrate at the junction of the well region and the drift region at one side of the groove;
wherein the isolation layer and the gate layer are formed in the same process step.
2. The method of forming a semiconductor structure according to claim 1, wherein in the step of forming a recess in the drift region, a depth of the recess isTo->
3. The method of forming a semiconductor structure of claim 1, wherein forming a recess in the drift region comprises: and etching a substrate material with partial thickness corresponding to the drift region by adopting a dry etching process, and forming the groove in the substrate.
4. The method of forming a semiconductor structure of claim 1, wherein the material of the isolation layer is polysilicon.
5. The method of forming a semiconductor structure of claim 1, wherein an isolation layer is formed within the recess by a deposition process.
6. The method of claim 5, wherein in the step of forming an isolation layer in the recess, the deposition process is a chemical vapor deposition process.
7. The method of forming a semiconductor structure of claim 1, wherein the step of forming the gate layer and isolation layer comprises: forming a gate material layer covering the substrate through a deposition process, wherein the gate material layer is also positioned in the groove;
and patterning the gate material layer, reserving the residual gate material layer in the groove as the isolation layer, reserving the residual gate material layer on the substrate at the junction of the well region and the drift region as the gate layer, and positioning the gate layer on one side of the isolation layer.
8. The method of forming a semiconductor structure of claim 1, further comprising, after forming a recess in the drift region, prior to forming an isolation layer in the recess: and forming a linear oxide layer at the bottom and the side wall of the groove.
9. The method of forming a semiconductor structure of claim 1, wherein in the step of providing a substrate, the well region and the drift region have dopant ions therein, and the dopant ion type in the drift region is different from the dopant ion type in the well region;
after forming the gate layer and the isolation layer, the method further comprises: forming a source region in a well region at one side of the gate layer far away from the isolation layer, forming a drain region in a drift region at one side of the isolation layer far away from the gate layer, wherein doping ions in the source region and the drain region are the same as doping ions in the drift region; after the source region and the drain region are formed, a silicide blocking layer is formed on the substrate, and covers the drift region and the drain region exposed by the gate layer and the isolation layer, and also covers the isolation layer, and the side wall and part of the top of the gate layer, which is close to one side of the isolation layer.
10. The method of forming a semiconductor structure of claim 9, wherein forming the source and drain regions comprises: forming a pattern layer on the substrate, wherein the pattern layer covers the isolation layer and exposes a partial area substrate on one side of the gate layer away from the isolation layer and a partial area substrate on one side of the isolation layer away from the gate layer;
doping the substrate by taking the pattern layer as a mask to form the source region and the drain region;
and after the source region and the drain region are formed, removing the pattern layer.
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