CN116185508A

CN116185508A - Baseboard management controller and server

Info

Publication number: CN116185508A
Application number: CN202310140523.5A
Authority: CN
Inventors: 王俊祥
Original assignee: Suzhou Inspur Intelligent Technology Co Ltd
Current assignee: Suzhou Inspur Intelligent Technology Co Ltd
Priority date: 2023-02-20
Filing date: 2023-02-20
Publication date: 2023-05-30

Abstract

The embodiment of the invention provides a substrate management controller and a server, wherein the substrate management controller comprises a management chip, the management chip comprises a first processing module and a second processing module which are mutually connected, and the first processing module comprises a low-speed transmission interface, a high-speed transmission interface and a processor; the processor is in communication connection with the high-speed transmission interface, and is used for receiving and processing information transmitted by the high-speed transmission interface, the second processing module is in communication connection with the low-speed transmission interface, and the second processing module is used for receiving and processing information transmitted by the low-speed transmission interface. The baseboard management controller provided by the embodiment of the invention breaks the receiving process of the information transmitted by the high-speed transmission interface and the receiving process of the information transmitted by the low-speed transmission interface, so as to improve the overall efficiency of the baseboard management controller, and further improve the operation efficiency of the baseboard management controller, thereby achieving better system efficiency.

Description

Baseboard management controller and server

Technical Field

The present invention relates to the field of server technologies, and in particular, to a baseboard management controller and a server.

Background

The BMC (baseboard management controller) is used as a server management control system, and is configured to monitor a temperature, a voltage, a fan, a power supply, etc. of a server, and perform corresponding adjustment according to a monitoring result, so as to ensure that the server is in a normal working state.

In the prior art, the BMC uses an SOC (system on a chip) chip of an ARM architecture, and most of communication interfaces common to the outside are low-speed transmission interfaces, such as I2C, UART, LPC and LAN. However, the lower rate of the low speed transmission interface may affect the operation performance of the BMC, so that the operation efficiency of the BMC is lower.

Disclosure of Invention

The embodiment of the invention aims to provide a baseboard management controller for solving the technical problem of low running efficiency of BMC in the prior art. The specific technical scheme is as follows:

in a first aspect, an embodiment of the present invention provides a baseboard management controller, including a management chip, where the management chip includes a first processing module and a second processing module that are interconnected, and the first processing module includes a low-speed transmission interface, a high-speed transmission interface, and a processor;

the processor is in communication connection with the high-speed transmission interface, the processor is used for receiving and processing information transmitted by the high-speed transmission interface, the second processing module is in communication connection with the low-speed transmission interface, and the second processing module is used for receiving and processing information transmitted by the low-speed transmission interface.

Optionally, the first processing module further includes a memory controller, where the memory controller is respectively in communication connection with the processor and the second processing module, the memory controller is configured to be in communication connection with a memory, the second processing module is configured to store the received information transmitted by the low-speed transmission interface to the memory, and the processor is configured to read the information stored in the memory by the second processing module from the memory.

Optionally, the management chip is a socfpgas chip, the first processing module is an HPS module, and the second processing module is an FPGA module.

Optionally, the low-speed transmission interface includes a first low-speed transmission interface, where the first low-speed transmission interface is used to connect with a temperature sensor, the first low-speed transmission interface is used to receive current temperature information output by the temperature sensor and transmit the current temperature information to the second processing module, the second processing module is used to store the received current temperature information to the memory, and the processor is used to read the current temperature information from the memory.

Optionally, the memory controller is communicatively connected to the memory through a memory bus, and the memory is a double-rate synchronous dynamic random access memory.

Optionally, the low-speed transmission interface includes at least one of an I2C interface, a UART interface, a GPIO interface, and an SPI interface.

Optionally, the high-speed transmission interface includes at least one of a usb otg interface and an Ethernet interface.

Optionally, the processor is a dual core processor.

In a second aspect, an embodiment of the present invention provides a server, including any one of the baseboard management controllers described above.

Optionally, the server includes a motherboard, the baseboard management controller is integrated on the motherboard, the server further includes a memory, the baseboard management controller is in communication connection with the memory through the memory controller, the second processing module is configured to store the received information transmitted by the low-speed transmission interface to the memory, and the processor is configured to read the information stored in the memory by the second processing module from the memory.

The processor is used for receiving and processing the information transmitted by the high-speed transmission interface, and the second processing module is used for receiving and processing the information transmitted by the low-speed transmission interface, namely, the receiving processing of the information transmitted by the high-speed transmission interface and the receiving processing of the information transmitted by the low-speed transmission interface are split, so that the overall efficiency of the substrate management controller is improved, and the operation efficiency of the substrate management controller is further improved, so that better system efficiency is achieved.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below.

FIG. 1 is a schematic diagram of a BMC according to the prior art;

fig. 2 is a schematic diagram of a baseboard management controller according to an embodiment of the invention;

fig. 3 is a schematic diagram of a baseboard management controller according to an embodiment of the invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be described below with reference to the accompanying drawings in the embodiments of the present invention.

The examples of the present invention are only for explaining the present invention and are not intended to limit the scope of the present invention. The invention is more particularly described by way of example in the following paragraphs with reference to the drawings. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.

Referring to fig. 1, BMCs used on the server are all SoC chips of ARM architecture, and internally mainly run embeddec, and external common communication interfaces include I2C, UART, LPC and LAN, which are mainly low-speed transmission interfaces. However, the lower rate of the low speed transmission interface may affect the operation performance of the BMC, so that the operation efficiency of the BMC is lower.

In order to solve the above-mentioned problems, embodiments of the present invention provide a baseboard management controller and a server, and the baseboard management controller and the server are specifically described below.

In a first aspect, referring to fig. 2 and fig. 3, a baseboard management controller provided by an embodiment of the present invention includes a management chip, where the management chip includes a first processing module and a second processing module that are interconnected, and the first processing module includes a low-speed transmission interface, a high-speed transmission interface, and a processor; the processor is in communication connection with the high-speed transmission interface, and is used for receiving and processing information transmitted by the high-speed transmission interface, the second processing module is in communication connection with the low-speed transmission interface, and the second processing module is used for receiving and processing information transmitted by the low-speed transmission interface.

Specifically, the baseboard management controller, i.e. the BMC, is applied to the server and is used for monitoring the operation status of the server. The server includes a motherboard onto which the baseboard management controller can be integrated. It should be noted that, in the server, the baseboard management controller is an independent system, and it does not depend on other hardware (such as CPU, etc.) on the system, and does not depend on BIOS (basic input output system), OS, etc., but the baseboard management controller may interact with BIOS and OS, so that better management effect can be achieved, and system management software under OS may cooperate with the baseboard management controller to achieve better management effect. Whether the server is provided with an operating system or not, whether the server is started or not can be monitored as long as the baseboard management controller is electrified. A baseboard management controller is a collection of detection and control functions, the object of which is hardware in a server. For example, the temperature, the voltage, the fan, the power supply and the like of the server are detected, and corresponding adjustment work is performed to ensure that the server is in a normal working state.

The management chip comprises a first processing module and a second processing module, and the first processing module and the second processing module can be respectively arranged on different layouts or bare chips. The distribution of the first processing module and the second processing module may for example be as follows: the first processing module and the second processing module may be disposed on different layouts, that is, different layout areas of the same die (die); the first processing module and the second processing module may be disposed on different dies, and subsequently may be packaged in a chip (chip) by stacking and packaging.

The first processing module and the second processing module are interconnected, that is, the first processing module and the second processing module can communicate with each other to realize data interaction between the two parts, and the first processing module and the second processing module can be interconnected through an AXI bus. The second processing module may be a field programmable gate array. The processor may be an ARM processor, and the processor is configured to run EmbeddedLinux to implement the functions required by the BMC system. The processor is a core operation unit of the whole baseboard management controller, is a hardware supporting part for operating the operating system, and is responsible for communication management, memory management, algorithm execution and other functions of the whole baseboard management controller. The first processing module comprises a plurality of low-speed transmission interfaces and a plurality of high-speed transmission interfaces, wherein the low-speed transmission interfaces comprise at least one of an I2C interface, a UART interface, a GPIO interface and an SPI interface, and the high-speed transmission interfaces comprise at least one of a USBOTG interface and an Ethernet interface.

The processor is communicatively coupled to each of the high speed transmission interfaces, and the second processing module is communicatively coupled to each of the low speed transmission interfaces. The high-speed transmission interface is used for connecting the first external equipment, information sent by the first external equipment is transmitted to the processor through the high-speed transmission interface, and the processor receives and processes the information transmitted by the high-speed transmission interface. The first external devices of the different high speed transmission interface connections are different and the second external devices of the different low speed transmission interface connections are different. The low-speed transmission interface is used for connecting second external equipment, information sent by the second external equipment is transmitted to the second processing module through the low-speed transmission interface, and the second processing module receives and processes the information transmitted by the low-speed transmission interface. It should be noted that, for the second processing module, the method steps executed are as follows: receiving information transmitted by a low-speed transmission interface; and processing the received information transmitted by the low-speed transmission interface. The method steps executed by the processor are as follows: receiving information transmitted by a high-speed transmission interface; and processing the received information transmitted by the high-speed transmission interface.

The baseboard management controller often needs to read temperature information to control the number of fan revolutions, so as to achieve effective heat dissipation. The temperature sensor mostly uses a low-rate I2C interface as a transmission interface. For example, when one of the low-speed transmission interfaces is an I2C interface and the second external device connected to the I2C interface is a temperature sensor, current temperature information output by the temperature sensor is transmitted to the second processing module through the I2C interface, and the second processing module receives and processes the current temperature information.

The first processing module further comprises a memory controller which is respectively in communication connection with the processor and the second processing module, the memory controller is used for being in communication connection with the memory, the second processing module is used for storing the received information transmitted by the low-speed transmission interface to the memory, and the processor is used for reading the information stored in the memory by the second processing module from the memory.

Specifically, the memory controller may be a multiport SDRAM (SynchronousDynamic Random-access memory) controller, supporting DDR (Double data rate) 2, DDR3L and LPDDR2. The memory connected to the memory controller may be DDR2SDRAM, DDR3LSDRAM, LPDDR2SDRAM, etc. Currently, in other embodiments, the memory may also be implemented by any type or combination of volatile or nonvolatile memory devices such as Static Random Access Memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), and the like. It should be noted that the processor and the second processing module share the same memory, that is, the processor and the second processing module may both store information into the memory, or may read information from the memory, that is, the processor and the second processing module may exchange access messages with each other.

The second processing module may store the information transmitted by the low speed transmission interface to the memory after receiving the information transmitted by the low speed transmission interface, and then the processor may read the information transmitted by the low speed transmission interface from the memory. For example, when one of the low-speed transmission interfaces is an I2C interface and the second external device connected to the I2C interface is a temperature sensor, current temperature information output by the temperature sensor is transmitted to the second processing module through the I2C interface, the second processing module can store the current temperature information into the memory after receiving the current temperature information, and then the processor can read the current temperature information from the memory. At this time, the processor is completely operated in a high-rate energy state, and no waiting for the low-rate temperature sensor to return current temperature information is needed. In the embodiment of the invention, the memory controller is respectively in communication connection with the processor and the second processing module, and the memory controller is used for setting the communication connection memory, so that the processor and the second processing module can exchange access information with each other.

It should be noted that, for the second processing module, the method steps executed are as follows: receiving information transmitted by a low-speed transmission interface; and storing the received information transmitted by the low-speed transmission interface into a memory. Specifically, storing the received information transmitted by the low-speed transmission interface into the memory includes: and sending the received information transmitted by the low-speed transmission interface to a memory controller so that the memory controller stores the information transmitted by the low-speed transmission interface received by the second processing module to a memory. The method steps executed by the processor are as follows: and reading the information stored by the second processing module from the memory. The method steps that it executes for the processor are as follows: receiving information transmitted by a high-speed transmission interface; and processing the received information transmitted by the high-speed transmission interface and/or storing the received information transmitted by the high-speed transmission interface into a memory.

The management chip is a socfpa chip, the first processing module is an HPS (hard processor system) module, and the second processing module is an FPGA (field programmable gate array) module.

Specifically, in order to solve the requirements of high-speed data acquisition, processing and transmission, each large traditional FPGA manufacturer has proposed a socfpa chip with an embedded hard core processor. The basic architecture of the SoCFPGA chip is to integrate the FPGA and ARM processors on the same silicon chip and connect them by high-speed and high-bandwidth interconnection architecture. The SoCFPGA chip integrates the advantages of ARM and FPGA, namely, the SoCFPGA chip has the advantages of the ARM processor for realizing flexible control, graphical interface display and network transmission and running a mature Linux operating system, and has the advantages of high-speed parallel processing, flexible customization and abundant IO units of the FPGA module.

The SoCFPGA chip is a chip with a hard core processor system embedded in the FPGA programmable logic chip. The socfpa chip may employ an intel ariaavsocfpa chip as shown in fig. 3. The SoCFPGA chip can integrate discrete processor, FPGA and Digital Signal Processing (DSP) functions in an ARM-based user customizable system on chip (SoC), thereby reducing system power consumption and system cost, reducing circuit board area and improving system performance.

The processor and the FPGA module in the HPS module in the SoCFPGA chip can be independently started and do not interfere with each other, and even one can not be electrified, the other can work normally. Although the HPS module and FPGA module can operate independently, they are closely linked by a high-performance AXI bus bridging broadband system interconnect. The HPS, namely the hard core processor system is constructed based on an ARMCortex-A9 processor, the ARM Cortex-A9 processor is a core operation unit of the whole baseboard management controller, is a hardware supporting part for operating the operating system and is responsible for the communication management, the memory management, the algorithm execution and other functions of the whole baseboard management controller. The memory serves as a memory exchange unit for the processor. The socfpa chip enables interconnection between the first processing module and the second processing module by using a high bandwidth interconnection backbone.

The Intel ArriaVSoCFPGA chip is provided with a dual-core ARMCortex-A9 processor, the efficiency can be compared with an AspeedAST2600, and the FPGA module has more flexible IO characteristics and can plan different use requirements according to different use scenes or client requirements. In the embodiment of the invention, the substrate management controller uses an Intel ArriaVSoCFPGA chip, and uses a dual-core ARMCortex-A9 processor of the Intel ArriaVSoCFPGA chip to run EmbeddLinux so as to realize the functions required by the substrate management controller, transfer a low-speed transmission interface to an FPGA module for management, and exchange access information with the FPGA module through a shared memory.

In the embodiment of the invention, a SoCFPGA chip is used as a chip of the substrate management controller, a dual-core ARMCortex-A9 processor with high efficiency energy is used for communicating with a high-speed transmission interface and processing the work of the substrate management controller, and an FPGA module is used for communicating with the high-speed transmission interface so as to improve the overall efficiency of the substrate management controller; the performance of the SoCFPGA chip is utilized to split the processing of the information transmitted by the high-speed transmission interface and the processing of the information transmitted by the low-speed transmission interface so as to improve the operation efficiency of the baseboard management controller. It should be noted that, the FPGA module further has flexible IO characteristics, and compared with the current AST2600, the FPGA module can plan the required IO transmission interface according to the use condition. By utilizing the characteristics of the FPGA module, a logic circuit can be designed by self so as to accelerate the operation of data, such as AI operation. The socfpa chip can even replace the existing CPLD (complex programmable logic device) used for PowerSequence, and can replace the system which originally needs two chips (bmc+cpld) only by one SoC FPGA chip.

The low-speed transmission interface comprises a first low-speed transmission interface, the first low-speed transmission interface is used for being connected with the temperature sensor, the first low-speed transmission interface is used for receiving current temperature information output by the temperature sensor and transmitting the current temperature information to the second processing module, the second processing module is used for storing the received current temperature information into the memory, and the processor is used for reading the current temperature information from the memory.

Specifically, the first low-speed transmission interface may be an I2C interface, the first processing module includes a plurality of low-speed transmission interfaces, and the plurality of low-speed transmission interfaces may include two first low-speed transmission interfaces, that is, may include two I2C interfaces. Of course, the number of the I2C interfaces may also be specifically set according to actual requirements. The I2C interface is used for communication connection with a temperature sensor, which may be used for monitoring the current temperature of the motherboard in the server, or may be used for monitoring the current temperature of the CPU on the motherboard.

In the embodiment of the invention, the first low-speed transmission interface is used for receiving the current temperature information output by the temperature sensor and transmitting the current temperature information to the second processing module, namely the second processing module can read the current temperature information output by the temperature sensor. It should be noted that, the manner of reading the current temperature information output by the temperature sensor by the second processing module may be to automatically read the temperature information output by the temperature sensor by a polling manner or to read the temperature information output by the temperature sensor in real time by a manual command manner. The baseboard management controller is also electrically connected with a fan, and the processor can control the operation of the fan according to the current temperature information read from the memory.

In the embodiment of the invention, the method executed by the second processing module comprises the following steps: receiving current temperature information transmitted by a first low-speed transmission interface; the current temperature information is stored to a memory. Wherein storing the current temperature information to the memory comprises: and sending the received current temperature information transmitted by the first low-speed transmission interface to the memory controller so that the memory controller stores the current temperature information to the memory. The method executed by the processor comprises the following steps: reading current temperature information from a memory; and controlling the operation of the fan according to the current temperature information.

It should be noted that, the temperature sensor is an example of a device connected to the first low-speed transmission interface, in practical application, the plurality of low-speed transmission interfaces may further include a second low-speed transmission interface, the second low-speed transmission interface may be an I2C interface, the second low-speed transmission interface may be electrically connected to the voltage sensor, and the voltage sensor may be used to monitor voltages of a core power supply, an IO power supply, a memory power supply, and a peripheral interface power supply of the CPU on the motherboard in real time. At this time, the second low-speed transmission interface is used for receiving the current voltage information output by the voltage sensor and transmitting the current voltage information to the second processing module, the second processing module is used for storing the received current voltage information into the memory, and the processor is used for reading the current voltage information from the memory. At this time, the second processing module executes the following method steps: receiving current voltage information transmitted by a second low-speed transmission interface; the current voltage information is stored to a memory. Wherein storing the current voltage information to the memory includes: and sending the received current voltage information transmitted by the second low-speed transmission interface to the memory controller so that the memory controller stores the current voltage information to the memory. The method executed by the processor comprises the following steps: reading current voltage information from a memory; and sending the current voltage information to a display for display.

When the memory is a DDRSDRAM, the processor is an ARMCortex-A9 processor, and the second processing module is an FPGA module, the FPGA module can be used for reading the current temperature information output by the temperature sensor and storing the current temperature information returned by the temperature sensor in the DDR SDRAM, ARMCortex-A9 processor, the current temperature information can be directly obtained only by reading the DDRSDRAM, the ARMCortex-A9 processor can be completely operated in a high-rate energy state, and the temperature information returned by the temperature sensor with low speed is not required to be waited, so that the baseboard management controller can achieve better system efficiency.

The memory controller is in communication connection with the memory through a memory bus, and the memory is a double-rate synchronous dynamic random access memory. Specifically, the memory controller may be a multiport SDRAM controller, namely sharedmultiport ddr SDRAM controller shown in fig. 3. The memory may be provided in one or more. The memory may be DDR2SDRAM, DDR3LSDRAM, LPDDR2SDRAM, etc. In the embodiment of the invention, the memory controller is in communication connection with the memory through the memory bus and the memory is arranged as the double-rate synchronous dynamic random access memory, so that the reading rate of the processor when the processor reads the information on the memory through the memory controller can be ensured, and the processor can be ensured to operate in a high-rate energy state.

The low-speed transmission interface comprises at least one of an I2C interface, a UART interface, a GPIO interface and an SPI interface.

Specifically, referring to fig. 3, the baseboard management controller includes a plurality of low-speed transmission interfaces, and the plurality of low-speed transmission interfaces may include two I2C interfaces, where the I2C interfaces are used to implement communication between the baseboard management controller and an external device, such as a temperature sensor. The plurality of low speed transmission interfaces may include two UART interfaces, UART or universal asynchronous receiver Transmitter (universal asynchronous receiver Transmitter), which is a form of physical interface for serial communication that converts data to be transmitted between serial and parallel communications. As a chip for converting parallel input signals into serial output signals, UARTs are typically integrated on the connection of other communication interfaces.

The plurality of low speed transmission interfaces may include a plurality of GPIO interfaces, i.e., general purpose input output interfaces. The plurality of low-speed transmission interfaces can also comprise SPI interfaces, namely serial peripheral interfaces, the SPI interfaces carry out synchronous serial data transmission between the substrate management controller and low-speed external equipment, under the shift pulse of the main device, data are transmitted according to bits, the high bits are in front, the low bits are in back, full duplex communication is realized, the data transmission speed is generally faster than that of an I2C bus, and the speed can reach tens of Mbps. In the embodiment of the invention, through the arrangement of the I2C interface, the UART interface, the GPIO interface and the SPI interface, the connection of different types of low-speed external equipment can be realized. It should be noted that the number of the I2C interfaces, UART interfaces, GPIO interfaces, and SPI interfaces is only illustrative, and the number can be adaptively modified according to actual requirements.

The high-speed transmission interface comprises at least one of a USBOTG interface and an Ethernet interface.

Specifically, the baseboard management controller includes a plurality of high-speed transmission interfaces, the plurality of high-speed transmission interfaces may include two usb OTG interfaces, and the usb OTG interfaces support an OTG (on-the-go) protocol, and the OTG protocol can implement data exchange between each electronic device directly without a computer, so that the two electronic devices can directly communicate. The plurality of high-speed transmission interfaces may include two Ethernet interfaces, i.e., ethernet interfaces. In the embodiment of the invention, the connection of different types of high-speed external devices can be realized through the arrangement of the USBOTG interface and the Ethernet interface. It should be noted that the number of usb otg interfaces and Ethernet interfaces is only exemplary, and the number may be adaptively modified according to actual requirements.

The processor is a dual-core processor. In particular, the processor provides a solution with high scalability and high power consumption efficiency for a dual-core ARMCortex-A9 processor, which utilizes dynamic length, eight-level superscalar architecture, multiple event pipeline, and Speculative out-of-order execution (Specification), capable of executing up to four instructions per cycle in devices with frequencies exceeding 1GHz, while also reducing the cost and improving efficiency of currently mainstream eight-level processors.

When the management chip is an intel aria vsocfpga chip, the HPS module may further include an on-chip memory, where the on-chip memory may be a 64KB on-chip RAM or a 64KB on-chip ROM. The first processing module may also include a NAND flash controller that supports an 8-bit ONFI1.0NAND flash device. The first processing module may also include a plurality of timers, the types of the plurality of timers including a dedicated interval for each processor, a global timer for the processor subsystem for the monitor timer, a general purpose timer, and a monitor timer. The intel aria vsocfpga chip also employs a precision-adjustable Digital Signal Processing (DSP) module. In the Intel ArriaVSoCFPGA chip, the HPS module is combined with the 28-nanometer low-power-consumption FPGA architecture of Intel, so that the performance and the ecosystem of the application-level ARM processor are realized, and meanwhile, the FPGA has the flexibility and the rich Digital Signal Processing (DSP) function of the FPGA.

In a second aspect, an embodiment of the present invention provides a server including the baseboard management controller of any one of the first aspects above. The server comprises a substrate management controller, wherein the substrate management controller comprises a management chip, the management chip comprises a first processing module and a second processing module which are mutually connected, and the first processing module comprises a low-speed transmission interface, a high-speed transmission interface and a processor; the processor is in communication connection with the high-speed transmission interface, and is used for receiving and processing information transmitted by the high-speed transmission interface, the second processing module is in communication connection with the low-speed transmission interface, and the second processing module is used for receiving and processing information transmitted by the low-speed transmission interface. The method steps executed by the second processing module are as follows: receiving information transmitted by a low-speed transmission interface; and processing the received information transmitted by the low-speed transmission interface. The method steps executed by the processor are as follows: receiving information transmitted by a high-speed transmission interface; and processing the received information transmitted by the high-speed transmission interface.

The server comprises a main board, a baseboard management controller is integrated on the main board, the server further comprises a memory, the baseboard management controller is in communication connection with the memory through the memory controller, the second processing module is used for storing information transmitted by the received low-speed transmission interface into the memory, and the processor is used for reading information stored in the memory by the second processing module from the memory.

The management chip is a SoCFPGA chip, the first processing module is an HPS module, and the second processing module is an FPGA module.

The server also includes a temperature sensor that can be used to monitor the current temperature of the motherboard in the server, or the current temperature of the CPU on the motherboard. The server further includes a fan, and the baseboard management controller is electrically connected to the fan, and the processor can control the operation of the fan according to the current temperature information read from the memory.

In other embodiments, the server further includes a voltage sensor, and the plurality of low-speed transmission interfaces may further include a second low-speed transmission interface, where the second low-speed transmission interface may be an I2C interface, and the second low-speed transmission interface may be used to electrically connect to the voltage sensor, where the voltage sensor may be used to monitor voltages of a core power supply, an IO power supply, a memory power supply, and a peripheral interface power supply of the CPU on the motherboard in real time. At this time, the second low-speed transmission interface is used for receiving the current voltage information output by the voltage sensor and transmitting the current voltage information to the second processing module, the second processing module is used for storing the received current voltage information into the memory, and the processor is used for reading the current voltage information from the memory.

The memory controller is in communication connection with the memory through a memory bus, and the memory is a double-rate synchronous dynamic random access memory.

The processor is a dual-core processor.

The server provided in the embodiment of the present invention includes each structure of the baseboard management controller in any one of the above embodiments, and in order to avoid repetition, a description thereof is omitted.

It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

It will be understood that when an element is referred to as being "fixed to" another element, it can be directly on the other element or intervening elements may also be present. When a component is considered to be "connected" to another component, it can be directly connected to the other component or intervening components may also be present. When an element is referred to as being "disposed on" another element, it can be directly on the other element or intervening elements may also be present. The terms "vertical," "horizontal," "left," "right," and the like are used herein for illustrative purposes only.

In this specification, each embodiment is described in a related manner, and identical and similar parts of each embodiment are all referred to each other, and each embodiment mainly describes differences from other embodiments. In particular, for system embodiments, since they are substantially similar to method embodiments, the description is relatively simple, as relevant to see a section of the description of method embodiments.

The foregoing description is only of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.

The baseboard management controller and the server provided by the invention are described in detail, and specific examples are applied to illustrate the principle and the implementation of the invention, and the description of the above examples is only used for helping to understand the structure and the core idea of the invention; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in accordance with the ideas of the present invention, the present description should not be construed as limiting the present invention in view of the above.

Claims

1. The substrate management controller is characterized by comprising a management chip, wherein the management chip comprises a first processing module and a second processing module which are mutually connected, and the first processing module comprises a low-speed transmission interface, a high-speed transmission interface and a processor;

2. The baseboard management controller of claim 1, wherein the first processing module further comprises a memory controller communicatively coupled to the processor and the second processing module, respectively, the memory controller being configured to communicatively couple to a memory, the second processing module being configured to store information received from the low speed transmission interface to the memory, the processor being configured to read information stored in the memory by the second processing module from the memory.

3. The baseboard management controller of claim 1 or 2, wherein the management chip is a SoC FPGA chip, the first processing module is an HPS module, and the second processing module is an FPGA module.

4. The baseboard management controller of claim 2, wherein the low speed transmission interface comprises a first low speed transmission interface for connecting to a temperature sensor, the first low speed transmission interface for receiving current temperature information output by the temperature sensor and transmitting the current temperature information to the second processing module for storing the received current temperature information to the memory, the processor for reading the current temperature information from the memory.

5. The baseboard management controller of claim 2, wherein the memory controller is communicatively coupled to the memory via a memory bus, the memory being a double rate synchronous dynamic random access memory.

6. The baseboard management controller of claim 1 or 2, wherein the low-speed transmission interface comprises at least one of an I2C interface, a UART interface, a GPIO interface, and an SPI interface.

7. The baseboard management controller of claim 1 or 2, wherein the high-speed transmission interface comprises at least one of a USB OTG interface, an Ethernet interface.

8. The baseboard management controller of claim 1 or 2, wherein the processor is a dual-core processor.

9. A server comprising the baseboard management controller of any one of claims 1 to 8.

10. The server of claim 9, wherein the server includes a motherboard, the baseboard management controller is integrated on the motherboard, the server further includes a memory, the baseboard management controller is communicatively connected to the memory through the memory controller, the second processing module is configured to store the received information transmitted by the low-speed transmission interface to the memory, and the processor is configured to read the information stored in the memory by the second processing module from the memory.