CN116154058B - Preparation method of combined chip and combined chip - Google Patents
Preparation method of combined chip and combined chip Download PDFInfo
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- CN116154058B CN116154058B CN202310418874.8A CN202310418874A CN116154058B CN 116154058 B CN116154058 B CN 116154058B CN 202310418874 A CN202310418874 A CN 202310418874A CN 116154058 B CN116154058 B CN 116154058B
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- 238000002360 preparation method Methods 0.000 title claims abstract description 16
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- 238000005530 etching Methods 0.000 claims description 40
- 229910018072 Al 2 O 3 Inorganic materials 0.000 claims description 27
- 238000000034 method Methods 0.000 claims description 23
- 238000004519 manufacturing process Methods 0.000 claims description 15
- 238000001259 photo etching Methods 0.000 claims description 12
- 238000005498 polishing Methods 0.000 claims description 11
- 238000001704 evaporation Methods 0.000 claims description 10
- 238000007747 plating Methods 0.000 claims description 10
- 238000005520 cutting process Methods 0.000 claims description 8
- 238000000206 photolithography Methods 0.000 claims description 7
- 239000011800 void material Substances 0.000 claims description 7
- 235000012431 wafers Nutrition 0.000 abstract description 182
- 238000012545 processing Methods 0.000 abstract description 15
- 238000000407 epitaxy Methods 0.000 description 29
- 239000007771 core particle Substances 0.000 description 21
- 238000010586 diagram Methods 0.000 description 18
- 238000003860 storage Methods 0.000 description 8
- 238000004590 computer program Methods 0.000 description 7
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
- H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The embodiment of the application provides a preparation method of a combined chip and the combined chip, and belongs to the field of LED chips. The preparation method comprises the following steps: processing a first epitaxial wafer in the epitaxial wafers to be combined to reserve a first vacancy on a first epitaxial substrate of the first epitaxial wafer for bonding a second epitaxial wafer; after bonding the second epitaxial wafer, processing the second epitaxial wafer so as to ensure that a second vacancy is reserved on a second epitaxial substrate of the second epitaxial wafer to bond a third epitaxial wafer until the epitaxial top layers of the last epitaxial wafer are processed to expose the first epitaxial top layer of the first epitaxial wafer, the second epitaxial top layer of the second epitaxial wafer and the third epitaxial top layer of the third epitaxial wafer after all the epitaxial wafers to be combined are bonded; thus, the chips to be combined are bonded on one epitaxial substrate and are manufactured as a whole in chip level, and the size of the chips is larger than that of an independent chip after being bonded into a whole no matter how small the size of the chips is, so that the chips are easier to later package and pick up the die.
Description
Technical Field
The application relates to the technical field of LED chips, in particular to a preparation method of a combined chip and the combined chip.
Background
In recent years, on the increasingly steaming days of the LED chip industry, along with the demands of application ends, the LED chip is increasingly developed to be smaller in size, but the biggest problem of the smaller-size chip is in subsequent transfer packaging, and the combined chip is difficult to package and difficult to pick up due to smaller size of the core particles.
Disclosure of Invention
The embodiment of the application aims to provide a preparation method of a combined chip and the combined chip, which are used for solving the technical problems in the prior art.
In order to achieve the above objective, an embodiment of the present application provides a method for manufacturing a combined chip, including processing a first epitaxial wafer in an epitaxial wafer to be combined, so that a first vacancy is reserved on a first epitaxial substrate of the first epitaxial wafer to bond a second epitaxial wafer; after the second epitaxial wafer is bonded, processing the second epitaxial wafer so as to ensure that a second vacancy is reserved on a second epitaxial substrate of the second epitaxial wafer to bond a third epitaxial wafer, and processing an epitaxial top layer of a last epitaxial wafer until the wafers to be combined are bonded completely so as to expose a first epitaxial top layer of the first epitaxial wafer, a second epitaxial top layer of the second epitaxial wafer and a third epitaxial top layer of the third epitaxial wafer; the first epitaxial wafer, the second epitaxial wafer and the third epitaxial wafer comprise an epitaxial substrate, an N layer, an MQW layer and a P layer which are sequentially stacked.
Optionally, the processing the first epitaxial wafer in the epitaxial wafers to be combined to reserve a first vacancy on a first epitaxial substrate of the first epitaxial wafer to bond the second epitaxial wafer includes: performing photoetching and etching treatment on the first epitaxial wafer to obtain the first vacancy; plating Al on the P layer and the first empty position of the etched first epitaxial wafer 2 O 3 Layer and to the Al 2 O 3 Subjecting the layer to polishing treatment to make the Al 2 O 3 The thickness of the layer meets the bonding requirement, and then the second epitaxial wafer is bonded.
Optionally, plating Al on the P layer of the etched first epitaxial wafer and the first empty site 2 O 3 The thickness of the layer is thicker than that of the first epitaxial wafer, the Al 2 O 3 The layer has a thickness of not more than 500 a after the polishing process.
Optionally, before bonding the second epitaxial wafer and the third epitaxial wafer, the preparation method further includes:
plating Al on the N layer/P layer of the second epitaxial wafer and the third epitaxial wafer 2 O 3 The layer of the material is formed from a layer,for plating Al on vacancies to be bonded thereto 2 O 3 The layers are bonded.
Optionally, after the processing is performed on the epitaxial top layer of the last epitaxial wafer to expose the first epitaxial top layer of the first epitaxial wafer, the second epitaxial top layer of the second epitaxial wafer, and the third epitaxial top layer of the third epitaxial wafer, the preparation method further includes: respectively manufacturing the first epitaxial wafer, the second epitaxial wafer and the Mesa of the third epitaxial wafer; and manufacturing P-Pad and N-Pad on the P layer and the N layer of the first epitaxial wafer, the second epitaxial wafer and the third epitaxial wafer.
Optionally, the preparation method further comprises: evaporating DBR layers on the upper surfaces of the first epitaxial wafer, the second epitaxial wafer and the third epitaxial wafer, and etching corresponding P-Pad and N-Pad conductive holes in the DBR layers; and evaporating contact electrodes on the surface of the DBR layer, wherein the contact electrodes respectively cover the P-Pad and N-Pad conducting holes in the DBR layer so as to conduct the first epitaxial wafer, the second epitaxial wafer and the third epitaxial wafer.
Optionally, the DBR layer has 99% reflection for light having a wavelength in a range of 400nm to 700 nm.
Optionally, after evaporating the contact electrode on the surface of the DBR layer, the preparation method further comprises: and etching independent cutting channels among the first epitaxial wafer, the second epitaxial wafer and the third epitaxial wafer.
Alternatively, the combined chip is singulated as a group using a laser to cut large scribe line locations.
Optionally, the first epitaxial wafer is a blue epitaxial wafer, the second epitaxial wafer is a green epitaxial wafer, and the third epitaxial wafer is a red epitaxial wafer.
In another aspect, the present application provides a combined chip comprising: an epitaxial substrate; the chips to be combined are bonded on the epitaxial substrate at step intervals.
Optionally, the plurality of chips to be combined include a blue light chip, a green light chip, and a red light chip.
Optionally, the blue light chip is bonded on an epitaxial substrate, and the green light chip is bonded in a step-like manner on Al of a first vacancy formed by etching the substrate of the blue light chip 2 O 3 The red light chip is bonded on the Al of the second vacancy formed by etching the substrate of the green light chip in a step-like manner 2 O 3 On the layer.
Through the technical scheme, the chip to be combined is bonded on the epitaxial substrate and is manufactured as a whole in a chip level, so that the size of the chip is larger than that of an independent chip after being bonded into a whole no matter how small the size of the chip is, and the chip is easier to pick up and fix the die in later packaging.
Additional features and advantages of embodiments of the application will be set forth in the detailed description which follows.
Drawings
The accompanying drawings are included to provide a further understanding of embodiments of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain, without limitation, the embodiments of the application. In the drawings:
fig. 1 is a schematic structural diagram of an epitaxial wafer provided in the prior art;
FIG. 2 is a flowchart of a method for manufacturing a combined chip according to an embodiment of the present application;
FIG. 3 is a schematic diagram of a second epitaxial wafer pretreatment structure according to an embodiment of the present application;
FIG. 4 is a first void-filled polished Al provided in an embodiment of the application 2 O 3 A schematic diagram;
FIG. 5 is a schematic structural diagram of a green epitaxial wafer bonded in a first void according to an embodiment of the present application;
FIG. 6 shows an embodiment of the application for a green epitaxial wafer with bonded and polished Al 2 O 3 A layer schematic;
fig. 7 is a schematic structural diagram of a bonded blue light epitaxial wafer, green light epitaxial wafer and red light epitaxial wafer according to an embodiment of the present application;
FIG. 8 is a schematic diagram of a structure after etching the outermost red light by photolithography and etching according to an embodiment of the present application;
FIG. 9 is a schematic diagram of a structure of a Mesa, an N-Pad and a P-Pad fabricated on a combined chip according to an embodiment of the present application;
FIG. 10 is a schematic diagram of RGB and contact electrode structures fabricated on a combined chip according to an embodiment of the present application;
fig. 11 is a schematic diagram of a combined chip structure according to an embodiment of the present application.
Detailed Description
The following describes the detailed implementation of the embodiments of the present application with reference to the drawings. It should be understood that the detailed description and specific examples, while indicating and illustrating the application, are not intended to limit the application.
Referring to fig. 1, a schematic structural diagram of an epitaxial wafer provided in the prior art includes: epitaxial substrate, P layer, MQW layer and N layer.
Based on the epitaxial wafer provided by the prior art, a combined chip is prepared, and referring to fig. 2, a flowchart of implementation of a preparation method of the combined chip provided by an embodiment of the application specifically includes the following steps.
Step 200: and processing the first epitaxial wafer in the epitaxial wafer to be combined so as to reserve a first vacancy on the first epitaxial substrate of the first epitaxial wafer to bond the second epitaxial wafer.
Specifically, in performing step 200, the following steps may be performed.
And S1, respectively carrying out photoetching and etching treatment on the first epitaxial wafer to obtain the first vacancy.
S2, plating Al on the P layer and the first vacancy of the etched first epitaxial wafer 2 O 3 Layer and to Al 2 O 3 Subjecting the layer to polishing treatment to make the Al 2 O 3 The thickness of the layer meets the bonding requirement, and then the second epitaxial wafer is bonded.
Wherein the P layer and the P layer of the first epitaxial wafer after etchingAl plated on the first empty site 2 O 3 The thickness of the layer is thicker than that of the first epitaxial wafer, the Al 2 O 3 The layer has a thickness of not more than 500 a after the polishing process.
In some embodiments, before bonding a second epitaxial wafer, referring to fig. 3, a schematic diagram of a pretreatment structure of a second epitaxial wafer according to an embodiment of the present application is shown, first, a P layer of the second epitaxial wafer is temporarily bonded to a Si wafer by using a temporarily bonded high-temperature wax or a thermal stripping film, then an N layer of the second epitaxial wafer is exposed by polishing, the second epitaxial wafer is transferred to the Si wafer, and then a layer of Al is grown on the surface of the N layer of the second epitaxial wafer 2 O 3 And polished in preparation for subsequent activated bonding.
In some embodiments, referring to fig. 4, a first epitaxial wafer (e.g., a blue light epitaxial wafer) is subjected to photolithography and etching to reserve vacancies of the sizes of a subsequent second epitaxial wafer and a third epitaxial wafer on a blue light substrate, the first vacancies are required to be etched to the substrate of the blue light epitaxial wafer, the positions of the single blue light epitaxial wafer are not etched (i.e., the structure of the blue light epitaxial wafer is complete, namely, the blue light substrate, the blue light N layer, the blue light MQW layer and the blue light P layer), and Al is plated on the P layer of the etched blue light epitaxial wafer 2 O 3 The thickness is required to be thicker than that of the blue light epitaxial wafer, and then Al is grown 2 O 3 The blue light epitaxial wafer of the layer is polished, and only Al of about 500A is required to be reserved on the blue light epitaxy 2 O 3 A layer in which the first void is filled with polished Al 2 O 3 Al plated on the P layer in this example 2 O 3 Is 2um thicker than the blue light epitaxial wafer, in practical application, the P layer is plated with Al 2 O 3 The thickness of (2) may be set according to actual needs, and is not limited herein.
Step 201: and after bonding the second epitaxial wafer, processing the second epitaxial wafer so as to ensure that a second vacancy is reserved on a second epitaxial substrate of the second epitaxial wafer to bond a third epitaxial wafer, and processing an epitaxial top layer of the last epitaxial wafer until the bonding of all the epitaxial wafers to be combined is completed so as to expose a first epitaxial top layer of the first epitaxial wafer, a second epitaxial top layer of the second epitaxial wafer and a third epitaxial top layer of the third epitaxial wafer.
The first epitaxial wafer, the second epitaxial wafer and the third epitaxial wafer comprise an epitaxial substrate, an N layer, an MQW layer and a P layer which are sequentially stacked.
Specifically, before bonding the second epitaxial wafer and the third epitaxial wafer in step 201, the following steps are further performed. Plating Al on the N layer/P layer of the second epitaxial wafer and the third epitaxial wafer 2 O 3 A layer for plating Al on the vacancies to be bonded thereto 2 O 3 The layers are bonded.
In some embodiments, the polished Al is filled 2 O 3 Bonding the pretreated second epitaxial wafer (such as green epitaxial wafer) to the first vacancy of the wafer to plate Al 2 O 3 One surface of the layers is bonded together, then temporary bonding is released, at the moment, the green epitaxial P layer is arranged on the outermost surface, and is sequentially provided with a green MQW layer, a green N layer and green polished Al 2 O 3 Etching green light epitaxy by photoetching and etching to expose vacancies of the third epitaxial wafer size to polished Al 2 O 3 The layer and the blue light epitaxial wafer P layer are shown in FIG. 5, and then Al grows on the outermost surface of the bonded green light epitaxial wafer (i.e. the upper surface of the green light P layer) 2 O 3 Layer and polish, see FIG. 6, al 2 O 3 The thickness is grown thicker than the green epitaxy, the green epitaxy surface remains only 500 a after polishing, and the third epitaxy is subsequently prepared for active bonding, in this example, al 2 O 3 The growth thickness is 2um thicker than green light epitaxy, in the practical application scene, the P layer is plated with Al 2 O 3 The thickness of (2) may be set according to actual needs, and is not limited herein.
In some embodiments, when bonding a third epitaxial wafer (e.g., a red epitaxial wafer) on the second void, the surface of the red epitaxial wafer is roughened to achieve the purpose of brightening and brightening, and then a layer of Al is grown 2 O 3 Layer and green withGrowth of Al on the outermost surface of the photo-epitaxial wafer 2 O 3 And bonding the layers, and removing the GaAs substrate of the infrared epitaxial wafer. At this time, the red light epitaxy, the green light epitaxy and the blue light epitaxy are integrated on the blue light epitaxy substrate, as shown in fig. 7, and finally the outermost surface red light epitaxy is etched by using photolithography and etching methods, so that the red light epitaxy N layer, the green light epitaxy P layer and the blue light epitaxy P layer are at the outermost surface, as shown in fig. 8.
Further, after the processing is performed on the epitaxial top layer of the last epitaxial wafer to expose the first epitaxial top layer of the first epitaxial wafer, the second epitaxial top layer of the second epitaxial wafer, and the third epitaxial top layer of the third epitaxial wafer, the preparation method further includes: respectively manufacturing the first epitaxial wafer, the second epitaxial wafer and the Mesa of the third epitaxial wafer; and manufacturing P-Pad and N-Pad on the P layer and the N layer of the first epitaxial wafer, the second epitaxial wafer and the third epitaxial wafer.
In some embodiments, the Mesa of the combined chip (RGB three-core) is fabricated using photolithography and etching, and then the N-Pad and P-Pad (both independent pads, without series contact) of the three-core are fabricated using photolithography and evaporation, as shown in fig. 9.
In some embodiments, the method of making further comprises: and evaporating DBR layers on the upper surfaces of the first epitaxial wafer, the second epitaxial wafer and the third epitaxial wafer, etching corresponding P-Pad and N-Pad conducting holes in the DBR layers, and evaporating contact electrodes on the surfaces of the DBR layers, wherein the contact electrodes cover the P-Pad and N-Pad conducting holes in the DBR layers respectively so as to conduct the first epitaxial wafer, the second epitaxial wafer and the third epitaxial wafer.
The DBR layer has 99% reflection on light with the wavelength range of 400-700 nm.
In some embodiments, after vapor plating the contact electrode on the DBR layer surface, the method further comprises: and etching independent cutting channels among the first epitaxial wafer, the second epitaxial wafer and the third epitaxial wafer.
In some embodiments, referring to fig. 10, the independent scribe lines of the RGB three-core particles are fabricated by using photolithography and etching, so that the three-core particles are kept relatively independent in epitaxy, and a communication phenomenon does not occur when a contact electrode is subsequently plated, and the three-core particles of RGB are used as a group of core particles to etch a large scribe line, then a DBR is grown, and etched, so that the P-Pad and the N-Pad of the three-core particles of RGB are exposed, and only the large scribe line is etched, and the independent scribe lines are not etched (etching the DBR layer on the large scribe line can expose a blue substrate to facilitate subsequent dicing, and the independent scribe lines can be performed on the core particles in groups, and can also prevent abnormal influences such as overflow of Sn paste of water vapor die bonding, etc.), and then a die bonding electrode is fabricated for subsequent flip-chip packaging, wherein the contact electrode covers the P-Pad and the N-Pad conductive holes in the DBR layer, respectively, so as to conduct the three-core particles.
Therefore, the space between the RGB chips is only the size of the independent cutting channel, which is far smaller than the space between the single chips, so that more RGB modules can be arranged on the same-size die bonding packaging board, and the resolution is optimized.
In some embodiments, to facilitate the pick-and-transfer of the combined chips, the combined chips are singulated as a group using a laser to cut large scribe line locations.
Optionally, the first epitaxial wafer is a blue epitaxial wafer, the second epitaxial wafer is a green epitaxial wafer, and the third epitaxial wafer is a red epitaxial wafer.
It should be noted that the order of the blue light epitaxial wafer, the green light epitaxial wafer and the red light epitaxial wafer may be adjusted according to the actual application scenario, which is not limited herein.
In some embodiments, the following steps may be employed to fabricate an RGB (red, green, and blue) combination chip.
Step 1: preparing a red light epitaxial wafer, a green light epitaxial wafer and a blue light epitaxial wafer.
Step 2: temporarily bonding the P layer of the green epitaxial wafer with the Si wafer by using temporarily bonded high-temperature wax or a heat stripping film, exposing the N layer of the green epitaxial wafer by using a grinding and polishing mode, transferring the green epitaxial wafer onto the Si wafer, and then removing the green epitaxial waferA layer of Al grows on the surface of the P layer of the extension piece 2 O 3 And polished in preparation for subsequent activated bonding.
Step 3: the blue light epitaxial wafer is subjected to photoetching and etching, so that the blue light epitaxial wafer reserves the vacancy with the size of single core particle of the subsequent green light and the red light, only the vacancy is required to be etched to the substrate of the blue light chip, the single blue light chip is epitaxially not etched, and then the P layer of the etched blue light epitaxial wafer is plated with Al 2 O 3 The thickness is 2um thicker than the blue light epitaxy thickness.
Step 4: then for growing Al 2 O 3 The blue light epitaxial wafer of the layer is polished until only Al with the thickness of about 500A is reserved on the blue light epitaxy 2 O 3 A layer, wherein the vacancies of the green single core particle position are filled with polished Al 2 O 3 。
Step 5: the green light epitaxial wafer and the blue light epitaxial wafer are subjected to activation bonding to be plated with Al 2 O 3 The temporary bonding is then released, the P layer of the green light epitaxy is arranged on the outermost layer, and the green light epitaxy is etched by photoetching and etching to expose the vacancy with the size of the red light single particle core to Al 2 O 3 And a blue light epitaxial wafer P layer.
Step 6: growing Al on the outermost surface of the bonded epitaxial wafer 2 O 3 /SiO 2 Layer and polish Al 2 O 3 /SiO 2 The thickness of the epitaxial wafer is 2um thicker than that of the green light epitaxy, and the surface of the green light epitaxy after polishing is only kept to be 500 a, so that preparation is made for subsequent active bonding with a red light epitaxy wafer.
Step 7: coarsening the surface of the infrared epitaxial wafer, and then growing Al 2 O 3 /SiO 2 Polishing, and activating the surface Al of the red epitaxial wafer and the bonded blue epitaxial wafer and green epitaxial wafer 2 O 3 /SiO 2 And bonding the layers, and removing the red light epitaxial wafer GaAs substrate, wherein the red light, the green light and the blue light are epitaxially collected on the blue light epitaxial substrate.
Step 8: etching the surface-most red epitaxy by using photoetching and etching modes to expose blue epitaxy and green epitaxy at the positions of the subsequent single core particles, wherein the red epitaxy N layer, the green epitaxy P layer and the blue epitaxy P layer corresponding to the positions of the core particles are arranged on the surface-most.
Step 9: the method comprises the steps of manufacturing the Mesa of three RGB core particles by using a photoetching and etching mode, manufacturing the N-Pad and the P-Pad (which are independent pads and do not need to be in series contact) of the three core particles by using a photoetching and evaporation mode, and then continuously manufacturing the independent cutting paths of the three RGB core particles by using a photoetching and etching mode, so that the three core particles are relatively independent in extension, a communication phenomenon can not occur during subsequent plating of a contact electrode, and the three RGB core particles are used as a group of core particles to etch a large cutting path.
Step 10: the three RGB cores grow a DBR, and the DBR is required to have 99% reflection on 400-700 nm wavelength light.
Step 11: etching the DBR to expose pad of three RGB core particles, etching only the large dicing channel, not etching the independent dicing channel (etching the DBR layer on the large dicing channel to expose the blue light substrate for facilitating subsequent dicing, not etching the independent dicing channel to group the core particles, and also preventing abnormal influence of overflow of Sn paste for water vapor die bonding on the chip), then evaporating the contact electrode, and manufacturing the die bonding electrode for subsequent flip chip packaging.
Step 12: and cutting the large cutting path position by using laser, and dividing the RGB three core particles as a group, so that the RGB combined flip chip is manufactured.
On the other hand, the embodiment of the present application further provides a combined chip, the schematic structural diagram of which is shown in fig. 11, including: an epitaxial substrate; the chips to be combined are bonded on the epitaxial substrate at step intervals.
Optionally, the plurality of chips to be combined include: blue light chip, green light chip and red light chip.
It should be noted that the plurality of chips to be combined may be other chips than the blue light chip, the green light chip, and the red light chip, which is not limited herein.
In some embodiments, the blue light chip is bonded to an epitaxial substrate and the green light chip passes through greenPolished Al 2 O 3 Step-type bonding Al at first vacancy formed by etching substrate of blue light chip 2 O 3 On the layer, the red light chip passes through the Al after red light polishing 2 O 3 Step-bonding Al in a second vacancy formed by etching the substrate of the green chip 2 O 3 On the layer, see fig. 11.
In this way, three kinds of epitaxy of RGB are assembled on one epitaxial substrate in an active bonding mode, so that three kinds of photochromic chips of RGB can be manufactured at one time later, and even the chip with the size of Mirco is larger than an independent chip due to the fact that the chip with the size of three Mircos is used as a group, and the chip is easier to pick up and transfer.
It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
In one typical configuration, a computing device includes one or more processors (CPUs), input/output interfaces, network interfaces, and memory.
The memory may include volatile memory in a computer-readable medium, random Access Memory (RAM) and/or nonvolatile memory, etc., such as Read Only Memory (ROM) or flash RAM. Memory is an example of a computer-readable medium.
Computer readable media, including both non-transitory and non-transitory, removable and non-removable media, may implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of storage media for a computer include, but are not limited to, phase change memory (PRAM), static Random Access Memory (SRAM), dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), read Only Memory (ROM), electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices, or any other non-transmission medium, which can be used to store information that can be accessed by a computing device. Computer-readable media, as defined herein, does not include transitory computer-readable media (transmission media), such as modulated data signals and carrier waves.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article or apparatus that comprises an element.
The foregoing is merely exemplary of the present application and is not intended to limit the present application. Various modifications and variations of the present application will be apparent to those skilled in the art. Any modification, equivalent replacement, improvement, etc. which come within the spirit and principles of the application are to be included in the scope of the claims of the present application.
Claims (11)
1. The preparation method of the combined chip is characterized by comprising the following steps of:
a first epitaxial wafer is subjected to photoetching and etching, so that a first vacancy with the size of a subsequent second epitaxial wafer and a third epitaxial wafer is reserved on a first epitaxial substrate of the first epitaxial wafer, wherein the structure of the first epitaxial wafer comprises a first epitaxial substrate, an N layer, an MQW layer and a P layer which are sequentially laminated;
growing Al on the P layer of the etched first epitaxial wafer and the first vacancy 2 O 3 Then for growing Al 2 O 3 Polishing the first epitaxial wafer of the layer to fill the first empty space with polished Al 2 O 3 ；
At full of polished Al 2 O 3 Bonding a second epitaxial wafer to the first void of (a) so that Al grows 2 O 3 Wherein the structure of the second epitaxial wafer comprises polished Al laminated in sequence 2 O 3 Layer, N layer, MQW layer and P layer;
exposing a second vacancy with the size of a third epitaxial wafer to polished Al by photoetching and etching the second epitaxial wafer 2 O 3 The layer exposes the P layer of the first epitaxial wafer;
growing Al on the etched P layer of the second epitaxial wafer and the second empty site 2 O 3 Then for growing Al 2 O 3 Polishing the second epitaxial wafer of the layer to fill the polished Al with the second empty space 2 O 3 ；
At full of polished Al 2 O 3 Bonding a third epitaxial wafer to the second void of the substrate to grow Al 2 O 3 Wherein the structure of the third epitaxial wafer comprises polished Al laminated in sequence 2 O 3 Layer, P layer, MQW layer, and N layer; and
and etching the third epitaxial wafer by utilizing photoetching and etching modes, so that the N layer of the third epitaxial wafer, the P layer of the second epitaxial wafer and the P layer of the first epitaxial wafer are arranged on the outermost surface.
2. The method according to claim 1, wherein Al is grown on 2 O 3 After polishing the first epitaxial wafer of the layer, al on the P layer of the first epitaxial wafer 2 O 3 The layer has a thickness of not more than 500 a.
3. The method according to claim 1, wherein after etching the third epitaxial wafer by photolithography and etching such that the N layer of the third epitaxial wafer, the P layer of the second epitaxial wafer, and the P layer of the first epitaxial wafer are on the outermost surface, the method further comprises:
respectively manufacturing the first epitaxial wafer, the second epitaxial wafer and the Mesa of the third epitaxial wafer; and
and manufacturing P-Pad and N-Pad on the P layer and the N layer of the first epitaxial wafer, the second epitaxial wafer and the third epitaxial wafer.
4. A method of preparing according to claim 3, further comprising:
evaporating DBR layers on the upper surfaces of the first epitaxial wafer, the second epitaxial wafer and the third epitaxial wafer, and etching corresponding P-Pad and N-Pad conductive holes in the DBR layers;
and evaporating contact electrodes on the surface of the DBR layer, wherein the contact electrodes respectively cover the P-Pad and N-Pad conducting holes in the DBR layer so as to conduct the first epitaxial wafer, the second epitaxial wafer and the third epitaxial wafer.
5. The method of claim 4, wherein the DBR layer has a 99% reflection of light having a wavelength in the range of 400nm to 700 nm.
6. The method of manufacturing according to claim 4, further comprising, after vapor plating the contact electrode on the DBR layer surface:
and etching independent cutting channels among the first epitaxial wafer, the second epitaxial wafer and the third epitaxial wafer.
7. The method of claim 6, wherein the combined chips are singulated as a group using a laser to cut large scribe line locations.
8. The method of any one of claims 1-7, wherein the first epitaxial wafer is a blue epitaxial wafer, the second epitaxial wafer is a green epitaxial wafer, and the third epitaxial wafer is a red epitaxial wafer.
9. A combined chip prepared by the method for preparing a combined chip according to any one of claims 1 to 8, characterized in that the combined chip comprises:
a first epitaxial substrate;
the chips to be combined are formed on the first epitaxial substrate at step intervals.
10. The combination chip of claim 9, wherein the plurality of chips to be combined comprises: blue light chip, green light chip and red light chip.
11. The combination chip of claim 10, wherein the blue light chip is formed on the first epitaxial substrate, and the green light chip is bonded stepwise to Al of the first void formed by etching the blue light chip 2 O 3 The red light chip is bonded with Al of a second vacancy formed by etching the green light chip in a step-like manner on the layer 2 O 3 On the layer.
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