KR0171377B1 - Fabrication method of ultra thin device - Google Patents
Fabrication method of ultra thin device Download PDFInfo
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- KR0171377B1 KR0171377B1 KR1019950052669A KR19950052669A KR0171377B1 KR 0171377 B1 KR0171377 B1 KR 0171377B1 KR 1019950052669 A KR1019950052669 A KR 1019950052669A KR 19950052669 A KR19950052669 A KR 19950052669A KR 0171377 B1 KR0171377 B1 KR 0171377B1
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- layer
- gallium arsenide
- buffer layer
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- 238000000034 method Methods 0.000 title claims abstract description 14
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 33
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 239000010408 film Substances 0.000 claims abstract description 13
- 238000005530 etching Methods 0.000 claims abstract description 10
- 239000010409 thin film Substances 0.000 claims abstract description 10
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 7
- 239000010703 silicon Substances 0.000 claims abstract description 7
- MDPILPRLPQYEEN-UHFFFAOYSA-N aluminium arsenide Chemical compound [As]#[Al] MDPILPRLPQYEEN-UHFFFAOYSA-N 0.000 claims abstract description 6
- -1 gallium arsenide compound Chemical class 0.000 claims abstract description 6
- FTWRSWRBSVXQPI-UHFFFAOYSA-N alumanylidynearsane;gallanylidynearsane Chemical compound [As]#[Al].[As]#[Ga] FTWRSWRBSVXQPI-UHFFFAOYSA-N 0.000 claims abstract description 4
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 4
- 239000004065 semiconductor Substances 0.000 claims description 8
- KRKNYBCHXYNGOX-UHFFFAOYSA-N citric acid Chemical compound OC(=O)CC(O)(C(O)=O)CC(O)=O KRKNYBCHXYNGOX-UHFFFAOYSA-N 0.000 claims description 6
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 2
- 229910052737 gold Inorganic materials 0.000 claims description 2
- 239000010931 gold Substances 0.000 claims description 2
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 claims description 2
- 230000017525 heat dissipation Effects 0.000 abstract description 7
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 4
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical compound [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 238000002109 crystal growth method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02455—Group 13/15 materials
- H01L21/02463—Arsenides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02494—Structure
- H01L21/02496—Layer structure
- H01L21/02505—Layer structure consisting of more than two layers
- H01L21/02507—Alternating layers, e.g. superlattice
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02538—Group 13/15 materials
- H01L21/02546—Arsenides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
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- Computer Hardware Design (AREA)
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Abstract
본 발명은 극 박막소자 제조 방법에 관한 것으로서, 반절연성의 갈륨 비소 화합물 반도체 기판상에 상기 갈륨 비소와 식각 선택비가 큰 알루미늄 비소로 이루어진 희생층, 갈륨 비소 또는 갈륨 비소와 알루미늄 갈륨 비소의 초격자 구조로 이루어진 완충층, 실리콘이 도핑된 갈륨 비소층으로 이루어진 채널층으로 순착적으로 결정 성장하는 공정과, 상기 채널층의 소정부분을 상기 완충층이 노출되도록 제거하여 소자를 분리하는 공정과, 상기 완충층과 채널층의 상부에 감광막을 도포한 후 노광 및 현상하여 상기 완충층을 노출시키는 공정과, 상기 완충층을 상기 희생층이 노출되도록 식각하는 공정과, 상기 감광막의 상부에 여분의 웨이퍼를 부착하고 상기 희생층을 제거하여 소자를 기판으로 부터 분리하는 공정과, 상기 완충층의 노출면에 패키지 할 때 열 방출을 효율적으로 할 수 있는 열방출층을 형성하는 공정과, 상기 열방출층의 표면에 열전도성이 좋은 열전도기판을 부착하고 상기 감광막을 제거하는 공정을 구비한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a polar thin film device, comprising: a superlattice structure of a sacrificial layer made of gallium arsenide and aluminum arsenide having a high etching selectivity on a semi-insulating gallium arsenide compound substrate, gallium arsenide, or gallium arsenide and aluminum gallium arsenide A process of crystally growing into a buffer layer consisting of a buffer layer made of silicon and a gallium arsenide layer doped with silicon, and removing a predetermined portion of the channel layer so that the buffer layer is exposed, and separating the device, the buffer layer and a channel Applying a photoresist film on top of the layer, exposing and developing the buffer layer to expose the buffer layer, etching the buffer layer to expose the sacrificial layer, attaching an extra wafer to the top of the photoresist film, and Removing the device from the substrate, and packaged on the exposed surface of the buffer layer. Forming a heat dissipation layer capable of efficiently dissipating heat at a time; and attaching a heat conductive substrate having good thermal conductivity to the surface of the heat dissipation layer and removing the photosensitive film.
따라서, 본 발명은 동시에 칩을 분리 할 수 있으며, 이렇게 분리된 칩은 두께가 수 마이크로 미터로 줄어들므로 열방출을 효율적으로 할 수 있어 전력소자의 성능을 향상시킬 수 있다.Therefore, the present invention can separate the chip at the same time, and the separated chip is reduced to a few micrometers thickness, so that the heat dissipation can be efficiently improved the performance of the power device.
Description
제1도는 본 발명에 따른 극 박막소자를 제조하기 위한 에피택셜층의 단면도.1 is a cross-sectional view of an epitaxial layer for manufacturing a polar thin film device according to the present invention.
제2도(a) 내지 (h)는 본 발명에 따른 극 박막소자의 제조 공정도.2 (a) to (h) is a manufacturing process diagram of the polar thin film device according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 반도체 기판 2 : 희생층1 semiconductor substrate 2 sacrificial layer
3 : 완충층 4 : 채널층3: buffer layer 4: channel layer
5 : 감광막 6 : 여분의 웨이퍼5: photosensitive film 6: extra wafer
7 : 열방출층 8 : 열전도기판7: heat dissipation layer 8: heat conducting substrate
본 발명은 극 박막소자의 제조방법에 관한 것으로서, 특히, 갈륨 비소 화합물 반도체로 제조한 전력 소자가 얇은 두께를 가져 열방출율을 효과적으로 제어하여 전력소자의 전력 효율을 높일 수 있는 극 박막소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a polar thin film device. In particular, a power device manufactured from a gallium arsenide compound semiconductor has a thin thickness and effectively controls a heat emission rate, thereby improving the power efficiency of the power thin film device. It is about.
일반적으로 갈륨 비소 화합물 반도체 전력 소자는 기판에 이온 주입을 하거나 에피택시장치에 의하여 에피택셜 성장한 활성층을 이용하여 제작하고 있다.In general, gallium arsenide compound semiconductor power devices are fabricated using ion-implanted substrates or epitaxially grown active layers.
이온 주입 방법에 의해 형성된 전력 소자 두께는 대체로 사용한 기판의 두께와 같으며, 에피택셜 방법에 의한 전력 소자의 두께는 기판보다 성장한 층들의 두께 만큼 두꺼운 형태를 가지게 된다.The thickness of the power device formed by the ion implantation method is generally the same as the thickness of the substrate used, and the thickness of the power device by the epitaxial method is thicker than the thickness of the grown layers.
이러한 갈륨 비소 소자는 두꺼운 기판과 자체의 특성 때문에 소자 동작시 발생하는 열을 효과적으로 방출하지 못한다.Such gallium arsenide devices do not effectively dissipate heat generated during device operation due to their thick substrates and their characteristics.
특히 갈륨 비소 반도체는 열 방출 특성이 실리콘 보다 매우 낮은 특성을 가지므로 갈륨 비소 반도체로 소자를 제작하면 열방출 문제가 대두 된다.In particular, the gallium arsenide semiconductor has a much lower heat release characteristics than silicon, so if a device is manufactured from a gallium arsenide semiconductor, heat dissipation problems arise.
그러므로, 종래에는 제작된 기판의 하부면을 100~300㎛ 정도로 얇게 연마하여 소자 동작시 발생되는 열을 효과적으로 방출시켜 소자를 안정적으로 동작시켰다.Therefore, in the related art, the lower surface of the fabricated substrate is polished to about 100 to 300 µm, thereby effectively releasing heat generated during device operation, thereby stably operating the device.
그러나, 갈륨 비소 반도체로 제조된 소자를 열방출을 위하여 연마하여 기판의 두께를 얇게 만들면 부서지기 쉬운 문제점이 있었다.However, when a device made of gallium arsenide semiconductor is polished for heat dissipation to make the thickness of the substrate thin, there is a problem of brittleness.
따라서, 본 발명의 목적은 연마하지 않고 갈륨 비소 화합물 전력 소자 구조를 에피택셜 방법으로 제작할 수 있는 극 박막소자의 제조방법을 제공함에 있다.Accordingly, it is an object of the present invention to provide a method for manufacturing a polar thin film device which can produce a gallium arsenide compound power device structure by an epitaxial method without polishing.
상기 목적을 달성하기 위한 본 발명에 따른 극 박막소자의 제조방법은 반절연성의 갈륨 비소 화합물 반도체 기판 상에 상기 갈륨 비소와 식각 선택비가 큰 알루미늄 비소로 이루어진 희생층, 갈륨 비소 또는 갈륨 비소와 알루미늄 갈륨 비소의 초격자 구조로 이루어진 완충층, 실리콘이 도핑된 갈륨 비소층으로 이루어진 채널층을 순차적으로 결정 성장하는 공정과, 상기 채널층의 소정 부분을 상기 완충층이 노출되도록 제거하여 소자를 분리하는 공정과, 상기 완충층과 채널층의 상부에 감광막을 도포한 후 노광 및 현상하여 상기 완충층을 노출시키는 공정과, 상기 완충층을 상기 희생층이 노출되도록 식각하는 공정과, 상기 감광막의 상부에 여분의 웨이퍼를 부착하고 상기 희생층을 제거하여 소자를 기판으로 부터 분리하는 공정과, 상기 완충층의 노출면에 패키지 할 때 열 방출을 효율적으로 할 수 있는 열방출층을 형성하는 공정과, 상기 열방출층의 표면에 열 전도성이 좋은 열전도기판을 부착하고 상기 감광막을 제거하는 공정을 구비한다.According to an aspect of the present invention, there is provided a method of fabricating an ultra-thin device according to the present invention, wherein a sacrificial layer made of gallium arsenide and aluminum arsenide having a high etching selectivity on a semi-insulating gallium arsenide compound semiconductor substrate, gallium arsenide, or gallium arsenide and aluminum gallium Sequential crystal growth of a buffer layer consisting of a arsenic superlattice structure and a gallium arsenide layer doped with silicon, and separating a device by removing a predetermined portion of the channel layer so that the buffer layer is exposed; Exposing and buffering the photosensitive film on top of the buffer layer and the channel layer, exposing and developing the buffer layer, etching the buffer layer to expose the sacrificial layer, and attaching an extra wafer to the top of the photosensitive film. Removing the sacrificial layer to separate the device from the substrate, and When the package resin receiving surface comprises a step of attaching a heat conductive substrate is good thermal conductivity to the surface of the step and the heat-releasing layer to form the heat dissipating layer which can effectively dissipate heat and remove the photosensitive film.
이하, 첨부한 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
제1도는 극 박막소자를 제조하기 위한 에픽택셜 층의 구조로서, 참조 번호 1은 에피택셜 성장을 위한 반절연성 갈륨 비소 기판이며, 참조 번호 2는 습식 에칭의 상기 갈륨 비소 기판(1)과 식각 선택비가 큰 알루미늄 비소가 50~500Å 정도의 두께로 형성된 희생층이며, 참조 번호 3은 갈륨 비소 또는 갈륨 비소와 알루미늄 갈륨 비소의 초격자 구조로 이루어진 완충층이고, 참조 번호 4는 실리콘이 도핑된 갈륨 비소층으로 수십에서 수백 나노미터의 두께를 갖는 채널층이다.FIG. 1 is a structure of an epitaxial layer for fabricating a polar thin film device, in which reference numeral 1 is a semi-insulating gallium arsenide substrate for epitaxial growth, and reference numeral 2 is an etching selection with the gallium arsenide substrate 1 of wet etching. Aluminum arsenic having a large ratio is a sacrificial layer formed to a thickness of about 50 ~ 500Å, reference numeral 3 is a buffer layer consisting of a superlattice structure of gallium arsenide or gallium arsenide and aluminum gallium arsenide, reference numeral 4 is a gallium arsenide layer doped with silicon It is a channel layer with a thickness of tens to hundreds of nanometers.
상기에서 완충층(3)은 성장시 기판(1)의 결함을 상기 채널층(4)으로 확산되는 것을 차단하고 채널층(4)의 누설 전류를 감소시킨다.The buffer layer 3 blocks the diffusion of the defects of the substrate 1 into the channel layer 4 during growth and reduces the leakage current of the channel layer 4.
상술한 제1도와 같은 구조를 염산 용액에 넣으면 갈륨 비소로 이루어진 완충층(3)과 채널층(4)는 식각이 되지않고 알루미늄 비소로 이루어진 희생층(2)만 식각되어 완충층(3)과 채널층(4)을 기판(1)과 분리할 수 있어 완충층(3)과 채널층(4)으로만 이루어진 극 박막소자를 제조할 수 있다.When the above structure shown in FIG. 1 is placed in a hydrochloric acid solution, the buffer layer 3 and the channel layer 4 made of gallium arsenide are not etched, and only the sacrificial layer 2 made of aluminum arsenide is etched to prevent the buffer layer 3 and the channel layer. (4) can be separated from the substrate 1, so that a polar thin film element composed of only the buffer layer 3 and the channel layer 4 can be manufactured.
제2도(a) 내지 (h)는 본 발명에 따른 극 박막소자의 제조 공정도이다.2 (a) to (h) is a manufacturing process diagram of the polar thin film device according to the present invention.
제2도(a)를 참조하면, 반절연성의 갈륨 비소 기판(1)의 상부에 갈륨 비소와 식각 선택비가 큰 알루미늄 비소로 이루어진 희생층(2)을 50~500Å 정도의 두께로, 갈륨 비소 또는 갈륨 비소와 알루미늄 갈륨 비소의 초격자 구조로 이루어진 완충층(3) 및 실리콘이 도핑된 갈륨 비소층으로 수십에서 수백 나노미터의 두께를 갖는 채널층(4)을 MBE 또는 MOCVD 등의 결정 성장 방법으로 순차적으로 결정 성장하여 형성한다.Referring to FIG. 2 (a), a sacrificial layer 2 made of gallium arsenide and aluminum arsenide having a large etching selectivity is formed on the semi-insulating gallium arsenide substrate 1 to a thickness of about 50 to 500 μm, and the gallium arsenide or the like. A buffer layer (3) composed of gallium arsenide and aluminum gallium arsenide, and a gallium arsenide layer doped with silicon, and the channel layer (4) having a thickness of several tens to several hundred nanometers is sequentially formed by a crystal growth method such as MBE or MOCVD. Formed by crystal growth.
그리고, 통상의 포토리쏘그래피 방법에 의해 상기 채널층(4)의 소정 부분을 상기 완충층(3)이 노출되도록 제거하여 소자를 분리한다.The device is separated by removing a predetermined portion of the channel layer 4 so that the buffer layer 3 is exposed by a conventional photolithography method.
제2도(b)를 참조하면, 상기 완충층(3)과 채널층(3)의 상부에 감광막(5)을 도포한 후 제2도(c)와 같이 칩 분리 마스크를 이용하여 노광 및 현상하여 상기 완충층(3)을 노출시킨다.Referring to FIG. 2B, after the photosensitive film 5 is coated on the buffer layer 3 and the channel layer 3, the photosensitive film 5 is exposed and developed using a chip separation mask as shown in FIG. 2C. The buffer layer 3 is exposed.
이때, 노출된 완충층(3)을 식각 선택비가 큰 구연산 용액과 과산화 수소를 3 : 1의 비율로 섞은 식각 용액을 이용하면 제2도(d)와 같이 상기 희생막(2)이 노출되도록 완충층(3)까지 식각할 수 있다.In this case, when the exposed buffer layer 3 is mixed with a citric acid solution having a large etching selectivity and hydrogen peroxide in a ratio of 3: 1, the buffer layer 2 is exposed to expose the sacrificial layer 2 as shown in FIG. It can be etched up to 3).
그리고, 상기 감광막(5)의 상부에 여분의 웨이퍼(6)를 왁스 등으로 제2도(e)와 같이 부착한 후 염산 용액에 담그면 노출 되어 있는 희생층(3)이 제거되어 제2도(f)와 같이 소자를 기판(1)으로 부터 분리된다.Then, the excess wafer 6 is attached to the upper portion of the photoresist film 5 with wax or the like as shown in FIG. 2E, and then immersed in a hydrochloric acid solution to remove the exposed sacrificial layer 3 to remove the The device is separated from the substrate 1 as in f).
그 다음, 완충층(3)의 노출면에 제2도(g)와 같이 금 또는 알루미늄 등을 증착하여 패키지 할 때의 열 방출을 효율적으로 할 수 있는 열방출층(7)을 형성한다.Next, as shown in FIG. 2 (g), gold or aluminum is deposited on the exposed surface of the buffer layer 3 to form a heat dissipation layer 7 capable of efficiently dissipating heat during packaging.
그리고, 상기 열방출층(7)의 표면에 열 전도성이 좋은 열전도기판(8)을 부착하고 아세톤에 의해 상기 감광막(5)을 제거하면 제2도(h)와 같이 된다.Then, when the thermally conductive substrate 8 having good thermal conductivity is attached to the surface of the heat dissipating layer 7 and the photosensitive film 5 is removed by acetone, the result is as shown in FIG.
따라서, 본 발명은 동시에 칩을 분리 할 수 있으며, 이렇게 분리된 칩은 두께가 수 마이크로 미터로 줄어들므로 열방출을 효율적으로 할 수 있어 전력소자의 성능을 향상시킬 수 있는 잇점이 있다.Therefore, the present invention can separate the chip at the same time, the separated chip is reduced to a few micrometers thickness can be efficiently released heat has the advantage of improving the performance of the power device.
Claims (5)
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