CN115020439A - LED display screen manufacturing method for small spacing and LED display screen - Google Patents
LED display screen manufacturing method for small spacing and LED display screen Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
- H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
- H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
- H01L33/387—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape with a plurality of electrode regions in direct contact with the semiconductor body and being electrically interconnected by another electrode layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/40—Materials therefor
- H01L33/42—Transparent materials
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Abstract
The invention provides a method for manufacturing an LED display screen with small spacing and the LED display screen, wherein the method comprises the following steps: carrying out epitaxial layer growth on different substrates to obtain each epitaxial wafer; forming a transparent conducting layer on the epitaxial wafer, and etching the transparent conducting layer to form a mesa step and a cutting channel exposing the first semiconductor layer; forming electrode layers with different polarities on the transparent conducting layer and the first semiconductor layer of the epitaxial wafer, and forming an insulating reflecting layer on the epitaxial wafer to expose the electrode layers; forming a common electrode communication layer on one electrode layer of at least two LED chips so as to combine the LED chips to form an LED chip group; forming a metal bonding layer on each other electrode layer of the LED chip group and the common electrode communication layer of one LED chip; grinding and thinning the substrate of the LED chip group and cutting along the cutting path; and testing, sorting and packaging each LED chip group to form the LED display screen. The invention solves the problem of low efficiency of the existing LED chip cutting, sorting and packaging.
Description
Technical Field
The invention relates to the technical field of photoelectricity, in particular to a method for manufacturing an LED display screen with small spacing and an LED display screen.
Background
With the continuous development of the LED display technology, the small-pitch LED display screen has a great potential in the future display field, and with the increasing demand of the display screen on the pixel density, that is, the LED chip size and the unit pitch are smaller and smaller, the difficulty at the packaging end will be larger and larger, a 4-inch epitaxial wafer forms a LED chip with a length and width of 50-400 μm after the chip front-end process is completed, and then the LED chip is ground, cut, tested and sorted, so that hundreds of thousands of orders of magnitude of LED chips are manufactured on the epitaxial wafer, then the LED chips in three bands of blue, green and red are packaged, and each three LED chips with different colors form a pixel point, and finally the LED display screen is assembled, as shown in fig. 5 in the prior art.
However, with the reduction of the size of the LED chip, the time required for cutting and sorting on an epitaxial wafer is more and more, which greatly affects the productivity, and meanwhile, due to the further reduction of the size of the LED chip, the difficulty from the chip end to the packaging end is higher and higher, the smaller the size of the LED chip is, the greater the difficulty in transferring is, the current packaging end can only package one LED chip by one LED chip, which undoubtedly greatly reduces the packaging speed, and when the size of the LED chip is small to be close to the micro level, the operation of sorting and packaging cannot be performed.
In addition, in most cases, each LED chip needs to be provided with two PAD points for electrical connection to achieve independent driving of each LED chip, which means that the driving sources on the PCB corresponding to the LED display screen also need to be in one-to-one correspondence with the number of the LED chips, thereby undoubtedly increasing the difficulty of manufacturing.
Disclosure of Invention
Based on the above, the invention aims to provide a method for manufacturing an LED display screen with small spacing and the LED display screen, so as to fundamentally solve the problem of low efficiency of the existing LED chip cutting, sorting and packaging.
The method for manufacturing the LED display screen with small spacing comprises the following steps:
respectively growing epitaxial layers on different substrates to obtain epitaxial wafers of different wave bands, wherein the epitaxial wafers comprise a red light epitaxial wafer, a green light epitaxial wafer and a blue light epitaxial wafer;
forming a transparent conducting layer on the second semiconductor layer on the surface of each epitaxial wafer, and etching the transparent conducting layer to form a mesa step exposing the first semiconductor layer and a cutting channel for cutting;
forming electrode layers with different polarities on the transparent conductive layer of each epitaxial wafer and the exposed first semiconductor layer respectively, and forming an insulating reflecting layer on each epitaxial wafer to expose the electrode layers;
a common electrode communication layer communicated with each electrode layer of the same polarity is formed on one of the electrode layers of the at least two LED chips of the same wave band, so that the communicated at least two LED chips of the same wave band are combined to form an LED chip group of the corresponding wave band;
respectively forming metal bonding layers on each other electrode layer of the LED chip group and a common electrode communication layer in one LED chip;
grinding and thinning the substrate of the LED chip group and cutting along a cutting channel at the peripheral LED chip in the LED chip group;
and sequentially testing, sorting and packaging the LED chip sets of each waveband to form the LED display screen.
In addition, the method for manufacturing the LED display screen with small spacing according to the above embodiment of the present invention may further have the following additional technical features:
further, the step of etching the transparent conductive layer to form a mesa step exposing the first semiconductor layer and a cutting street for cutting includes:
carrying out photoetching on the transparent conductive layer to form a mask with a special pattern of mesa, wherein the photoetching comprises gluing, exposing and developing operations;
removing the transparent conductive layer outside the mask by wet etching to expose the second semiconductor layer;
etching to expose the first semiconductor layer through ICP to form a mesa step, and removing the photoresist;
photoetching the surface of the epitaxial wafer to form an ISO special pattern mask;
and forming a cutting channel by ICP etching, and carrying out photoresist removing operation.
Further, the step of forming electrode layers with different polarities on the transparent conductive layer and the exposed first semiconductor layer of each epitaxial wafer includes:
photoetching the surface of the epitaxial wafer to form a special pattern mask of the electrode layer;
and respectively forming electrode layers with different polarities on the transparent conductive layer and the exposed first semiconductor layer by metal evaporation through a metal evaporation process, and performing photoresist removing operation.
Further, the insulating reflective layer includes an insulating protective layer and a reflective layer;
the step of forming the insulating reflecting layer on the epitaxial wafer and exposing the electrode layer comprises the following steps:
sequentially depositing an insulating protective layer and a reflecting layer on the epitaxial wafer;
photoetching the surface of the epitaxial wafer to form a special pattern mask of the insulating reflecting layer;
etching to expose the electrode layer by ICP, and removing photoresist.
Further, the step of forming a common electrode communication layer communicating with electrode layers of the same polarity on one of the electrode layers of at least two LED chips of the same wavelength band includes:
photoetching the surfaces of at least two LED chips with the same wave band to form a special pattern mask of a common electrode communication layer;
and forming a common electrode communication layer on one of the electrode layers exposed by the LED chips by metal evaporation through a metal evaporation process, so that the electrode layers with the same polarity of at least two LED chips with the same wave band are communicated through the common electrode communication layer, and performing photoresist removing operation.
Further, the step of forming metal bonding layers on each other electrode layer of the LED chip group and the common electrode communication layer in one of the LED chips respectively includes:
photoetching each LED chip of the LED chip group to form a special pattern mask of the metal bonding layer;
and respectively forming a metal bonding layer on the other electrode layer exposed by each LED chip and the common electrode communication layer in one of the LED chips by metal evaporation through a metal evaporation process, and performing photoresist stripping operation.
Further, the transparent conducting layer is an ITO transparent conducting layer, an FTO transparent conducting layer, a ZAO transparent conducting layer or a Ni micro-grid transparent conducting layer;
the metal composition of the electrode layer, the common electrode communication layer and the metal bonding layer comprises any one or combination of Cr, Al, Ti, Pt, Ni and Au;
the photoresist thickness corresponding to the photoetching is 2.5-10um, the exposure is 150-1000mj, and the developing time is 50-250 s.
According to the embodiment of the invention, the LED display screen for small spacing comprises the following components:
the LED chip sets are sequentially arrayed and distributed and have different wave bands, and each LED chip set comprises a red LED chip set, a green LED chip set and a blue LED chip set;
the LED chip group consists of at least two LED chips, and each LED chip comprises a substrate, and an epitaxial layer, a transparent conducting layer, an electrode layer, an insulating reflecting layer, a common electrode communication layer and a metal bonding layer which are sequentially stacked on the substrate;
the epitaxial layer is including range upon range of in proper order first semiconductor layer, luminescent layer and the second semiconductor layer on the substrate, transparent conducting layer locates on the second semiconductor layer, the electrode layer is located respectively first semiconductor layer reaches on the transparent conducting layer, be equipped with on the insulating reflection stratum and expose the opening of electrode layer, common electrode UNICOM layer locates and exposes on one of them opening of electrode layer, and mutual UNICOM between the common electrode UNICOM layer in each LED chip, the metal bonding layer is located and is exposed on another opening of electrode layer, and still be equipped with on the common electrode UNICOM layer in one of them LED chip in the LED chipset the metal bonding layer.
Further, the metal components of the electrode layer, the common electrode communication layer and the metal bonding layer comprise any one or combination of Cr, Al, Ti, Pt, Ni and Au.
Further, the insulating reflective layer comprises an insulating protective layer and a reflective layer, wherein the insulating protective layer comprises a SiN layer or SiO layer 2 A layer comprising an Ag reflective layer or a DBR reflective layer.
Compared with the prior art: the common electrode communication layer is arranged to communicate the electrode layers with the same polarity in at least two LED chips to form an LED chip group, so that the LED chips are only required to be cut into the LED chip group instead of each LED chip, the cutting efficiency is improved, and meanwhile, the LED chips on the LED chip group can be considered as a whole to be sorted and packaged, so that the sorting and packaging of the LED chips can be realized at one time, the size of the LED chips is enlarged in a phase-changing manner, and the sorting and packaging difficulty is reduced; meanwhile, the sorting and packaging of the LED chips can be carried out at one time, so that the sorting and packaging efficiency is effectively improved, and meanwhile, when the metal bonding layers are arranged, one electrode layer in each LED chip group is connected through the common electrode communication layer, so that only one metal bonding layer is needed to be arranged to complete the packaging of one electrode of the LED chip group and the packaging of the other electrode of the LED chip group is completed by the metal bonding layers corresponding to the number of the LED chips, and the using number of the metal bonding layers in the packaging end can be reduced. Meanwhile, the use of the driving source required by the corresponding metal bonding layer is reduced in the packaging process, the number of the driving sources on the PCB is correspondingly reduced, the manufacturing difficulty of the PCB is reduced, and meanwhile, the voltage or the current of a certain level of each LED chip in the LED chip set can be kept consistent, so that the display of the LED display screen can be better controlled, and the problem of low packaging efficiency in the existing LED chip cutting and sorting process is solved.
Drawings
FIG. 1 is a flow chart of a method for manufacturing a small-pitch LED display screen according to a first embodiment of the present invention;
FIG. 2 is a schematic diagram of a second embodiment of an LED display screen with small pitch;
FIG. 3 is a schematic diagram of an LED chip set in an LED display screen with small pitch according to a second embodiment of the present invention;
FIG. 4 is a cross-sectional view of LED chips in a second embodiment of the present invention for small pitch LED display;
fig. 5 is a schematic structural diagram of an LED display screen in the prior art.
The following detailed description will further illustrate the invention in conjunction with the above-described figures.
Detailed Description
To facilitate an understanding of the invention, the invention will now be described more fully with reference to the accompanying drawings. Several embodiments of the invention are presented in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
It will be understood that when an element is referred to as being "secured to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. The terms "vertical," "horizontal," "left," "right," and the like as used herein are for illustrative purposes only.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
Example one
Referring to fig. 1, a method for manufacturing a small-pitch LED display screen according to a first embodiment of the present invention is shown, and the method specifically includes steps S01-S07.
And step S01, respectively growing epitaxial layers on different substrates to obtain epitaxial wafers with different wave bands, wherein the epitaxial wafers comprise a red light epitaxial wafer, a green light epitaxial wafer and a blue light epitaxial wafer.
In the embodiment of the invention, the manufacturing method is used for manufacturing the LED display screen, wherein the LED display screen is composed of a plurality of pixel points arranged in an array, the longitudinal and transverse number of the pixel points is set according to the pixel resolution required by the LED display screen, each pixel point is composed of LED chips with three different wave bands of blue, green and red, therefore, in order to realize the manufacturing of the LED display screen, the LED chips with three wave bands are firstly prepared, an epitaxial layer is usually prepared on a large substrate to obtain an epitaxial wafer, then the P electrode and the N electrode are prepared on the epitaxial wafer, so that an LED wafer is prepared, at the moment, hundreds of thousands of orders of magnitude of LED chips can be prepared on one epitaxial wafer, and the prepared LED wafer is ground and cut to obtain the final LED chips.
Therefore, the epitaxial layers are grown on different substrates respectively to obtain epitaxial wafers of each waveband, namely, a red epitaxial wafer, a green epitaxial wafer and a blue epitaxial wafer, wherein the element composition ratio of semiconductors in the epitaxial layers is mainly adjusted to enable a light emitting layer in the epitaxial layers to emit a desired wavelength, such as ultraviolet, blue, red, infrared and other light radiation, at the moment, specific materials of the epitaxial layers in the epitaxial wafers of each waveband are set according to actual production application, so that the required red epitaxial wafer, green epitaxial wafer and blue epitaxial wafer can be prepared, and no specific limitation is made herein.
The substrate is a substrate for epitaxial layer growth, and has the functions of supporting and stabilizing. The substrate may be an insulating substrate or a conductive substrate, and the substrate may be a planar substrate or a patterned substrate. Wherein the substrate material includes, but is not limited to, sapphire, aluminum nitride, gallium nitride, silicon, and silicon carbide. In the embodiment of the invention, the substrate is a sapphire substrate.
Further, the epitaxial layer includes a first semiconductor layer, a light emitting layer, and a second semiconductor layer sequentially stacked on the substrate, wherein a polarity of the first semiconductor layer is opposite to a polarity of the second semiconductor layer. In an embodiment of the present invention, the first semiconductor layer is an N-type semiconductor layer, such as an N-type gallium nitride layer (GaN); correspondingly, the second semiconductor layer is a P-type semiconductor layer, such as a P-type gallium nitride layer. Note that the N-type semiconductor layer is a semiconductor layer formed by silicon doping or carbon doping, and the P-type semiconductor layer is a semiconductor layer formed by magnesium doping or zinc doping. It is understood that, in other embodiments of the present invention, the first semiconductor layer may also be a P-type semiconductor layer, and the second semiconductor layer may also be an N-type semiconductor layer, and the epitaxial wafer is manufactured according to actual production conditions and requirements, which is not limited herein.
Step S02, forming a transparent conductive layer on the second semiconductor layer on the surface of each epitaxial wafer, and etching the transparent conductive layer to form a mesa step exposing the first semiconductor layer and a scribe line for cutting.
In the embodiment of the present invention, after the epitaxial wafer of each wavelength band is grown on the substrate, a transparent conductive layer is deposited on the second semiconductor layer (i.e., the P-type semiconductor layer) on the surface of each epitaxial wafer, and the transparent conductive layer is obtained by depositing in a magnetron sputtering bombardment target manner, wherein the transparent conductive layer is an ITO (tin-doped indium oxide) transparent conductive layer, an FTO (fluorine-doped tin oxide) transparent conductive layer, a ZAO (aluminum-doped zinc oxide) transparent conductive layer, or a Ni micro-grid transparent conductive layer, specifically, the ITO transparent conductive layer is used in the present embodiment, and the thickness of the deposited transparent conductive layer is 120-1200A (angstrom), and the transparent conductive layer is used to facilitate current diffusion and form ohmic contact.
Further, in the embodiment of the present invention, after forming the transparent conductive layer on the second semiconductor layer on the surface of each epitaxial wafer, the transparent conductive layer is etched to form a mesa step exposing the first semiconductor layer and a cutting street for cutting, and the steps include:
carrying out photoetching on the transparent conductive layer to form a mask with a special pattern of mesa, wherein the photoetching comprises gluing, exposing and developing operations; removing the transparent conductive layer outside the mask by wet etching to expose the second semiconductor layer; etching to expose the first semiconductor layer through ICP to form a mesa step, and removing the photoresist; photoetching the surface of the epitaxial wafer to form an ISO special pattern mask; and forming a cutting channel by ICP etching, and carrying out photoresist removing operation.
Specifically, a layer of photoresist is coated on the surface of a transparent conducting layer, wherein the photoresist thickness corresponding to photoetching is 2.5-10um, then the photoresist layer formed on the transparent conducting layer is exposed and developed through a mesa photoetching plate, wherein the exposure amount is 150-1000mj (milli-coke), the developing time is 50-250s, so as to form the photoresist layer with a mesa special pattern, at this time, the photoresist layer with the mesa special pattern is used as a mask, then the transparent conducting layer outside the mask is corroded by a wet method through a mixed solution obtained by mixing hydrochloric acid and ferric chloride according to a certain proportion (hydrochloric acid: ferric chloride: 10: 22) to expose a second semiconductor layer, and then ICP is carried out to further etch the surface of an epitaxial wafer downwards by about 1um until the first semiconductor layer is exposed to form a mesa step, wherein, the thicknesses of the second semiconductor layer and the light emitting layer are not 1um thick, a small part of the first semiconductor layer can be correspondingly etched when ICP etches about 1um, and the first semiconductor layer is mainly used for etching until the first semiconductor layer is completely exposed. Wherein the cavity temperature in ICP etching is 0-5 deg.C, and the corresponding etching gas is Cl 2 (chlorine gas), BCl 3 (boron trichloride), CF 4 (carbon tetrafluoride), etc., the corresponding etching time is 100-2000s, in the embodiment of the invention, Cl is adopted 2 The ICP etching of (1) is 900 s. And then removing the photoresist layer to expose the etched transparent conductive layer on the second semiconductor layer. Wherein it is pointed out that the etching forms mesa stepsAnd then, respectively manufacturing electrodes on the first semiconductor layer and the transparent conducting layer to obtain each LED chip, wherein when photoetching mask is carried out, the distance between the single LED chips on the PCB needs to be matched, so that the metal bonding layer on each LED chip in the LED chip group manufactured subsequently can be matched with each driving source on the PCB.
Further, the photoetching operation is carried out on the etched epitaxial wafer according to the above, so that an ISO special pattern mask is formed by photoetching, and then Cl is carried out 2 The ICP etches 1650s, so that the first semiconductor layer on the mesa step is etched continuously to form a cutting channel, then the photoresist removing operation is performed, the cutting channel is located at the periphery of each LED chip, the subsequent cutting operation and cutting alignment are facilitated, the LED wafer made of the epitaxial wafer is cut to form a plurality of independently dispersed LED chips, and the risk of cutting fracture possibly generated when the cutting channel is not arranged is avoided.
In step S03, electrode layers with different polarities are formed on the transparent conductive layer and the exposed first semiconductor layer of each epitaxial wafer, and an insulating reflective layer is formed on the epitaxial wafer to expose the electrode layers.
In an embodiment of the present invention, the step of forming electrode layers with different polarities on the transparent conductive layer and the exposed first semiconductor layer of each epitaxial wafer respectively includes:
photoetching the surface of the epitaxial wafer to form a special pattern mask of the electrode layer;
and respectively forming electrode layers with different polarities on the transparent conductive layer and the exposed first semiconductor layer by metal evaporation through a metal evaporation process, and performing photoresist removing operation.
Specifically, the foregoing photolithography operation is performed on the epitaxial wafer processed in step S02 to form a mask with a special pattern of the electrode layer by photolithography, and then metal is evaporated on the transparent conductive layer and the exposed first semiconductor layer by a metal evaporation process to form electrode layers with different polarities, respectively, and then a photoresist removal operation is performed. Specifically, it forms a first polarity on the first semiconductor layerAn electrode layer (i.e., an N electrode layer), and a second polarity electrode layer (i.e., a P electrode layer) formed on the transparent conductive layer. Wherein the metal evaporation process comprises the steps of firstly carrying out vacuum pumping operation, and enabling the vacuum degree to reach 1X10 -2 And starting to evaporate a target material of a corresponding metal after the torr so as to evaporate the metal to the surface of the epitaxial wafer, wherein the plating rate is 0.1-10A/s, the metal composition of the electrode layer comprises any one or more combinations of Cr, Al, Ti, Pt, Ni and Au, and the specific combination mode is combined according to the experimental design and the required capacity and is not limited specifically.
Specifically, as an example of the present invention, the metal composition and the corresponding thickness of the electrode layer are shown in table 1 below, that is, the metal is evaporated one by one in table 1 below, and the unit of the metal thickness is a (angstrom), that is, Cr (chromium) with a thickness of 50A is evaporated first, then Al (aluminum) with a thickness of 1200A is evaporated, and finally Ti (titanium) with a thickness of 50A is evaporated.
| Cr | Al | Ti | Pt | Ti | Pt | Au | Pt | Pt | Ti |
| 50 | 1200 | 1000 | 500 | 1000 | 500 | 9300 | 1100 | 1100 | 50 |
TABLE 1
Further, in an embodiment of the present invention, the step of forming the insulating reflective layer on the epitaxial wafer and exposing the electrode layer includes:
sequentially depositing an insulating protective layer and a reflecting layer on the epitaxial wafer; photoetching the surface of the epitaxial wafer to form a special pattern mask of the insulating reflecting layer; etching to expose the electrode layer by ICP, and removing photoresist.
Specifically, the insulating reflective layer comprises an insulating protective layer and a reflective layer, wherein after the electrode layer is evaporated, the insulating protective layer with the thickness of 2000-8000A is deposited, and then the reflective layer with the thickness of 6000-60000A is deposited, so that the insulating reflective layer is formed. Wherein the insulating protective layer can be SiN layer or SiO 2 The reflective layer may be an Ag reflective layer or a DBR (distributed Bragg reflector) reflective layer. The insulating reflecting layer is used for reflecting light emitted by the light emitting layer in the epitaxial layer, so that the light is emitted from the back surface of the LED chip. Further, a special pattern mask of the insulating reflective layer is formed on the surface of the epitaxial wafer through photoetching, then part of the insulating reflective layer on the electrode layer is subjected to ICP etching as described above, so that the electrode layer is exposed, and then photoresist removing operation is carried out.
Step S04, a common electrode communication layer communicating with each electrode layer of the same polarity is formed on one of the electrode layers of the at least two LED chips of the same wavelength band, so that the at least two LED chips of the same wavelength band are combined to form an LED chip group of the corresponding wavelength band.
In an embodiment of the present invention, the step S04 specifically includes:
photoetching the surfaces of at least two LED chips with the same wave band to form a special pattern mask of a common electrode communication layer; and forming a common electrode communication layer on one of the electrode layers exposed by the LED chips by metal evaporation through a metal evaporation process, so that the electrode layers with the same polarity of at least two LED chips with the same wave band are communicated through the common electrode communication layer, and performing photoresist removing operation.
It should be noted that the LED chip is obtained completely after the electrode is fabricated on the epitaxial wafer and after the electrode is ground and cut, and the overall structure of the LED chip can be shown in fig. 4, but in the embodiment of the present invention, the structure obtained after the above operation is described on the epitaxial wafer, so the LED chip is referred to as an LED chip herein. Referring to fig. 3, the above-mentioned steps specifically take a common cathode as an example, and a common electrode connection layer is evaporated on an N electrode layer (i.e., an electrode layer above the exposed first semiconductor layer) of three LED chips (e.g., red LED chips on a red light epitaxial wafer) of the same wavelength band, so that the common electrode connection layer can be connected with the N electrode layer of each LED chip, thereby implementing the common cathode, and at this time, the three red LED chips can be subsequently and finally combined to form a red LED chip set due to the connection of the common electrode connection layer. As for the LED chips in other bands, it should be noted that the number of LED chips communicated by the common electrode communication layer in the LED chip sets in each band formed by the LED chips should be consistent, for example, the number of red LED chips in the manufactured red LED chip set is 3, the number of green LED chips in the corresponding green LED chip set should also be 3, and the number of blue LED chips in the blue LED chip set should also be 3. It is understood that, in other embodiments of the present invention, the number of the LED chips in the LED chip set is at least two, and besides the three, the number of the LED chips may also be four, six, and the like, which is not limited herein. The common electrode communication layer can be further evaporated on a P electrode layer of the LED chip to form a common anode, and the common anode is arranged according to actual use requirements. The metal composition of the common electrode communication layer includes any one or more combinations of Cr, Al, Ti, Pt, Ni, and Au, and the specific combination manner is combined according to experimental design and required capability, and is not limited specifically herein.
Step S05, forming metal bonding layers on each other electrode layer of the LED chip set and the common electrode communication layer in one of the LED chips, respectively.
In an embodiment of the present invention, the step S05 specifically includes:
photoetching each LED chip of the LED chip group to form a special pattern mask of the metal bonding layer; and respectively forming a metal bonding layer on the other electrode layer exposed by each LED chip and the common electrode communication layer in one of the LED chips by metal evaporation through a metal evaporation process, and performing photoresist stripping operation.
Specifically, the LED chip group formed after the processing of step S04 is subjected to the photolithography operation described above, so that a mask with a special pattern of a metal bonding layer is formed by photolithography, then metal is evaporated on another electrode layer (P electrode layer) in each LED chip and a common electrode communication layer in one of the LED chips by a metal evaporation process to form a metal bonding layer (i.e., PAD dot), and then a photoresist stripping operation is performed. For example, as shown in fig. 2 and 3, a negative electrode metal bonding layer (N-type PAD point) is formed on a common electrode connection layer of a middle LED chip in an LED chip group having three LED chips, and positive electrode metal bonding layers (P-type PAD points) are formed on the other electrode layers of the LED chips, respectively.
Further, the metal composition of the metal bonding layer includes any one or more combinations of Cr, Al, Ti, Pt, Ni, and Au, and the specific combination manner is combined according to the experimental design and the required capability, which is not limited herein. Specifically, as an example of the present invention, the metal composition and the corresponding thickness of the metal bonding layer are shown in table 2 below, that is, the metal bonding layer is evaporated one by one according to the following table 2, and the unit of the metal thickness is a (angstrom), that is, Cr with a thickness of 16000A is evaporated first, and then Ti with a thickness of 1000A, and Au (gold) with a thickness of 2000A is evaporated till the end.
| Al | Ti | Pt | Ti | Ni | Au |
| 16000 | 1000 | 2000 | 500 | 4000 | 2000 |
TABLE 2
It should be noted that, in the embodiment of the present invention, the above steps S02-S05 all use a photolithography mask manner to perform deposition, evaporation or etching to form the above various structures, but it should be understood that, in other embodiments of the present invention, it may also directly perform deposition, evaporation or the like without using a photolithography mask manner, and then remove unnecessary portions by using laser ablation or the like when a desired special pattern is required, thereby achieving the same effect as that of the photolithography mask.
And step S06, grinding and thinning the substrate of the LED chip group and cutting along the cutting path at the peripheral LED chip in the LED chip group.
In the embodiment of the invention, after the metal bonding layer is evaporated on each LED chip in the LED chip set, the substrate in each LED chip in the LED chip set is ground and thinned, so that the whole thickness of the ground epitaxial wafer is 150-300 mu m, wherein the sapphire substrate is thick during conventional manufacturing, so that light absorption can be carried out, the emergent brightness of the LED chip is reduced, and the light absorption can be reduced by grinding and thinning the sapphire substrate, so that the brightness is improved. Meanwhile, after the substrate is ground and thinned, subsequent cutting and sorting operations are facilitated.
Furthermore, after the substrate of the LED chip group is ground, a cutting operation is performed to cut and disperse the LED chips on the manufactured LED wafer, wherein the cutting operation is specifically performed along cutting lanes on the LED chips on the periphery of the LED chip group, so in the embodiment of the present invention, the LED chips obtained by cutting are not scattered LED chips in the prior art, but are cut into LED chip groups using the LED chip group as a unit. Meanwhile, when the number of the LED chips contained in the LED chip group is larger, the cutting time and times are remarkably reduced, and the cutting efficiency is improved.
And step S07, testing, sorting and packaging the LED chip sets of each wave band in sequence to form the LED display screen.
In the embodiment of the invention, after the cutting is finished to obtain each LED chip group, each LED chip group is tested to test the photoelectric characteristic and the appearance state of the LED chip group, and after the testing is finished, each LED chip group with the same specification is sorted and packaged.
When the photoelectric characteristic test is carried out on the LED chips manufactured and formed by the epitaxial wafers, one probe is pricked on the negative metal bonding layer, the other probe is pricked on one positive metal bonding layer, and at the moment, the corresponding LED chip can be lightened when the probe is pricked on any one positive metal bonding layer, so that the photoelectric characteristic test of the LED chip is realized. Because each LED chip of the LED chip group realizes a common cathode through the common electrode communication layer, when the LED chip tests each LED chip in the LED chip group, a probe pricked on the negative electrode metal bonding layer does not need to be moved, and at the moment, another probe pricked on the positive electrode metal bonding layer is moved, so that the moving times of the probe in the test process are reduced.
It should be noted that, in this embodiment, it may be implemented by driving each positive electrode metal bonding layer to light a single LED chip in the LED chip set, and when it needs to light the entire LED chip set each time in other embodiments of the present invention, it may further set two groups of common electrode communication layers in step S04, that is, one group of common electrode communication layers communicates with P electrode layers on all LED chips in the LED chip set, and the other group of common electrode communication layers communicates with N electrode layers on all LED chips in the LED chip set, at this time, it only needs to form metal bonding layers on two common electrode communication layers in one LED chip in the LED chip set respectively in step S05. That is, only two metal bonding layers are needed to realize the integral control of each LED chip in the LED chip group, so that the test times are more effectively reduced, and the test efficiency is improved.
Furthermore, because the LED chips need to be individually sorted and packaged at present, the sorting and packaging difficulty of the LED chips can be improved along with the reduction of the size of the LED chips, and in the embodiment of the invention, the distance between the single LED chips on the PCB is matched by adopting the design of the photoetching mask during the manufacturing of the LED chip end, so that the sorting and packaging can be carried out by taking a plurality of LED chips on an LED chip group as a whole, the sorting and packaging of the plurality of LED chips can be carried out at one time, the size of the LED chips is enlarged in a phase change manner, and the sorting and packaging difficulty is reduced; meanwhile, the sorting and packaging of the LED chips can be carried out at one time, so that the sorting and packaging efficiency is effectively improved.
Meanwhile, when the metal bonding layers are arranged, after the N electrode layers in each LED chip group are connected through the common electrode communication layer, only one metal bonding layer is needed to be arranged to complete N-pole packaging of the LED chip group and the metal bonding layers corresponding to the number of the LED chips to complete P-pole packaging of the LED chip group, namely only N +1 metal bonding layers are needed in one LED chip group, wherein N is the number of the LED chips in the LED chip group, and 2N metal bonding layers are needed in the prior art. In this embodiment, as shown in fig. 2 and 3, each LED chip group only needs to be provided with four metal bonding layers, whereas in the prior art, as shown in fig. 5, six metal bonding layers need to be provided for three LED chips, so that the number of metal bonding layers used in the package end can be reduced. Meanwhile, the use of driving sources required by corresponding metal bonding layers is reduced in the packaging process, the number of the driving sources arranged on the PCB is correspondingly reduced, the manufacturing difficulty of the PCB is reduced, and meanwhile, the voltage or the current of a certain level of each LED chip in the LED chip set can be kept consistent, so that the display of the LED display screen can be better controlled.
In summary, in the method for manufacturing the LED display screen for small pitch in the above embodiments of the present invention, the common electrode communication layer is arranged to communicate the electrode layers of the same polarity in at least two LED chips to form the LED chip set, so that the LED chip set is only required to be cut instead of each LED chip, thereby improving the cutting efficiency, and meanwhile, the LED chips on the LED chip set can be regarded as a whole to be sorted and packaged, thereby achieving the purpose of sorting and packaging the LED chips at one time, so that the size of the LED chips is enlarged in a phase-changing manner, and the difficulty in sorting and packaging is reduced; meanwhile, the sorting and packaging of the LED chips can be carried out at one time, so that the sorting and packaging efficiency is effectively improved, and meanwhile, when the metal bonding layers are arranged, one electrode layer in each LED chip group is connected through the common electrode communication layer, so that only one metal bonding layer is needed to be arranged to complete the packaging of one electrode of the LED chip group and the packaging of the other electrode of the LED chip group is completed by the metal bonding layers corresponding to the number of the LED chips, and the using number of the metal bonding layers in the packaging end can be reduced. Meanwhile, the use of the driving source required by the corresponding metal bonding layer is reduced in the packaging process, the number of the driving sources on the PCB is correspondingly reduced, the manufacturing difficulty of the PCB is reduced, and meanwhile, the voltage or the current of a certain level of each LED chip in the LED chip set can be kept consistent, so that the display of the LED display screen can be better controlled, and the problem of low packaging efficiency in the existing LED chip cutting and sorting process is solved.
Example two
Referring to fig. 2 to 4, LED display screens for small pitch in a second embodiment of the present invention are shown, and for convenience of illustration, only the portions related to the embodiment of the present invention are shown, and the LED display screens according to the embodiment of the present invention include:
the LED chip sets are sequentially arrayed and distributed and have different wave bands, and each LED chip set comprises a red LED chip set 1, a green LED chip set 2 and a blue LED chip set 3;
the LED chip group consists of at least two LED chips, wherein each LED chip comprises a substrate 10, and an epitaxial layer 11, a transparent conducting layer 12, an electrode layer 13, an insulating reflecting layer 14, a common electrode communication layer 15 and a metal bonding layer 16 which are sequentially stacked on the substrate 10;
the epitaxial layer 11 includes a first semiconductor layer 111, a light emitting layer 112, and a second semiconductor layer 113 stacked on the substrate 10 in sequence, the transparent conductive layer 12 is disposed on the second semiconductor layer 113, the electrode layers 13 are disposed on the first semiconductor layer 111 and the transparent conductive layer 12, the insulating reflective layer 14 is provided with an opening exposing the electrode layer 13, the common electrode communication layer 15 is disposed on one opening exposing the electrode layer 13, the common electrode communication layers 15 in the LED chips are communicated with each other, the metal bonding layer 16 is disposed on the other opening exposing the electrode layer 13, and the metal bonding layer 16 is further disposed on the common electrode communication layer 15 in one of the LED chips in the LED chip set.
Wherein, as shown in fig. 2, the LED display screen is composed of a plurality of pixels arranged in an array, and the LED display screen specifically sets the longitudinal and transverse number of the pixels according to the pixel resolution required by the LED display screen, wherein each pixel is composed of three LED chips with different bands of blue, green and red, that is, as shown in fig. 2, the three common combinations of the blue LED chip, the green LED chip and the red LED chip constitute one pixel, and the pixel pitch of each pixel is set according to the actual use requirement, and specifically in this embodiment 390um is taken as an example. Meanwhile, the LED chips with different wave bands all comprise the structure, and only the growth material of the epitaxial layer 11 is controlled correspondingly according to the required wave band.
The substrate 10 is a substrate on which the epitaxial layer 11 is grown, and has a supporting and stabilizing function. The substrate 10 may be an insulating substrate or a conductive substrate, and the substrate 10 may be a planar substrate 10 or a patterned substrate 10. Wherein the material of the substrate 10 includes, but is not limited to, sapphire, aluminum nitride, gallium nitride, silicon, and silicon carbide. In the embodiment of the present invention, the substrate 10 is a sapphire substrate 10.
Further, an epitaxial layer 11 is formed on the substrate 10, wherein the epitaxial layer 11 may be formed by growing on the substrate 10 by a Metal Organic Chemical Vapor Deposition (MOCVD) apparatus, and the epitaxial layer 11 may also be bonded on the substrate 10 by a transparent bonding layer bonding method. As an example of the present invention, the epitaxial layer 11 includes a first semiconductor layer 111, a light emitting layer 112, and a second semiconductor layer 113, which are sequentially disposed on the substrate 10, wherein a polarity of the first semiconductor layer 111 is opposite to a polarity of the second semiconductor layer 113. In the present embodiment, the first semiconductor layer 111 is an N-type semiconductor layer, such as an N-type gallium nitride (GaN) layer; accordingly, the second semiconductor layer 113 is a P-type semiconductor layer, such as a P-type gallium nitride layer. Note that the N-type semiconductor layer is a semiconductor layer formed by silicon doping or carbon doping, and the P-type semiconductor layer is a semiconductor layer formed by magnesium doping or zinc doping. It is understood that, in other embodiments of the present invention, the first semiconductor layer 111 may also be a P-type semiconductor layer, and the second semiconductor layer 113 may also be an N-type semiconductor layer, which is fabricated with a corresponding epitaxial wafer according to actual production conditions and requirements.
Furthermore, the light emitting layer 112 includes quantum well layers and quantum barrier layers that are periodically and alternately grown in sequence, wherein the quantum well layers and the quantum barrier layers are periodically and alternately grown in sequence, so that at least one composite well can be formed in the light emitting layer 112, and the composite well can improve the light emitting efficiency of the light emitting diode chip. The light emitting layer 112 may be made of gallium nitride based material, gallium arsenide based material, etc., and the element composition ratio of the semiconductor may be adjusted to emit light with desired wavelength, such as providing light radiation of ultraviolet, blue, red, infrared, etc.
Furthermore, after the epitaxial layer 11 is fabricated, a transparent conductive layer 12 is deposited by bombarding the target material with magnetron sputtering, and the transparent conductive layer 12 is disposed on the second semiconductor layer 113 (i.e. the P-type semiconductor layer), wherein the transparent conductive layer 12 is an ITO (tin-doped indium oxide) transparent conductive layer, an FTO (fluorine-doped tin oxide) transparent conductive layer, a ZAO (aluminum-doped zinc oxide) transparent conductive layer or a Ni micro-grid transparent conductive layer, the transparent conductive layer 12 is made of ITO (indium tin oxide) and the thickness of the transparent conductive layer 12 is 120-1200A (angstroms), at this time, since the transparent conductive layer 12 is entirely laid on the second semiconductor layer 113, the current diffusion and ohmic contact with the second semiconductor layer 113 are facilitated, meanwhile, the transparent conductive layer 12 is transparent and does not block the light emitted from the light-emitting layer 112.
Furthermore, after the transparent conductive layer 12 is manufactured, the second semiconductor layer 113 and the light emitting layer 112 in the epitaxial layer 11 on one side are etched by the wet etching and ICP etching processes described in the above method embodiment until the first semiconductor layer 111 is exposed, so that a mesa step is formed by etching. Further, in the embodiment of the present invention, each LED chip of the same wavelength band is formed by growing the same substrate 10, that is, each epitaxial layer 11, the transparent conductive layer 12, the electrode layer 13, the insulating reflective layer 14, the common electrode communication layer 15, and the metal bonding layer 16 are formed on the whole substrate 10, and then cut by the cutting process, so that each LED chip is finally formed. Therefore, in order to facilitate the subsequent cutting operation and the cutting alignment, the cutting street 17 is disposed at the boundary between the LED chips, and specifically, the first semiconductor layer 111 is further etched on the mesa step by the etching process, so that one cutting street 17 is etched, which is shown in fig. 3.
Further, the transparent conductive layer 12 of each epitaxial wafer and the exposed first semiconductor layer 111 are respectively formed with electrode layers 13 with different polarities, that is, the electrode layers 13 are respectively disposed on the first semiconductor layer 111 and the transparent conductive layer 12, specifically, a first polarity electrode layer (i.e., an N electrode layer) is formed on the first semiconductor layer 111, and a second polarity electrode layer (i.e., a P electrode layer) is formed on the transparent conductive layer 12.
Furthermore, after the electrode layer 13 is manufactured, the insulating reflective layer 14 is deposited by the photolithography and evaporation process described in the above method embodiment, and the insulating reflective layer 14 is provided with an opening exposing the electrode layer 13. The insulating reflective layer 14 comprises an insulating protective layer and a reflective layer, wherein the insulating protective layer and the reflective layer are sequentially arranged from bottom to top, and the insulating protective layer comprises an SiN layer or SiO layer 2 A reflective layer including an Ag reflective layer or a DBR reflective layer, wherein the insulating reflective layer 14 is used to reflect light emitted from the light emitting layer 112 in the epitaxial layer 11 so that light is emitted from the rear surface of the LED chip.
Furthermore, a layer of common electrode communication layer 15 for communicating the LED chips is further disposed, and at this time, the common electrode communication layer 15 is disposed on one of the openings exposing the electrode layer 13, specifically in this embodiment, the common electrode communication layer 15 is disposed on the opening corresponding to the first polarity electrode layer, so that the common electrode communication layer 15 communicates the first polarity electrode layer of the LED chips, thereby implementing a common electrode.
Furthermore, a negative metal bonding layer (N-type PAD point) is disposed on the opening of the second polarity electrode layer, and a positive metal bonding layer (P-type PAD point) is disposed on the common electrode communication layer 15 of one of the LED chips in the LED chip set.
Further, the metal components of the electrode layer 13, the common electrode via layer 15 and the metal bonding layer 16 include any one or more of Cr, Al, Ti, Pt, Ni and Au. Specifically, as an example of the present invention, the metal composition and the corresponding thickness of the electrode layer 13 are shown in table 1 in the foregoing method embodiment, that is, the electrode layer 13 includes a Cr (chromium) layer, an Al (aluminum) layer, a Ti (titanium) layer, a Pt (platinum) layer, a Ti layer, a Pt layer, an Au (gold) layer, a Pt layer, and a Ti layer, which are sequentially disposed from bottom to top. The metal composition and the corresponding thickness of the metal bonding layer 16 are shown in table 2 in the foregoing method embodiment, that is, the metal bonding layer 16 includes an Al layer, a Ti layer, a Pt layer, a Ti layer, a Ni (nickel) layer, and an Au layer, which are sequentially disposed from bottom to top.
In summary, in the LED display screen for small pitch in the above embodiments of the present invention, the common electrode communication layer is arranged to communicate the electrode layers of the same polarity in at least two LED chips to form an LED chip set, so that the LED chip set is only required to be cut instead of each LED chip, thereby improving the cutting efficiency, and meanwhile, the LED chips on the LED chip set can be regarded as a whole to be sorted and packaged, thereby achieving the purpose of sorting and packaging the LED chips at one time, so that the size of the LED chips is enlarged by changing the phase, and the sorting and packaging difficulty is reduced; meanwhile, because the sorting and packaging of the LED chips can be carried out once, the sorting and packaging efficiency is effectively improved, and meanwhile, when the metal bonding layers are arranged, one electrode layer in each LED chip group is connected through the common electrode connection layer, one electrode of the LED chip group is packaged by only arranging one metal bonding layer, and the other electrode of the LED chip group is packaged by the metal bonding layers corresponding to the number of the LED chips, so that the using number of the metal bonding layers in the packaging end can be reduced. Meanwhile, the use of the driving source required by the corresponding metal bonding layer is reduced in the packaging process, the number of the driving sources on the PCB is correspondingly reduced, the manufacturing difficulty of the PCB is reduced, and meanwhile, the voltage or the current of a certain level of each LED chip in the LED chip set can be kept consistent, so that the display of the LED display screen can be better controlled, and the problem of low packaging efficiency in the existing LED chip cutting and sorting process is solved.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the present invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. A method for manufacturing an LED display screen with small spacing is characterized by comprising the following steps:
respectively growing epitaxial layers on different substrates to obtain epitaxial wafers of different wave bands, wherein the epitaxial wafers comprise a red light epitaxial wafer, a green light epitaxial wafer and a blue light epitaxial wafer;
forming a transparent conducting layer on the second semiconductor layer on the surface of each epitaxial wafer, and etching the transparent conducting layer to form a mesa step exposing the first semiconductor layer and a cutting channel for cutting;
forming electrode layers with different polarities on the transparent conductive layer of each epitaxial wafer and the exposed first semiconductor layer respectively, and forming an insulating reflecting layer on each epitaxial wafer to expose the electrode layers;
a common electrode communication layer communicated with each electrode layer of the same polarity is formed on one of the electrode layers of the at least two LED chips of the same wave band, so that the communicated at least two LED chips of the same wave band are combined to form an LED chip group of the corresponding wave band;
respectively forming metal bonding layers on each other electrode layer of the LED chip group and a common electrode communication layer in one LED chip;
grinding and thinning the substrate of the LED chip group and cutting along a cutting channel at the peripheral LED chip in the LED chip group;
and sequentially testing, sorting and packaging the LED chip sets of each waveband to form the LED display screen.
2. The method of claim 1, wherein the step of etching the transparent conductive layer to form mesa steps exposing the first semiconductor layer and scribe lines for cutting comprises:
carrying out photoetching on the transparent conducting layer to form a mask with a special pattern of the mesa, wherein the photoetching comprises gluing, exposing and developing operations;
removing the transparent conductive layer outside the mask by wet etching to expose the second semiconductor layer;
etching to expose the first semiconductor layer through ICP to form a mesa step, and removing the photoresist;
photoetching the surface of the epitaxial wafer to form an ISO special pattern mask;
and forming a cutting channel by ICP etching, and carrying out photoresist removing operation.
3. The method of claim 1, wherein the step of forming electrode layers of different polarities on the transparent conductive layer and the exposed first semiconductor layer of each epitaxial wafer comprises:
photoetching the surface of the epitaxial wafer to form a special pattern mask of the electrode layer;
and respectively forming electrode layers with different polarities on the transparent conductive layer and the exposed first semiconductor layer by metal evaporation through a metal evaporation process, and performing photoresist removing operation.
4. The method of claim 1, wherein the insulating reflective layer comprises an insulating protective layer and a reflective layer;
the step of forming the insulating reflecting layer on the epitaxial wafer and exposing the electrode layer comprises the following steps:
sequentially depositing an insulating protective layer and a reflecting layer on the epitaxial wafer;
photoetching the surface of the epitaxial wafer to form a special pattern mask of the insulating reflecting layer;
etching to expose the electrode layer by ICP, and removing photoresist.
5. The method as claimed in claim 1, wherein the step of forming a common electrode interconnection layer for connecting electrode layers of the same polarity on one of the electrode layers of at least two LED chips of the same wavelength band comprises:
photoetching the surfaces of at least two LED chips with the same wave band to form a special pattern mask of a common electrode communication layer;
and evaporating metal on one of the exposed electrode layers of each LED chip by a metal evaporation process to form a common electrode communication layer, so that the electrode layers of the same polarity of at least two LED chips with the same wave band are communicated through the common electrode communication layer, and performing photoresist removing operation.
6. The method of claim 1, wherein the step of forming metal bonding layers on each of the other electrode layers of the LED chip set and the common electrode communication layer of one of the LED chips comprises:
photoetching each LED chip of the LED chip group to form a special pattern mask of the metal bonding layer;
and respectively forming a metal bonding layer on the other electrode layer exposed by each LED chip and the common electrode communication layer in one of the LED chips by metal vapor deposition through a metal vapor deposition process, and performing photoresist removing operation.
7. The method for manufacturing a small-spacing LED display screen according to any one of claims 2-6, wherein the transparent conductive layer is an ITO transparent conductive layer, an FTO transparent conductive layer, a ZAO transparent conductive layer or a Ni micro-grid transparent conductive layer;
the metal composition of the electrode layer, the common electrode communication layer and the metal bonding layer comprises any one or combination of more of Cr, Al, Ti, Pt, Ni and Au;
the photoresist thickness corresponding to the photoetching is 2.5-10um, the exposure is 150-1000mj, and the developing time is 50-250 s.
8. An LED display screen for small pitch comprising:
the LED chip sets are sequentially arrayed and distributed and have different wave bands, and each LED chip set comprises a red LED chip set, a green LED chip set and a blue LED chip set;
the LED chip group consists of at least two LED chips, and each LED chip comprises a substrate, and an epitaxial layer, a transparent conducting layer, an electrode layer, an insulating reflecting layer, a common electrode communication layer and a metal bonding layer which are sequentially stacked on the substrate;
the epitaxial layer is including range upon range of in proper order first semiconductor layer, luminescent layer and the second semiconductor layer on the substrate, transparent conducting layer locates on the second semiconductor layer, the electrode layer is located respectively first semiconductor layer reaches on the transparent conducting layer, be equipped with on the insulating reflection stratum and expose the opening of electrode layer, common electrode UNICOM layer locates and exposes on one of them opening of electrode layer, and mutual UNICOM between the common electrode UNICOM layer in each LED chip, the metal bonding layer is located and is exposed on another opening of electrode layer, and still be equipped with on the common electrode UNICOM layer in one of them LED chip in the LED chipset the metal bonding layer.
9. The LED display screen of claim 8, wherein the metal components of the electrode layer, common electrode via layer and metal bonding layer comprise any one or more of Cr, Al, Ti, Pt, Ni, Au.
10. The LED display screen of claim 8, wherein the insulating reflective layer comprises an insulating protective layer and a reflective layer, the insulating protective layer comprising a SiN layer or SiO layer 2 A layer comprising an Ag reflective layer or a DBR reflective layer.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115832129A (en) * | 2023-02-22 | 2023-03-21 | 江西兆驰半导体有限公司 | Flip LED chip preparation method |
| CN115863498A (en) * | 2023-02-21 | 2023-03-28 | 江西兆驰半导体有限公司 | Preparation method of normally-installed LED chip |
| CN116154058A (en) * | 2023-04-19 | 2023-05-23 | 河北光兴半导体技术有限公司 | Preparation method of combined chip and combined chip |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115863498A (en) * | 2023-02-21 | 2023-03-28 | 江西兆驰半导体有限公司 | Preparation method of normally-installed LED chip |
| CN115863498B (en) * | 2023-02-21 | 2024-03-12 | 江西兆驰半导体有限公司 | Preparation method of forward-mounted LED chip |
| CN115832129A (en) * | 2023-02-22 | 2023-03-21 | 江西兆驰半导体有限公司 | Flip LED chip preparation method |
| CN116154058A (en) * | 2023-04-19 | 2023-05-23 | 河北光兴半导体技术有限公司 | Preparation method of combined chip and combined chip |
| CN116154058B (en) * | 2023-04-19 | 2023-08-15 | 河北光兴半导体技术有限公司 | Preparation method of combined chip and combined chip |
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