CN116137262A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

Info

Publication number
CN116137262A
CN116137262A CN202211311700.3A CN202211311700A CN116137262A CN 116137262 A CN116137262 A CN 116137262A CN 202211311700 A CN202211311700 A CN 202211311700A CN 116137262 A CN116137262 A CN 116137262A
Authority
CN
China
Prior art keywords
material layer
semiconductor chip
semiconductor device
conductive plate
outer periphery
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202211311700.3A
Other languages
English (en)
Inventor
鹤冈辽太郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Publication of CN116137262A publication Critical patent/CN116137262A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/492—Bases or plates or solder therefor
    • H01L23/4924—Bases or plates or solder therefor characterised by the materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4871—Bases, plates or heatsinks
    • H01L21/4878—Mechanical treatment, e.g. deforming
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H01L23/49844—Geometry or layout for devices being provided for in H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3201—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3205—Shape
    • H01L2224/32057—Shape in side view
    • H01L2224/32059—Shape in side view comprising protrusions or indentations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3205—Shape
    • H01L2224/3207—Shape of bonding interfaces, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32111—Disposition the layer connector being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32112—Disposition the layer connector being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32153—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/32175—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic
    • H01L2224/32187—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic the layer connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4801—Structure
    • H01L2224/48011—Length
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/832—Applying energy for connecting
    • H01L2224/83201—Compression bonding
    • H01L2224/83203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8384—Sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3736—Metallic materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1011—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3512—Cracking
    • H01L2924/35121—Peeling or delaminating

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Geometry (AREA)
  • Manufacturing & Machinery (AREA)
  • Materials Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Die Bonding (AREA)

Abstract

本发明提供一种半导体装置及其制造方法，该半导体装置能够防止在将片状的烧结材料层转印于半导体芯片时的烧结材料层的弯曲形状所引起的烧结材料层的接合强度的下降。具备：半导体芯片(3)；烧结材料层(2)，其与半导体芯片(3)的下表面接合，该烧结材料层(2)的厚度(t1)随着接近半导体芯片(3)的外周而变薄；以及导电板(11)，其具有与半导体芯片(3)的下表面相向的主表面，在该主表面设置有与烧结材料层(2)接触的凹部(11a)，该凹部(11a)的深度(d1)随着接近半导体芯片(3)的外周而变浅。

Description

半导体装置及其制造方法
技术领域
本发明涉及一种半导体装置(半导体模块)及其制造方法。
背景技术
关于以往的半导体模块，半导体芯片、绝缘电路基板以及散热基座利用焊料相互接合，最终经由热复合物安装于冷却片来进行使用。在半导体芯片与绝缘电路基板的接合中，主要实施的是焊接，但近年来，出于高耐热性、高散热性、高可靠性等目的，对使用了银(Ag)等金属的纳米粒子或者微米粒子的烧结接合技术进行了研究。
在烧结接合技术所使用的烧结材料中，有膏状的烧结材料(烧结膏)以及片状的烧结材料(烧结片)。使用金属掩模等将烧结膏涂布在绝缘电路基板上，并将烧结膏进行干燥来进行使用。烧结片在被转印于半导体芯片的下表面之后，以配置在绝缘电路基板上的方式接合。在使用烧结膏和烧结片中的任一种的情况下，通过进行加压和加热来使烧结材料烧结，从而将绝缘电路基板与半导体芯片接合。
专利文献1中公开了如下内容：通过在烧结片形成与半导体芯片的表面侧的凸部对应的凹部来抑制半导体芯片的破坏。专利文献2中公开了如下内容：在宽带隙材料底座设置凹部，向凹部填充银粉，在凹部的银粉上载置宽带隙芯片并进行烧结。专利文献3中公开了如下内容：基板的导电体的芯片搭载面包含进行粗化处理所得到的粗化区域，烧结金属层形成于粗化区域上。
专利文献4中公开了如下内容：在半导体芯片的与烧结接合材料接合的背面以及在陶瓷基板的与烧结接合材料接合的上表面的布线形成有多个球面状的凸部。专利文献5中公开了如下内容：半导体模块具备绝缘基板、形成于绝缘基板上的布线层、具有与布线层叠加地配置并且与布线层电连接的一个端子的半导体芯片、以及固定在布线层与半导体芯片之间并且将布线层与半导体芯片电连接的金属的烧结接合材料，在俯视时，布线层在比重叠的半导体芯片的外周靠内侧的位置具有槽部。
现有技术文献
专利文献
专利文献1：日本特开2021-002563号公报
专利文献2：日本特开2015-207747号公报
专利文献3：国际公开第2020/050077号
专利文献4：日本特开2018-156988号公报
专利文献5：日本特开2017-92168号公报
发明内容
发明要解决的问题
在将烧结片向半导体芯片转印的情况下，在橡胶等弹性体上隔着保护膜载置烧结片，并在烧结片上载置半导体芯片。然后，进行加热和加压由此利用弹性体的凹陷，并在半导体芯片的端部切断烧结片，从而向半导体芯片的下表面转印作为烧结片的一部分的烧结材料层。
然而，由于烧结片下的保护膜、橡胶的弯曲，被转印于半导体芯片的烧结材料层的端部会弯曲。在该状态下，当在绝缘电路基板上经由烧结材料层接合半导体芯片时，烧结材料层的弯曲的端部不会与绝缘电路基板接合而成为开口形状。因此，存在如下问题：容易从烧结材料层的与绝缘电路基板接合的面的外周产生裂纹，并且烧结材料层容易从绝缘电路基板剥离，接合强度下降。
鉴于上述问题，本发明的目的在于提供一种如下的半导体装置，其能够防止在将片状的烧结材料层转印于半导体芯片时的烧结材料层的弯曲形状所引起的烧结材料层的接合强度的下降。
用于解决问题的方案
本发明的一个方式的主旨在于提供一种半导体装置，具备：(a)半导体芯片；(b)烧结材料层，其与半导体芯片的下表面接合，该烧结材料层的厚度随着接近半导体芯片的外周而变薄；以及(c)导电板，其具有与半导体芯片的下表面相向的主表面，在该主表面设置有与烧结材料层接触的凹部，所述凹部的深度随着接近半导体芯片的外周而变浅。
本发明的其它方式的主旨在于提供一种半导体装置的制造方法，包括以下工序：(a)在导电板的主表面形成凹部；(b)在半导体芯片的下表面转印具有弯曲形状的烧结材料层；以及(c)使被转印于半导体芯片的烧结材料层与导电板的所述凹部相向，通过从半导体芯片的上表面侧进行加压和加热来使烧结材料层烧结，从而将导电板与半导体芯片接合。
发明的效果
根据本发明，能够提供一种能够防止在将片状的烧结材料层转印于半导体芯片时的烧结材料层的弯曲形状所引起的烧结材料层的接合强度的下降的半导体装置。
附图说明
图1是第一实施方式所涉及的半导体装置的截面图。
图2是第一实施方式所涉及的半导体装置的俯视图。
图3是从图2的A-A方向观察得到的截面图。
图4是第一实施方式所涉及的半导体装置的制造方法的概要图。
图5是第一实施方式所涉及的半导体装置的制造方法的接着图4的概要图。
图6是第一实施方式所涉及的半导体装置的制造方法的接着图5的概要图。
图7是比较例所涉及的半导体装置的截面图。
图8是第一实施方式所涉及的半导体装置的制造方法的接着图6的概要图。
图9是第一实施方式所涉及的半导体装置的制造方法的接着图8的概要图。
图10是第一实施方式所涉及的半导体装置的制造方法的接着图9的概要图。
图11是第一实施方式所涉及的半导体装置的制造方法的接着图10的概要图。
图12是第二实施方式所涉及的半导体装置的截面图。
图13是第三实施方式所涉及的半导体装置的截面图。
图14是第四实施方式所涉及的半导体装置的截面图。
图15是第五实施方式所涉及的半导体装置的截面图。
图16是第六实施方式所涉及的半导体装置的截面图。
图17是第七实施方式所涉及的半导体装置的截面图。
图18是第八实施方式所涉及的半导体装置的截面图。
具体实施方式
下面，参照附图来说明第一实施方式～第八实施方式。在附图的记载中，对相同或类似的部分标注相同或类似的附图标记，并且省略重复的说明。但是，附图是示意性的，有时厚度与平面尺寸的关系、各层的厚度的比率等与实际不同。另外，在附图相互之间也可能包含尺寸的关系、比率不同的部分。另外，以下所示的第一实施方式～第八实施方式例示了用于使本发明的技术思想具体化的装置、方法，本发明的技术思想并不是将结构部件的材质、形状、构造、配置等特定为下述的结构部件的材质、形状、构造、配置。
另外，下面的说明中的上下、左右等方向的定义只是为了便于说明的定义，并不限定本发明的技术思想。例如，如果将对象旋转90°进行观察，则将上下变换为左右来解读，如果旋转180°进行观察，则将上下进行反转来解读，这是不言而喻的。
(第一实施方式)
<半导体装置的结构>
如图1所示，第一实施方式所涉及的半导体装置(半导体模块)具备绝缘电路基板1、与绝缘电路基板1的主表面(上表面)相向地配置的功率半导体芯片(半导体芯片)3、以及配置于绝缘电路基板1与半导体芯片3之间的利用烧结材料构成的接合层(烧结材料层)2。
绝缘电路基板1例如可以是直接铜接合(DCB)基板、活性钎焊(AMB)基板等。绝缘电路基板1具备绝缘板10、配置于绝缘板10的上表面的导电板(电路板)11以及配置于绝缘板10的下表面的导电板(散热板)12。绝缘板10例如利用陶瓷基板、树脂绝缘基板构成，陶瓷基板是利用氧化铝(Al2O3)、氮化铝(AlN)、氮化硅(Si3N4)等构成的基板，树脂绝缘基板是使用了高分子材料等的基板。导电板11、12例如利用铜(Cu)箔、铝(Al)箔等导体箔构成。
烧结材料层2例如通过对包含金(Au)、银(Ag)或铜(Cu)等金属粒子和有机成分(粘合剂)的片状的烧结材料(烧结片)进行烧结来构成。金属粒子具有几nm～几μm左右的微细的粒径。例如，由于银(Ag)系的烧结材料能够在低温下接合并且在接合后成为与Ag的融点相同的融点这样的特征，因此无需提高接合温度而得到高耐热性且高可靠性的接合层。
半导体芯片3配置为与导电板11的主表面(上表面)相向。作为半导体芯片3，例如能够采用绝缘栅型双极晶体管(IGBT)、场效应晶体管(FET)、静电感应(SI)晶闸管、门极可关断(GTO)晶闸管、续流二极管(FWD)等。半导体芯片3例如也可以利用硅(Si)基板构成，或者也可以利用化合物半导体基板构成，化合物半导体基板利用碳化硅(SiC)、氮化镓(GaN)、氧化镓(Ga2O3)等宽带隙半导体构成。半导体芯片3的利用金(Au)等构成的下表面电极经由烧结材料层2来与导电板11接合。在图1中例示了1个半导体芯片3，但半导体芯片的数量能够根据半导体模块的电流容量等进行适当设定，也可以具有2个以上的半导体芯片。
以围住绝缘电路基板1及半导体芯片3的外周的方式配置有利用树脂等绝缘材料构成的壳体5。在壳体5的内侧填充有将烧结材料层2和半导体芯片3密封的密封构件7。作为密封构件7，例如能够使用硅胶、热固化性树脂等绝缘材料。在壳体5固定有外部端子4a、4b。半导体芯片3、导电板11以及外部端子4a、4b经由接合线6a、6b、6c来相互电连接。
绝缘电路基板1的下表面经由接合层13来与利用铜(Cu)等金属构成的散热基座8接合。散热基座8的下表面经由接合层14来与利用铜(Cu)等金属构成的散热片9接合。作为接合层13、14，例如能够使用烧结材料、焊料材料、热界面材料(Thermal InterfaceMaterial；TIM)。接合层13、14既可以利用与烧结材料层2相同的材料构成，也可以利用与烧结材料层2不同的材料构成。
图2是图1所示的第一实施方式所涉及的半导体装置中的绝缘电路基板1的导电板11和半导体芯片3的俯视图。如图2所示，半导体芯片3具有矩形的平面图案。半导体芯片3的尺寸例如为1mm×1mm以上且10mm×10mm以下左右，但不限定于此。烧结材料层2的与半导体芯片3接触的上表面具有矩形的平面图案，烧结材料层2的与半导体芯片3接触的上表面的外周与半导体芯片3的外周一致。此外，烧结材料层2的上表面的外周也可以位于比半导体芯片3的外周靠外侧的位置。
图3是从图2的A-A方向观察得到的截面图。如图3所示，在绝缘电路基板1的导电板11的主表面(上表面)设置有凹部11a。凹部11a的深度d1在凹部11a的中央侧相对较深，在凹部11a的外周侧相对较浅。凹部11a的深度d1在凹部11a的中央部最深，从凹部11a的中央部起随着接近外周侧而变浅。在第一实施方式所涉及的半导体装置中，凹部11a整体为曲面，并且整体呈弯曲形状。
烧结材料层2被设置为埋入凹部11a并且与凹部11a接触。烧结材料层2的与凹部11a接触的面成为与凹部11a的形状相同的形状，烧结材料层2的至少端部呈弯曲形状。烧结材料层2的厚度t1在半导体芯片3的中央侧相对较厚，在半导体芯片3的外周侧相对较薄。烧结材料层2的厚度t1在半导体芯片3的中央部最厚，从半导体芯片3的中央部起随着接近半导体芯片3的外周侧而变薄。在图3中，例示了烧结材料层2的厚度t1与凹部11a的深度d1相等的情况。
根据第一实施方式所涉及的半导体装置，烧结材料层2被设置为埋入导电板11的凹部11a并且与凹部11a接触，因此能够防止烧结材料层2的外周的裂纹的产生、剥离，能够防止接合强度的下降。并且，相比于将弯曲形状的烧结材料层2与平坦的导电板11接合的情况而言，烧结材料层2与导电板11的接合面积大，因此能够高效地将来自半导体芯片3的发热经由烧结材料层2向导电板11侧散热。由此，能够实现高耐热、高散热、高可靠性的半导体装置。
<半导体装置的制造方法>
接着，说明第一实施方式所涉及的半导体装置的制造方法(组装方法)。首先，如图4所示那样在冲压机的支承部31的上表面配置橡胶等弹性体32。然后，使用搬送机等在弹性体32的上表面隔着保护膜33载置作为片状的烧结材料的烧结片2x。然后，使用搬送机等在烧结片2x上载置半导体芯片3。
接着，利用冲压机的加压部35隔着无尘纸等缓冲材料34从半导体芯片3的上表面侧加压，来将半导体芯片3的下表面按压于烧结片2x。此外，也可以在从半导体芯片3的上表面侧加压时进行加热，使得容易转印烧结片2x。此时，如图5所示，弹性体32弯曲，同时保护膜33不断裂地弯曲，由此烧结片2x在半导体芯片3的外周被切断。
接着，使冲压机的加压部35上升，从冲压机拆下半导体芯片3。如图6所示，在半导体芯片3的下表面转印有利用烧结片2x的一部分构成的烧结材料层2。烧结材料层2具有与在从半导体芯片3的上表面侧对半导体芯片3进行了加压时的弹性体32、保护膜33的弯曲形状相应的弯曲形状，烧结材料层2的至少外周部(端部)弯曲。烧结材料层2的厚度在半导体芯片3的中央侧相对较厚，在半导体芯片3的外周侧相对较薄。烧结材料层2的厚度从半导体芯片3的中央侧起随着接近半导体芯片3的外周侧而变薄。
在此，考虑将图6所示的转印有烧结材料层2的半导体芯片3接合到绝缘电路基板1的平坦的导电板11上的情况。在该情况下，如图7所示，通过从半导体芯片3的上表面侧进行加热和加压来将绝缘电路基板1的平坦的导电板11与半导体芯片3经由烧结材料层2接合。此时，由于烧结材料层2的外周部2y弯曲，因此烧结材料层2的外周部2y不与导电板11接合，而成为开口形状。其结果，容易从烧结材料层2的外周部2y的与导电板11的接合部产生裂纹，也容易发生烧结材料层2的剥离，因此接合强度下降。
因此，在第一实施方式所涉及的半导体装置的制造方法中，预先在导电板11形成凹部11a。例如，准备如图8所示那样的具有加工部36a的治具36，加工部36a具有与图6所示的烧结材料层2的弯曲形状对应的形状。而且，使治具36的加工部36a与平坦的导电板11相向，并且如图9所示那样从治具36的加工部36a的上侧加压，从而对平坦的导电板11的搭载半导体芯片3的预定的位置加压。之后，拆下治具36由此如图10所示那样在导电板11形成凹部11a。
凹部11a具有与烧结材料层2的弯曲形状对应并且与烧结材料层2的弯曲形状大致相同的弯曲形状。凹部11a的形状可以不必与烧结材料层2的形状相同。凹部11a的形状只要是以在将导电板11与半导体芯片3经由烧结材料层2接合时使烧结材料层2与凹部11a接触的程度来与烧结材料层2的弯曲形状对应的形状即可。
此外，作为在平坦的导电板11形成凹部11a的方法，除了使用治具36进行加压以外，还能够采用研磨、激光照射、切削、蚀刻等各种方法。另外，也可以将平坦的导电板11与绝缘板10接合来制作绝缘电路基板1，之后在平坦的导电板11形成凹部11a，或者也可以在平坦的导电板11形成凹部11a，之后将形成有凹部11a的导电板11与绝缘板10接合来制作绝缘电路基板1。
接着，使用搬送机等如图11所示那样将转印有烧结材料层2的半导体芯片3搭载于绝缘电路基板1的导电板11的凹部11a。然后，通过利用冲压机的模具、安装于模具的硅(Si)橡胶等构成的加压部来从半导体芯片3的上表面侧进行加压。在半导体芯片3被加压的状态下，以烧结材料层2的烧结温度以上的温度进行加热，由此使烧结材料层2发生烧结反应。例如，加压力设定为1MPa以上且60MPa以下左右，加热温度设定为150℃以上且350℃以下左右，加热时间设定为1分钟以上且5分钟以下左右。其结果，如图2及图3所示，烧结材料层2与导电板11的凹部11a接合，绝缘电路基板1与半导体芯片3经由烧结材料层2接合。
之后，通过如下的通常的工艺来完成图1所示的第一实施方式所涉及的半导体装置：在绝缘电路基板1和半导体芯片3的周围配置壳体5，利用接合线6a、6b、6c等将绝缘电路基板1、半导体芯片3以及外部端子4a、4b连接，并利用密封构件7进行密封等。
根据第一实施方式所涉及的半导体装置的制造方法，通过预先在平坦的导电板11形成凹部11a后在凹部11a埋入具有弯曲形状的烧结材料层2，能够减少或消除烧结材料层2的开口形状，能够防止烧结材料层2的外周部未与导电板11接合。因此，能够防止烧结材料层2的外周部的裂纹的产生、剥离，能够防止接合强度的下降。
并且，通过烧结材料层2与导电板11的凹部11a接触，相比于烧结材料层2与平坦的导电板11接触的情况而言，烧结材料层2与导电板11的接合面积变大，因此能够将来自半导体芯片3的热经由烧结材料层2高效地散热。由此，能够实现高耐热、高散热、高可靠性的半导体装置。
(第二实施方式)
第二实施方式所涉及的半导体装置与第一实施方式所涉及的半导体装置的结构的不同之处在于，如图12所示，在导电板11的凹部11a的外周设置有突起部11b。突起部11b能够由利用治具等进行凹部11a的加工时的导电板11的残渣形成。突起部11b例如以围住凹部11a的外周的方式设置为环状。
第二实施方式所涉及的半导体装置的其它结构与第一实施方式所涉及的半导体装置的结构相同，因此省略重复的说明。第二实施方式所涉及的半导体装置能够通过与第一实施方式所涉及的半导体装置的制造方法相同的过程实现。
根据第二实施方式所涉及的半导体装置，与第一实施方式所涉及的半导体装置的结构同样，烧结材料层2被设置为埋入导电板11的凹部11a并且与凹部11a接触，因此能够防止烧结材料层2的外周的裂纹的产生、剥离。并且，由于在导电板11的凹部11a的外周设置有突起部11b，因此能够防止半导体芯片3的位置偏移。
(第三实施方式)
第三实施方式所涉及的半导体装置与图3所示的第一实施方式所涉及的半导体装置的结构的不同之处在于，如图13所示，导电板11的凹部11a具有平坦的底面111。导电板11的凹部11a具有位于半导体芯片3的中央侧的平坦的底面111以及位于半导体芯片3的外周侧且与底面111连续的作为曲面的侧面112。
第三实施方式所涉及的半导体装置的其它结构与第一实施方式所涉及的半导体装置的结构相同，因此省略重复的说明。第三实施方式所涉及的半导体装置能够通过与第一实施方式所涉及的半导体装置的制造方法相同的过程实现。在将弯曲形状的烧结材料层2转印于半导体芯片3之后，在将半导体芯片3与导电板11经由烧结材料层2接合时，通过加压使烧结材料层2变形，从而能够成为与凹部11a接触的形状。
根据第三实施方式所涉及的半导体装置，在导电板11的凹部11a具有平坦的底面111的情况下，与第一实施方式所涉及的半导体装置的结构同样地，烧结材料层2也被设置为埋入导电板11的凹部11a并且与凹部11a接触，因此能够防止烧结材料层2的外周的裂纹的产生、剥离。
(第四实施方式)
第四实施方式所涉及的半导体装置与图3所示的第一实施方式所涉及的半导体装置的结构的不同之处在于，如图14所示，导电板11的凹部11a具有上表面侧(半导体芯片3侧)的上底比下表面侧(导电板11侧)的下底长的大致梯形(锥形)的截面形状。导电板11的凹部11a具有位于半导体芯片3的中央侧的平坦的底面111以及位于半导体芯片3的外周侧且与底面111连续的作为平面(斜面)的侧面113。
第四实施方式所涉及的半导体装置的其它结构与第一实施方式所涉及的半导体装置的结构相同，因此省略重复的说明。第四实施方式所涉及的半导体装置能够通过与第一实施方式所涉及的半导体装置的制造方法相同的过程实现。在将弯曲形状的烧结材料层2转印于半导体芯片3之后，在将半导体芯片3与导电板11经由烧结材料层2接合时，通过加压使烧结材料层2变形，从而能够成为与凹部11a接触的形状。
根据第四实施方式所涉及的半导体装置，在导电板11的凹部11a具有大致梯形的截面形状的情况下，与第一实施方式所涉及的半导体装置的结构同样地，烧结材料层2也被设置为埋入导电板11的凹部11a并且与凹部11a接触，因此能够防止烧结材料层2的外周的裂纹的产生、剥离。
(第五实施方式)
第五实施方式所涉及的半导体装置与图3所示的第一实施方式所涉及的半导体装置的结构的不同之处在于，如图15所示，导电板11的凹部11a及烧结材料层2的宽度W2比半导体芯片3的宽度W1宽。烧结材料层2的外周位于比半导体芯片3的外周靠外侧的位置。
第五实施方式所涉及的半导体装置的其它结构与第一实施方式所涉及的半导体装置的结构相同，因此省略重复的说明。第五实施方式所涉及的半导体装置能够通过与第一实施方式所涉及的半导体装置的制造方法相同的过程实现。例如，在向半导体芯片3转印烧结材料层2时，能够以烧结材料层2的外周位于比半导体芯片3的外周靠外侧的位置的方式转印烧结材料层2。
根据第五实施方式所涉及的半导体装置，与第一实施方式所涉及的半导体装置的结构同样地，烧结材料层2被设置为埋入导电板11的凹部11a并且与凹部11a接触，因此能够防止烧结材料层2的外周的裂纹的产生、剥离。
(第六实施方式)
第六实施方式所涉及的半导体装置与第一实施方式所涉及的半导体装置的结构的不同之处在于，如图16所示，导电板11的凹部11a的深度d1比烧结材料层2的厚度t1浅，并且导电板11的凹部11a的宽度W3比半导体芯片3的宽度W1窄。烧结材料层2比导电板11的主表面向上方突出厚度(t1-d1)，烧结材料层2的一部分设置于导电板11的主表面上。
第六实施方式所涉及的半导体装置的其它结构与第一实施方式所涉及的半导体装置的结构相同，因此省略重复的说明。第六实施方式所涉及的半导体装置能够通过与第一实施方式所涉及的半导体装置的制造方法相同的过程实现。
根据第六实施方式所涉及的半导体装置，与第一实施方式所涉及的半导体装置的结构同样地，烧结材料层2的一部分被设置为埋入导电板11的凹部11a并且与凹部11a接触，因此能够防止烧结材料层2的外周的裂纹的产生、剥离。并且，半导体芯片3的下表面与导电板11的主表面分开，因此能够防止半导体芯片3与导电板11的主表面的接触所导致的破损。
(第七实施方式)
第七实施方式所涉及的半导体装置与图3所示的第一实施方式所涉及的半导体装置的结构的不同之处在于，如图17所示，导电板11的凹部11a的深度d1比烧结材料层2的厚度t1浅，并且导电板11的凹部11a的宽度W4比半导体芯片3的宽度W1宽。烧结材料层2比导电板11的主表面向上方突出厚度(t1-d1)，烧结材料层2的一部分设置于导电板11的主表面上。
第七实施方式所涉及的半导体装置的其它结构与第一实施方式所涉及的半导体装置的结构相同，因此省略重复的说明。第七实施方式所涉及的半导体装置能够通过与第一实施方式所涉及的半导体装置的制造方法相同的过程实现。例如，在向半导体芯片3转印烧结材料层2时，能够以烧结材料层2的外周位于比半导体芯片3的外周靠外侧的位置的方式转印烧结材料层2。
根据第七实施方式所涉及的半导体装置，与第一实施方式所涉及的半导体装置的结构同样地，烧结材料层2的一部分被设置为埋入导电板11的凹部11a并且与凹部11a接触，因此能够防止烧结材料层2的外周的裂纹的产生、剥离。并且，半导体芯片3的下表面与导电板11的主表面分开，因此能够防止半导体芯片3与导电板11的主表面的接触所导致的破损。
(第八实施方式)
第八实施方式所涉及的半导体装置与图3所示的第一实施方式所涉及的半导体装置的结构的不同之处在于，如图18所示，与绝缘电路基板1的导电板11不同的导电板21接合于烧结材料层2。导电板21例如是利用铜(Cu)等导电材料构成的散热用的导电块(散热器)。导电板21的下表面经由焊料等接合层22来与绝缘电路基板1的导电板11接合。在导电板21的主表面(上表面)设置有凹部21a。凹部21a的形状与图3所示的绝缘电路基板1的导电板11的凹部11a的形状相同。
第八实施方式所涉及的半导体装置的其它结构与第一实施方式所涉及的半导体装置的结构相同，因此省略重复的说明。第八实施方式所涉及的半导体装置能够通过与第一实施方式所涉及的半导体装置的制造方法相同的过程实现。
根据第八实施方式所涉及的半导体装置，在与绝缘电路基板1的导电板11不同的导电板21设置凹部21a的情况下，烧结材料层2也被设置为埋入导电板21的凹部21a并且与凹部21a接触，因此能够防止烧结材料层2的外周的裂纹的产生、剥离。
(其它实施方式)
如上述那样，本发明通过第一实施方式～第八实施方式进行了记载，但不应理解为构成本公开的一部分的论述及附图限定本发明。对于本领域技术人员而言，根据本公开，各种代替实施方式、实施例以及运用技术是明了的。
例如，作为第一实施方式～第八实施方式所涉及的半导体装置，例示了经由接合线6a、6b、6c来连接半导体芯片3的结构，但不限定于此。例如，也能够应用于如下结构的半导体装置：在半导体芯片3的上方设置在印刷基板插入有销状的柱电极的植入基板，并且将半导体芯片3与柱电极连接。
另外，能够在不产生矛盾的范围内将第一实施方式～第八实施方式所分别公开的结构进行适当组合。这样，本发明包含在此未记载的各种实施方式等，这是不言而喻的。因而，本发明的技术范围仅由根据上述的说明而言妥当的权利要求书所涉及的发明特定事项决定。
附图标记说明
1：绝缘电路基板；2：接合层(烧结材料层)；2x：烧结片；2y：外周部；3：功率半导体芯片(半导体芯片)；4a、4b：外部端子；5：壳体；6a、6b、6c：接合线；7：密封构件；8：散热基座；9：散热片；10：绝缘板；11、12：导电板；11a：凹部；11b：突起部；13、14：接合层；21：导电板；21a：凹部；22：接合层；31：支承部；32：弹性体；33：保护膜；34：缓冲材料；35：加压部；36：治具；36a：加工部；111：底面；112、113：侧面。

Claims (16)

1.一种半导体装置，其特征在于，具备：
半导体芯片；
烧结材料层，其与所述半导体芯片的下表面接合，所述烧结材料层的厚度随着接近所述半导体芯片的外周而变薄；以及
导电板，其具有与所述半导体芯片的下表面相向的主表面，在该主表面设置有与所述烧结材料层接触的凹部，所述凹部的深度随着接近所述半导体芯片的外周而变浅。
2.根据权利要求1所述的半导体装置，其特征在于，
所述凹部的至少端部是曲面。
3.根据权利要求1或2所述的半导体装置，其特征在于，
所述凹部具有平坦的底面。
4.根据权利要求1所述的半导体装置，其特征在于，
所述凹部具有锥形的截面形状。
5.根据权利要求1～4中的任一项所述的半导体装置，其特征在于，
所述烧结材料层的外周与所述半导体芯片的外周一致。
6.根据权利要求1～4中的任一项所述的半导体装置，其特征在于，
所述烧结材料层的外周设置于比所述半导体芯片的外周靠外侧的位置。
7.根据权利要求1～6中的任一项所述的半导体装置，其特征在于，
所述凹部的外周与所述半导体芯片的外周一致。
8.根据权利要求1～6中的任一项所述的半导体装置，其特征在于，
所述凹部的外周设置于比所述半导体芯片的外周靠外侧的位置。
9.根据权利要求1～6中的任一项所述的半导体装置，其特征在于，
所述凹部的外周设置于比所述半导体芯片的外周靠内侧的位置。
10.根据权利要求1～9中的任一项所述的半导体装置，其特征在于，
所述烧结材料层的厚度与所述凹部的深度一致。
11.根据权利要求1～9中的任一项所述的半导体装置，其特征在于，
所述烧结材料层的厚度比所述凹部的深度厚，所述烧结材料层的一部分设置于所述主表面上。
12.根据权利要求1～11中的任一项所述的半导体装置，其特征在于，
在所述导电板的所述凹部的外周设置有突起部。
13.根据权利要求1～12中的任一项所述的半导体装置，其特征在于，
所述导电板是绝缘电路基板的一部分。
14.根据权利要求1～12中的任一项所述的半导体装置，其特征在于，
所述导电板是导电块，所述导电块设置于绝缘电路基板上。
15.根据权利要求1～14中的任一项所述的半导体装置，其特征在于，
所述导电板由以铜为主要成分的材料构成。
16.一种半导体装置的制造方法，其特征在于，包括以下工序：
在导电板的主表面形成凹部；
在半导体芯片的下表面转印具有弯曲形状的烧结材料层；以及
使被转印于所述半导体芯片的所述烧结材料层与所述导电板的所述凹部相向，通过从所述半导体芯片的上表面侧进行加压和加热来使所述烧结材料层烧结，从而将所述导电板与所述半导体芯片接合。
CN202211311700.3A 2021-11-16 2022-10-25 半导体装置及其制造方法 Pending CN116137262A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2021-186511 2021-11-16
JP2021186511A JP2023073819A (ja) 2021-11-16 2021-11-16 半導体装置及びその製造方法

Publications (1)

Publication Number Publication Date
CN116137262A true CN116137262A (zh) 2023-05-19

Family

ID=86324085

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202211311700.3A Pending CN116137262A (zh) 2021-11-16 2022-10-25 半导体装置及其制造方法

Country Status (3)

Country Link
US (1) US20230154882A1 (zh)
JP (1) JP2023073819A (zh)
CN (1) CN116137262A (zh)

Also Published As

Publication number Publication date
US20230154882A1 (en) 2023-05-18
JP2023073819A (ja) 2023-05-26

Similar Documents

Publication Publication Date Title
CN107615464B (zh) 电力用半导体装置的制造方法以及电力用半导体装置
JP2021197447A (ja) 半導体装置
EP2889902B1 (en) Electric power semiconductor device
EP3690938B1 (en) Semiconductor device and production method therefor
CN110383464B (zh) 半导体装置
CN111276447A (zh) 双侧冷却功率模块及其制造方法
US20180158762A1 (en) Semiconductor device
EP3739624A1 (en) Semiconductor arrangement with a compressible contact element encapsulated between two carriers and corresponding manufacturing method
KR102588854B1 (ko) 파워모듈 및 그 제조방법
CN112530915B (zh) 半导体装置
JP7175095B2 (ja) 半導体装置
CN116137262A (zh) 半导体装置及其制造方法
CN111937127A (zh) 功率半导体芯片上的材料减少的金属板
US20220005708A1 (en) Base Plate for a Semiconductor Module Arrangement and Method for Producing a Base Plate
US10236244B2 (en) Semiconductor device and production method therefor
CN116529876A (zh) 半导体装置
WO2023286432A1 (ja) 半導体装置
CN113498273A (zh) 半导体装置的制造方法、半导体装置以及按压装置
US20230369276A1 (en) Semiconductor device and method of manufacturing the same
US11887933B2 (en) Manufacturing method of semiconductor device
US20230132056A1 (en) Semiconductor device and method for manufacturing the same
KR102465954B1 (ko) 가압형 반도체 패키지
US20230298984A1 (en) Semiconductor device and method for manufacturing semiconductor device
JP7492375B2 (ja) 半導体装置
EP4148777A1 (en) Semiconductor device

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication